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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-01 08:54:14 -04:00
+ New feature added: Task notifications.
+ Optimise Cortex-M4F ports by inlining some critical section macros. + Original ports used a #define to set the path to portmacro.h - that method has been obsolete for years and now all the old definitions have been moved into a separate header files called deprecated_definitions.h. + Cortex-M port now check the active vector bits against 0xff when determining if a function is called from an interrupt - previously only a subset of the bits (0x1f) were checked. + Add in new standard demo/test files TaskNotify.c/h and include the files in the simulator demos. + Update trace recorder code, and some demos to use the new version (more to do). + Introduce uxTaskPriorityGetFromISR(). + Minor typo corrections. + Update MingW simulator demo to match the MSVC simulator demo.
This commit is contained in:
Richard Barry
parent
ca22607d14
commit
85fb1cc024
65 changed files with 5524 additions and 4527 deletions
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@ -167,8 +167,8 @@ the CPU itself before modifying certain hardware registers. */
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{ \
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portCPU_IRQ_DISABLE(); \
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portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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__asm( "DSB \n" \
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"ISB \n" ); \
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__asm volatile ( "DSB \n" \
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"ISB \n" ); \
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portCPU_IRQ_ENABLE(); \
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}
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@ -114,7 +114,7 @@ FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
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#define portPRIGROUP_SHIFT ( 8UL )
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/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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#define portVECTACTIVE_MASK ( 0x1FUL )
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#define portVECTACTIVE_MASK ( 0xFFUL )
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/* Constants required to set up the initial stack. */
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#define portINITIAL_XPSR ( 0x01000000UL )
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@ -111,7 +111,7 @@
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#define portPRIGROUP_SHIFT ( 8UL )
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/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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#define portVECTACTIVE_MASK ( 0x1FUL )
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#define portVECTACTIVE_MASK ( 0xFFUL )
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/* Constants required to manipulate the VFP. */
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#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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@ -384,27 +384,13 @@ void vPortEndScheduler( void )
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}
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/*-----------------------------------------------------------*/
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void vPortYield( void )
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{
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/* Set a PendSV to request a context switch. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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/* Barriers are normally not required but do ensure the code is completely
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within the specified behaviour for the architecture. */
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__asm volatile( "dsb" );
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__asm volatile( "isb" );
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}
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/*-----------------------------------------------------------*/
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void vPortEnterCritical( void )
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{
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portDISABLE_INTERRUPTS();
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uxCriticalNesting++;
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__asm volatile( "dsb" );
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__asm volatile( "isb" );
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/* This is not the interrupt safe version of the enter critical function so
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assert() if it is being called from an interrupt context. Only API
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assert() if it is being called from an interrupt context. Only API
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functions that end in "FromISR" can be used in an interrupt. Only assert if
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the critical nesting count is 1 to protect against recursive calls if the
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assert function also uses a critical section. */
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@ -426,37 +412,6 @@ void vPortExitCritical( void )
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}
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/*-----------------------------------------------------------*/
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__attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )
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{
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__asm volatile \
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( \
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" mrs r0, basepri \n" \
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" mov r1, %0 \n" \
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" msr basepri, r1 \n" \
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" bx lr \n" \
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:: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \
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);
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/* This return will not be reached but is necessary to prevent compiler
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warnings. */
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return 0;
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}
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/*-----------------------------------------------------------*/
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__attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )
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{
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__asm volatile \
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( \
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" msr basepri, r0 \n" \
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" bx lr \n" \
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:::"r0" \
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);
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/* Just to avoid compiler warnings. */
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( void ) ulNewMaskValue;
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}
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/*-----------------------------------------------------------*/
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void xPortPendSVHandler( void )
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{
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/* This is a naked function. */
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@ -480,6 +435,8 @@ void xPortPendSVHandler( void )
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" stmdb sp!, {r3} \n"
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" mov r0, %0 \n"
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" msr basepri, r0 \n"
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" dsb \n"
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" isb \n"
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" bl vTaskSwitchContext \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"
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@ -109,25 +109,21 @@ typedef unsigned long UBaseType_t;
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#define portBYTE_ALIGNMENT 8
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/*-----------------------------------------------------------*/
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/* Scheduler utilities. */
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extern void vPortYield( void );
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#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portYIELD() vPortYield()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
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#define portYIELD() vPortYield()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield()
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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extern uint32_t ulPortSetInterruptMask( void );
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extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
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#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
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#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
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#define portENABLE_INTERRUPTS() vPortClearInterruptMask(0)
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#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x)
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#define portDISABLE_INTERRUPTS() ulPortRaiseBASEPRI()
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#define portENABLE_INTERRUPTS() vPortSetBASEPRI(0)
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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@ -188,6 +184,53 @@ not necessary for to use this port. They are defined so the common demo files
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/* portNOP() is not required by this port. */
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#define portNOP()
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#ifndef portFORCE_INLINE
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#define portFORCE_INLINE inline __attribute__(( always_inline))
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#endif
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/*-----------------------------------------------------------*/
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portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
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{
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uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
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__asm volatile
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(
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" mrs %0, basepri \n" \
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" mov %1, %2 \n" \
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" msr basepri, %1 \n" \
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" isb \n" \
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" dsb \n" \
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:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
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);
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/* This return will not be reached but is necessary to prevent compiler
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warnings. */
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return ulOriginalBASEPRI;
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}
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/*-----------------------------------------------------------*/
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portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
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{
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__asm volatile
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(
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" msr basepri, %0 " :: "r" ( ulNewMaskValue )
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);
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}
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/*-----------------------------------------------------------*/
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portFORCE_INLINE static void vPortYield( void )
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{
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/* Set a PendSV to request a context switch. */
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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/* Barriers are normally not required but do ensure the code is completely
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within the specified behaviour for the architecture. */
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__asm volatile( "dsb" );
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__asm volatile( "isb" );
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}
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#ifdef __cplusplus
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}
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#endif
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@ -217,7 +217,7 @@ typedef struct PORT_REGISTER_DUMP
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/* The human readable name of the task that was running at the time the
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exception occurred. This is the name that was given to the task when the
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task was created using the FreeRTOS xTaskCreate() API function. */
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int8_t *pcCurrentTaskName;
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char *pcCurrentTaskName;
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/* The handle of the task that was running a the time the exception
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occurred. */
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