Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation.

FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h

@@ -205,5 +205,7 @@ number of bits implemented by the interrupt controller. */
 #define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
 #define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
 #endif /* PORTMACRO_H */
 

FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h

@@ -202,5 +202,7 @@ number of bits implemented by the interrupt controller. */
 #define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
 #define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
 #endif /* PORTMACRO_H */
 

FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h

@@ -107,6 +107,8 @@ extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__((naked)
 
 #define portNOP()
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
 #ifdef __cplusplus
 }
 #endif

FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h

@@ -233,6 +233,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }

FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h

@@ -291,6 +291,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }

FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h

@@ -233,6 +233,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }

FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h

@@ -291,6 +291,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }

FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h

@@ -237,6 +237,7 @@ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
 }
 /*-----------------------------------------------------------*/
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
 
 #ifdef __cplusplus
 }

FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h

@@ -189,5 +189,7 @@ number of bits implemented by the interrupt controller. */
 #define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
 #define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
 #endif /* PORTMACRO_H */
 

FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h

@@ -164,6 +164,8 @@ void vPortTaskUsesFPU( void );
 #define portNOP() __asm volatile( "NOP" )
 #define portINLINE __inline
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
 #ifdef __cplusplus
 	} /* extern C */
 #endif

FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h

@@ -144,6 +144,8 @@ not necessary for to use this port.  They are defined so the common demo files
 	#define portFORCE_INLINE inline __attribute__(( always_inline))
 #endif
 
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
 #ifdef __cplusplus
 }
 #endif