aarch64: Rename ARM_CA53_64_BIT/_SRE to Arm_AARCH64/_SRE (#822)

The Cortex-A53 ports are generic and can be used as a starting point
for other Armv8-A application processors. Therefore, rename
`ARM_CA53_64_BIT` to `Arm_AARCH64` and `ARM_CA53_64_BIT_SRE` to
`Arm_AARCH64_SRE`.

With this renaming, existing projects that use old port, should
migrate to renamed port as follows:

* `ARM_CA53_64_BIT` -> `Arm_AARCH64`
* `ARM_CA53_64_BIT_SRE` -> `Arm_AARCH64_SRE`

Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>

portable/GCC/ARM_CA53_64_BIT/README.md

@@ -0,0 +1,16 @@
+# ARM_CA53_64_BIT port
+
+Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
+Arm Cortex-A53 processor.
+
+* ARM_CA53_64_BIT
+    * Memory mapped interace to access Arm GIC registers
+
+This port is generic and can be used as a starting point for other Armv8-A
+application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as
+`Arm_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`,
+should migrate to renamed port `Arm_AARCH64`.
+
+**NOTE**
+
+This port uses memory mapped interace to access Arm GIC registers.

portable/GCC/ARM_CA53_64_BIT_SRE/README.md

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+# ARM_CA53_64_BIT_SRE port
+
+Initial port to support Armv8-A architecture in FreeRTOS kernel was written for
+Arm Cortex-A53 processor.
+
+* ARM_CA53_64_BIT_SRE
+    * System Register interace to access Arm GIC registers
+
+This port is generic and can be used as a starting point for other Armv8-A
+application processors. Therefore, the port `Arm_AARCH64_SRE` is renamed as
+`Arm_AARCH64_SRE`. The existing projects that use old port `Arm_AARCH64_SRE`,
+should migrate to renamed port `Arm_AARCH64_SRE`.
+
+**NOTE**
+
+This port uses System Register interace to access Arm GIC registers.

portable/GCC/Arm_AARCH64/README.md

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+# Armv8-A architecture support
+
+The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
+Execution states, known as AArch64 and AArch32 respectively. The AArch64
+Execution state supports the A64 instruction set. It holds addresses in 64-bit
+registers and allows instructions in the base instruction set to use 64-bit
+registers for their processing.
+
+The AArch32 Execution state is a 32-bit Execution state that preserves
+backwards compatibility with the Armv7-A architecture, enhancing that profile
+so that it can support some features included in the AArch64 state. It supports
+the T32 and A32 instruction sets. Follow the
+[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
+for more information.
+
+## Arm_AARCH64 port
+
+This port adds support for Armv8-A architecture AArch64 execution state.
+This port is generic and can be used as a starting point for Armv8-A
+application processors.
+
+* Arm_AARCH64
+    * Memory mapped interace to access Arm GIC registers

portable/GCC/Arm_AARCH64_SRE/README.md

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+# Armv8-A architecture support
+
+The Armv8-A architecture introduces the ability to use 64-bit and 32-bit
+Execution states, known as AArch64 and AArch32 respectively. The AArch64
+Execution state supports the A64 instruction set. It holds addresses in 64-bit
+registers and allows instructions in the base instruction set to use 64-bit
+registers for their processing.
+
+The AArch32 Execution state is a 32-bit Execution state that preserves
+backwards compatibility with the Armv7-A architecture, enhancing that profile
+so that it can support some features included in the AArch64 state. It supports
+the T32 and A32 instruction sets. Follow the
+[link](https://developer.arm.com/Architectures/A-Profile%20Architecture)
+for more information.
+
+## Arm_AARCH64_SRE port
+
+This port adds support for Armv8-A architecture AArch64 execution state.
+This port is generic and can be used as a starting point for Armv8-A
+application processors.
+
+* Arm_AARCH64_SRE
+    * System Register interace to access Arm GIC registers