mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-06-05 20:09:05 -04:00
Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode.
This commit is contained in:
Richard Barry
parent
101806906d
commit
8285ca6b5f
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@ -41,7 +41,7 @@
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@ -85,9 +85,9 @@
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@ -97,6 +97,12 @@
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor.1853992692" name="Use preprocessor" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/FreeRTOS_Source/portable/GCC/RISC-V-RV32/CLINT}""/>
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</tool>
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@ -11,7 +11,7 @@
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<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
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<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-564858745062802889" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
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<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="247273655846757705" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
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<language-scope id="org.eclipse.cdt.core.gcc"/>
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@ -144,4 +144,8 @@ header file. */
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#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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#define handle_m_ext_interrupt vPortHandleInterrupt
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#endif /* FREERTOS_CONFIG_H */
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@ -1,17 +1,17 @@
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/*******************************************************************************
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* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
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*
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*
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* file name : microsemi-riscv-igloo2.ld
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* Mi-V soft processor linker script for creating a SoftConsole downloadable
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* image executing in eNVM.
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*
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*
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* This linker script assumes that the eNVM is connected at on the Mi-V soft
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* processor memory space.
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* processor memory space.
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*
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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@ -24,19 +24,19 @@ MEMORY
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RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */
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RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
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STACK_SIZE = 2k; /* needs to be calculated for your application */
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STACK_SIZE = 2k; /* needs to be calculated for your application */
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HEAP_SIZE = 2k; /* needs to be calculated for your application */
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SECTIONS
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{
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.text : ALIGN(0x10)
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{
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KEEP (*(SORT_NONE(.text.entry)))
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*(.text .text.* .gnu.linkonce.t.*)
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*(.plt)
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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@ -45,12 +45,12 @@ SECTIONS
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*crtend.o(.dtors))
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@ -66,14 +66,14 @@ SECTIONS
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(0x10);
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} >envm
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/* short/global data section */
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.sdata : ALIGN(0x10)
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{
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__sdata_load = LOADADDR(.sdata);
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__sdata_start = .;
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__sdata_start = .;
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PROVIDE( __global_pointer$ = . + 0x800);
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*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
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*(.srodata*)
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@ -84,9 +84,9 @@ SECTIONS
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/* data section */
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.data : ALIGN(0x10)
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{
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{
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@ -103,10 +103,10 @@ SECTIONS
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. = ALIGN(0x10);
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__sbss_end = .;
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} > ram
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/* sbss section */
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.bss : ALIGN(0x10)
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__bss_start = .;
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*(.shbss)
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@ -117,7 +117,7 @@ SECTIONS
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/* End of uninitialized data segment */
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_end = .;
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.heap : ALIGN(0x10)
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{
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__heap_start = .;
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@ -126,13 +126,14 @@ SECTIONS
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. = ALIGN(0x10);
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_heap_end = __heap_end;
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} > ram
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.stack : ALIGN(0x10)
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{
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__stack_bottom = .;
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. += STACK_SIZE;
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__stack_top = .;
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_sp = .;
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__freertos_irq_stack_top = .;
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} > ram
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}
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@ -1,10 +1,10 @@
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/*******************************************************************************
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* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
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*
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*
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* file name : microsemi-riscv-ram.ld
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* Mi-V soft processor linker script for creating a SoftConsole downloadable
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* debug image executing in SRAM.
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*
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*
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* This linker script assumes that the SRAM is connected at on the Mi-V soft
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* processor memory space. The start address and size of the memory space must
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* be correct as per the Libero design.
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@ -12,7 +12,7 @@
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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@ -24,19 +24,19 @@ MEMORY
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RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */
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RAM_SIZE = 512k; /* Must be the same value MEMORY region ram LENGTH above. */
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STACK_SIZE = 64k; /* needs to be calculated for your application */
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STACK_SIZE = 64k; /* needs to be calculated for your application */
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HEAP_SIZE = 64k; /* needs to be calculated for your application */
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SECTIONS
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{
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.text : ALIGN(0x10)
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{
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KEEP (*(SORT_NONE(.text.entry)))
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||||
KEEP (*(SORT_NONE(.text.entry)))
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||||
. = ALIGN(0x10);
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*(.text .text.* .gnu.linkonce.t.*)
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*(.plt)
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. = ALIGN(0x10);
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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||||
KEEP (*crtend.o(.dtors))
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||||
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||||
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||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
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||||
*(.gcc_except_table)
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||||
*(.gcc_except_table)
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||||
*(.eh_frame_hdr)
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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KEEP (*(SORT(.fini_array.*)))
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(0x10);
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} > ram
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/* short/global data section */
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.sdata : ALIGN(0x10)
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{
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__sdata_load = LOADADDR(.sdata);
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__sdata_start = .;
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__sdata_start = .;
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PROVIDE( __global_pointer$ = . + 0x800);
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*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
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*(.srodata*)
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@ -84,9 +84,9 @@ SECTIONS
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/* data section */
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.data : ALIGN(0x10)
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{
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{
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__data_load = LOADADDR(.data);
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__data_start = .;
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__data_start = .;
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*(.got.plt) *(.got)
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*(.shdata)
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*(.data .data.* .gnu.linkonce.d.*)
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. = ALIGN(0x10);
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__sbss_end = .;
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} > ram
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/* sbss section */
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.bss : ALIGN(0x10)
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{
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{
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__bss_start = .;
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*(.shbss)
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*(.bss .bss.* .gnu.linkonce.b.*)
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/* End of uninitialized data segment */
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_end = .;
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.heap : ALIGN(0x10)
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{
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__heap_start = .;
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. = ALIGN(0x10);
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_heap_end = __heap_end;
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} > ram
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.stack : ALIGN(0x10)
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{
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__stack_bottom = .;
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. += STACK_SIZE;
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__stack_top = .;
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_sp = .;
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__freertos_irq_stack_top = .;
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} > ram
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}
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@ -1,4 +1,3 @@
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#if 0
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/*******************************************************************************
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* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
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*
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@ -15,6 +14,8 @@
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#include "riscv_hal.h"
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#include "FreeRTOS.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -66,70 +67,6 @@ uint8_t External_31_IRQHandler(void);
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extern void Software_IRQHandler(void);
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extern void Timer_IRQHandle( void );
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/*------------------------------------------------------------------------------
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* Increment value for the mtimecmp register in order to achieve a system tick
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* interrupt as specified through the SysTick_Config() function.
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*/
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static uint64_t g_systick_increment = 0U;
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/*------------------------------------------------------------------------------
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* Disable all interrupts.
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*/
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void __disable_irq(void)
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{
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clear_csr(mstatus, MSTATUS_MPIE);
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clear_csr(mstatus, MSTATUS_MIE);
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}
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/*------------------------------------------------------------------------------
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* Enabler all interrupts.
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*/
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void __enable_irq(void)
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{
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set_csr(mstatus, MSTATUS_MIE);
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}
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/*------------------------------------------------------------------------------
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* Configure the machine timer to generate an interrupt.
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*/
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uint32_t SysTick_Config(uint32_t ticks)
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{
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uint32_t ret_val = ERROR;
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g_systick_increment = (uint64_t)(ticks) / RTC_PRESCALER;
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if (g_systick_increment > 0U)
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{
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uint32_t mhart_id = read_csr(mhartid);
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PRCI->MTIMECMP[mhart_id] = PRCI->MTIME + g_systick_increment;
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set_csr(mie, MIP_MTIP);
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__enable_irq();
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ret_val = SUCCESS;
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}
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return ret_val;
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}
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/*------------------------------------------------------------------------------
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* RISC-V interrupt handler for machine timer interrupts.
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*/
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volatile uint32_t ulTimerInterrupts = 0;
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extern void Timer_IRQHandler( void );
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static void handle_m_timer_interrupt(void)
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{
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// clear_csr(mie, MIP_MTIP);
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Timer_IRQHandler();
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// PRCI->MTIMECMP[read_csr(mhartid)] = PRCI->MTIME + g_systick_increment;
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// set_csr(mie, MIP_MTIP);
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}
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/*------------------------------------------------------------------------------
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* RISC-V interrupt handler for external interrupts.
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*/
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@ -172,7 +109,7 @@ uint8_t (*ext_irq_handler_table[32])(void) =
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/*------------------------------------------------------------------------------
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*
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*/
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static void handle_m_ext_interrupt(void)
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void handle_m_ext_interrupt(void)
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{
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uint32_t int_num = PLIC_ClaimIRQ();
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uint8_t disable = EXT_IRQ_KEEP_ENABLED;
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@ -187,82 +124,7 @@ static void handle_m_ext_interrupt(void)
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}
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}
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static void handle_m_soft_interrupt(void)
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{
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Software_IRQHandler();
|
||||
|
||||
/*Clear software interrupt*/
|
||||
PRCI->MSIP[0] = 0x00U;
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Trap/Interrupt handler
|
||||
*/
|
||||
#define ENV_CALL_FROM_M_MODE 11
|
||||
extern void vTaskSwitchContext( void );
|
||||
|
||||
uintptr_t handle_trap(uintptr_t mcause, uintptr_t mepc)
|
||||
{
|
||||
/*_RB_*/
|
||||
if( mcause == ENV_CALL_FROM_M_MODE )
|
||||
{
|
||||
vTaskSwitchContext();
|
||||
|
||||
/* Ensure not to return to the instruction that generated the exception. */
|
||||
mepc += 4;
|
||||
} else
|
||||
/*end _RB_*/
|
||||
if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
|
||||
{
|
||||
handle_m_ext_interrupt();
|
||||
}
|
||||
else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))
|
||||
{
|
||||
handle_m_timer_interrupt();
|
||||
}
|
||||
else if ( (mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT))
|
||||
{
|
||||
handle_m_soft_interrupt();
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifndef NDEBUG
|
||||
/*
|
||||
Arguments supplied to this function are mcause, mepc (exception PC) and stack pointer
|
||||
based onprivileged-isa specification
|
||||
mcause values and meanings are:
|
||||
0 Instruction address misaligned (mtval/mbadaddr is the address)
|
||||
1 Instruction access fault (mtval/mbadaddr is the address)
|
||||
2 Illegal instruction (mtval/mbadaddr contains the offending instruction opcode)
|
||||
3 Breakpoint
|
||||
4 Load address misaligned (mtval/mbadaddr is the address)
|
||||
5 Load address fault (mtval/mbadaddr is the address)
|
||||
6 Store/AMO address fault (mtval/mbadaddr is the address)
|
||||
7 Store/AMO access fault (mtval/mbadaddr is the address)
|
||||
8 Environment call from U-mode
|
||||
9 Environment call from S-mode
|
||||
A Environment call from M-mode
|
||||
B Instruction page fault
|
||||
C Load page fault (mtval/mbadaddr is the address)
|
||||
E Store page fault (mtval/mbadaddr is the address)
|
||||
*/
|
||||
|
||||
uintptr_t mip = read_csr(mip); /* interrupt pending */
|
||||
uintptr_t mbadaddr = read_csr(mbadaddr); /* additional info and meaning depends on mcause */
|
||||
uintptr_t mtvec = read_csr(mtvec); /* trap vector */
|
||||
uintptr_t mscratch = read_csr(mscratch); /* temporary, sometimes might hold temporary value of a0 */
|
||||
uintptr_t mstatus = read_csr(mstatus); /* status contains many smaller fields: */
|
||||
|
||||
/* breakpoint*/
|
||||
__asm("ebreak");
|
||||
#else
|
||||
_exit(1 + mcause);
|
||||
#endif
|
||||
}
|
||||
return mepc;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -143,7 +143,7 @@ static inline void PLIC_init(void)
|
|||
PLIC->TARGET[hart_id].PRIORITY_THRESHOLD = 0;
|
||||
|
||||
/* Enable machine external interrupts. */
|
||||
// set_csr(mie, MIP_MEIP);
|
||||
set_csr(mie, MIP_MEIP);
|
||||
}
|
||||
|
||||
/*==============================================================================
|
||||
|
|
|
|||
|
|
@ -70,6 +70,10 @@
|
|||
#include "timers.h"
|
||||
#include "semphr.h"
|
||||
|
||||
/* Microsemi incldues. */
|
||||
#include "core_timer.h"
|
||||
#include "riscv_hal.h"
|
||||
|
||||
/* Standard demo application includes. */
|
||||
#include "dynamic.h"
|
||||
#include "blocktim.h"
|
||||
|
|
@ -123,6 +127,12 @@ void main_full( void );
|
|||
*/
|
||||
static void prvCheckTask( void *pvParameters );
|
||||
|
||||
/*
|
||||
* Initialise and start the peripheral timers that are used to exercise external
|
||||
* interrupt processing.
|
||||
*/
|
||||
static void prvSetupPeripheralTimers( void );
|
||||
|
||||
/*
|
||||
* Register check tasks as described at the top of this file. The nature of
|
||||
* these files necessitates that they are written in an assembly file, but the
|
||||
|
|
@ -142,6 +152,13 @@ void vFullDemoTickHook( void );
|
|||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Timers used to exercise external interrupt processing. */
|
||||
static timer_instance_t g_timer0, g_timer1;
|
||||
|
||||
/* Variables incremented by the peripheral timers used to exercise external
|
||||
interrupts. */
|
||||
volatile uint32_t ulTimer0Interrupts = 0, ulTimer1Interrupts = 0;
|
||||
|
||||
/* The following two variables are used to communicate the status of the
|
||||
register check tasks to the check task. If the variables keep incrementing,
|
||||
then the register check tasks have not discovered any errors. If a variable
|
||||
|
|
@ -188,6 +205,9 @@ void main_full( void )
|
|||
running. */
|
||||
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
|
||||
|
||||
/* Start the timers that are used to exercise external interrupt handling. */
|
||||
prvSetupPeripheralTimers();
|
||||
|
||||
/* Start the scheduler. */
|
||||
vTaskStartScheduler();
|
||||
|
||||
|
|
@ -205,7 +225,8 @@ static void prvCheckTask( void *pvParameters )
|
|||
{
|
||||
TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD;
|
||||
TickType_t xLastExecutionTime;
|
||||
static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
|
||||
uint32_t ulLastRegTest1Value = 0, ulLastRegTest2Value = 0;
|
||||
uint32_t ulLastTimer0Interrupts = 0, ulLastTimer1Interrupts = 0;
|
||||
char * const pcPassMessage = "Pass.\r\n";
|
||||
char * pcStatusMessage = pcPassMessage;
|
||||
extern void vSendString( const char * const pcString );
|
||||
|
|
@ -310,9 +331,21 @@ extern void vToggleLED( void );
|
|||
}
|
||||
ulLastRegTest2Value = ulRegTest2LoopCounter;
|
||||
|
||||
/* Check interrupts from the peripheral timers are being handled. */
|
||||
if( ulLastTimer0Interrupts == ulTimer0Interrupts )
|
||||
{
|
||||
pcStatusMessage = "ERROR: Peripheral timer 0.\r\n";
|
||||
}
|
||||
ulLastTimer0Interrupts = ulTimer0Interrupts;
|
||||
|
||||
if( ulLastTimer1Interrupts == ulTimer1Interrupts )
|
||||
{
|
||||
pcStatusMessage = "ERROR: Peripheral timer 1.\r\n";
|
||||
}
|
||||
ulLastTimer1Interrupts = ulTimer1Interrupts;
|
||||
|
||||
/* Write the status message to the UART. */
|
||||
vSendString( pcStatusMessage );
|
||||
vToggleLED();
|
||||
|
||||
/* If an error has been found then increase the LED toggle rate by
|
||||
increasing the cycle frequency. */
|
||||
|
|
@ -383,3 +416,60 @@ void vFullDemoTickHook( void )
|
|||
/* Called from vApplicationTickHook() when the project is configured to
|
||||
build the full test/demo applications. */
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupPeripheralTimers( void )
|
||||
{
|
||||
TMR_init( &g_timer0,
|
||||
CORETIMER0_BASE_ADDR,
|
||||
TMR_CONTINUOUS_MODE,
|
||||
PRESCALER_DIV_1024,
|
||||
83000 );
|
||||
|
||||
TMR_init( &g_timer1,
|
||||
CORETIMER1_BASE_ADDR,
|
||||
TMR_CONTINUOUS_MODE,
|
||||
PRESCALER_DIV_512,
|
||||
42000 );
|
||||
|
||||
/* In this version of the PLIC, the priorities are fixed at 1.
|
||||
Lower numbered devices have higher priorities. But this code is given as
|
||||
an example.
|
||||
*/
|
||||
PLIC_SetPriority( External_30_IRQn, 1 );
|
||||
PLIC_SetPriority( External_31_IRQn, 1 );
|
||||
|
||||
/*Enable Timer 1 & 0 Interrupt*/
|
||||
PLIC_EnableIRQ( External_30_IRQn );
|
||||
PLIC_EnableIRQ( External_31_IRQn );
|
||||
|
||||
/* Enable the timers */
|
||||
TMR_enable_int( &g_timer0 );
|
||||
TMR_enable_int( &g_timer1 );
|
||||
|
||||
/* Make sure timers don't interrupt until the scheduler is running. */
|
||||
portDISABLE_INTERRUPTS();
|
||||
|
||||
/*Start the timer*/
|
||||
TMR_start( &g_timer0 );
|
||||
TMR_start( &g_timer1 );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*Core Timer 0 Interrupt Handler*/
|
||||
uint8_t External_30_IRQHandler( void )
|
||||
{
|
||||
ulTimer0Interrupts++;
|
||||
TMR_clear_int(&g_timer0);
|
||||
return( EXT_IRQ_KEEP_ENABLED );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*Core Timer 1 Interrupt Handler*/
|
||||
uint8_t External_31_IRQHandler( void )
|
||||
{
|
||||
ulTimer1Interrupts++;
|
||||
TMR_clear_int(&g_timer1);
|
||||
|
||||
return( EXT_IRQ_KEEP_ENABLED );
|
||||
}
|
||||
|
|
|
|||
|
|
@ -107,7 +107,6 @@ static void prvSetupHardware( void )
|
|||
{
|
||||
PLIC_init();
|
||||
UART_init( &g_uart, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, ( DATA_8_BITS | NO_PARITY ) );
|
||||
GPIO_init( &g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -182,3 +181,5 @@ void vApplicationTickHook( void )
|
|||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue