mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-07 14:47:42 -04:00
Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode.
This commit is contained in:
Richard Barry
parent
101806906d
commit
8285ca6b5f
9 changed files with 149 additions and 184 deletions
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@ -1,17 +1,17 @@
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/*******************************************************************************
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* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
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*
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*
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* file name : microsemi-riscv-igloo2.ld
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* Mi-V soft processor linker script for creating a SoftConsole downloadable
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* image executing in eNVM.
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*
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*
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* This linker script assumes that the eNVM is connected at on the Mi-V soft
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* processor memory space.
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* processor memory space.
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*
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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@ -24,19 +24,19 @@ MEMORY
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RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */
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RAM_SIZE = 64k; /* Must be the same value MEMORY region ram LENGTH above. */
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STACK_SIZE = 2k; /* needs to be calculated for your application */
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STACK_SIZE = 2k; /* needs to be calculated for your application */
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HEAP_SIZE = 2k; /* needs to be calculated for your application */
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SECTIONS
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{
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.text : ALIGN(0x10)
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{
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KEEP (*(SORT_NONE(.text.entry)))
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KEEP (*(SORT_NONE(.text.entry)))
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. = ALIGN(0x10);
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*(.text .text.* .gnu.linkonce.t.*)
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. = ALIGN(0x10);
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*crtend.o(.dtors))
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(0x10);
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} >envm
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/* short/global data section */
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.sdata : ALIGN(0x10)
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{
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__sdata_load = LOADADDR(.sdata);
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__sdata_start = .;
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__sdata_start = .;
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PROVIDE( __global_pointer$ = . + 0x800);
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*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
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*(.srodata*)
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@ -84,9 +84,9 @@ SECTIONS
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/* data section */
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.data : ALIGN(0x10)
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{
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{
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__data_load = LOADADDR(.data);
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__data_start = .;
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__data_start = .;
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@ -103,10 +103,10 @@ SECTIONS
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. = ALIGN(0x10);
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__sbss_end = .;
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} > ram
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/* sbss section */
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.bss : ALIGN(0x10)
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{
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{
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__bss_start = .;
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*(.shbss)
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*(.bss .bss.* .gnu.linkonce.b.*)
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@ -117,7 +117,7 @@ SECTIONS
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/* End of uninitialized data segment */
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_end = .;
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.heap : ALIGN(0x10)
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{
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__heap_start = .;
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@ -126,13 +126,14 @@ SECTIONS
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. = ALIGN(0x10);
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_heap_end = __heap_end;
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} > ram
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.stack : ALIGN(0x10)
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{
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__stack_bottom = .;
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. += STACK_SIZE;
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__stack_top = .;
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_sp = .;
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__freertos_irq_stack_top = .;
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} > ram
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}
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@ -1,10 +1,10 @@
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/*******************************************************************************
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* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
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*
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*
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* file name : microsemi-riscv-ram.ld
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* Mi-V soft processor linker script for creating a SoftConsole downloadable
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* debug image executing in SRAM.
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*
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*
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* This linker script assumes that the SRAM is connected at on the Mi-V soft
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* processor memory space. The start address and size of the memory space must
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* be correct as per the Libero design.
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@ -12,7 +12,7 @@
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* SVN $Revision: 9661 $
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* SVN $Date: 2018-01-15 16:13:33 +0530 (Mon, 15 Jan 2018) $
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*/
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OUTPUT_ARCH( "riscv" )
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ENTRY(_start)
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@ -24,19 +24,19 @@ MEMORY
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RAM_START_ADDRESS = 0x80000000; /* Must be the same value MEMORY region ram ORIGIN above. */
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RAM_SIZE = 512k; /* Must be the same value MEMORY region ram LENGTH above. */
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STACK_SIZE = 64k; /* needs to be calculated for your application */
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STACK_SIZE = 64k; /* needs to be calculated for your application */
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HEAP_SIZE = 64k; /* needs to be calculated for your application */
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SECTIONS
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{
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.text : ALIGN(0x10)
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{
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KEEP (*(SORT_NONE(.text.entry)))
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KEEP (*(SORT_NONE(.text.entry)))
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. = ALIGN(0x10);
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*(.text .text.* .gnu.linkonce.t.*)
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*(.plt)
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. = ALIGN(0x10);
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*crtend.o(.dtors))
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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*(.gcc_except_table)
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*(.eh_frame_hdr)
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KEEP (*(SORT(.fini_array.*)))
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(0x10);
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} > ram
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/* short/global data section */
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.sdata : ALIGN(0x10)
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{
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__sdata_load = LOADADDR(.sdata);
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__sdata_start = .;
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__sdata_start = .;
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PROVIDE( __global_pointer$ = . + 0x800);
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*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
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*(.srodata*)
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@ -84,9 +84,9 @@ SECTIONS
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/* data section */
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.data : ALIGN(0x10)
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{
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{
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__data_load = LOADADDR(.data);
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__data_start = .;
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__data_start = .;
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*(.got.plt) *(.got)
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*(.shdata)
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*(.data .data.* .gnu.linkonce.d.*)
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. = ALIGN(0x10);
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__sbss_end = .;
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} > ram
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/* sbss section */
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.bss : ALIGN(0x10)
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{
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{
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__bss_start = .;
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*(.shbss)
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*(.bss .bss.* .gnu.linkonce.b.*)
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/* End of uninitialized data segment */
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_end = .;
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.heap : ALIGN(0x10)
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{
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__heap_start = .;
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. = ALIGN(0x10);
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_heap_end = __heap_end;
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} > ram
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.stack : ALIGN(0x10)
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{
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__stack_bottom = .;
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. += STACK_SIZE;
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__stack_top = .;
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_sp = .;
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__freertos_irq_stack_top = .;
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} > ram
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}
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@ -1,4 +1,3 @@
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#if 0
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/*******************************************************************************
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* (c) Copyright 2016-2018 Microsemi SoC Products Group. All rights reserved.
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*
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@ -15,6 +14,8 @@
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#include "riscv_hal.h"
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#include "FreeRTOS.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern void Software_IRQHandler(void);
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extern void Timer_IRQHandle( void );
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/*------------------------------------------------------------------------------
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* Increment value for the mtimecmp register in order to achieve a system tick
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* interrupt as specified through the SysTick_Config() function.
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*/
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static uint64_t g_systick_increment = 0U;
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/*------------------------------------------------------------------------------
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* Disable all interrupts.
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*/
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void __disable_irq(void)
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{
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clear_csr(mstatus, MSTATUS_MPIE);
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clear_csr(mstatus, MSTATUS_MIE);
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}
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/*------------------------------------------------------------------------------
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* Enabler all interrupts.
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*/
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void __enable_irq(void)
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{
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set_csr(mstatus, MSTATUS_MIE);
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}
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/*------------------------------------------------------------------------------
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* Configure the machine timer to generate an interrupt.
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*/
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uint32_t SysTick_Config(uint32_t ticks)
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{
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uint32_t ret_val = ERROR;
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g_systick_increment = (uint64_t)(ticks) / RTC_PRESCALER;
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if (g_systick_increment > 0U)
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{
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uint32_t mhart_id = read_csr(mhartid);
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PRCI->MTIMECMP[mhart_id] = PRCI->MTIME + g_systick_increment;
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set_csr(mie, MIP_MTIP);
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__enable_irq();
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ret_val = SUCCESS;
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}
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return ret_val;
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}
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/*------------------------------------------------------------------------------
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* RISC-V interrupt handler for machine timer interrupts.
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*/
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volatile uint32_t ulTimerInterrupts = 0;
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extern void Timer_IRQHandler( void );
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static void handle_m_timer_interrupt(void)
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{
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// clear_csr(mie, MIP_MTIP);
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Timer_IRQHandler();
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// PRCI->MTIMECMP[read_csr(mhartid)] = PRCI->MTIME + g_systick_increment;
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// set_csr(mie, MIP_MTIP);
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}
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/*------------------------------------------------------------------------------
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* RISC-V interrupt handler for external interrupts.
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*/
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/*------------------------------------------------------------------------------
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*
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*/
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static void handle_m_ext_interrupt(void)
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void handle_m_ext_interrupt(void)
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{
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uint32_t int_num = PLIC_ClaimIRQ();
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uint8_t disable = EXT_IRQ_KEEP_ENABLED;
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}
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}
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static void handle_m_soft_interrupt(void)
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{
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Software_IRQHandler();
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/*Clear software interrupt*/
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PRCI->MSIP[0] = 0x00U;
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}
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/*------------------------------------------------------------------------------
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* Trap/Interrupt handler
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*/
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#define ENV_CALL_FROM_M_MODE 11
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extern void vTaskSwitchContext( void );
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uintptr_t handle_trap(uintptr_t mcause, uintptr_t mepc)
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{
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/*_RB_*/
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if( mcause == ENV_CALL_FROM_M_MODE )
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{
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vTaskSwitchContext();
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/* Ensure not to return to the instruction that generated the exception. */
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mepc += 4;
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} else
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/*end _RB_*/
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if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
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{
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handle_m_ext_interrupt();
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}
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else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))
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{
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handle_m_timer_interrupt();
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}
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else if ( (mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT))
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{
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handle_m_soft_interrupt();
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}
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else
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{
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#ifndef NDEBUG
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/*
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Arguments supplied to this function are mcause, mepc (exception PC) and stack pointer
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based onprivileged-isa specification
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mcause values and meanings are:
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0 Instruction address misaligned (mtval/mbadaddr is the address)
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1 Instruction access fault (mtval/mbadaddr is the address)
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2 Illegal instruction (mtval/mbadaddr contains the offending instruction opcode)
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3 Breakpoint
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4 Load address misaligned (mtval/mbadaddr is the address)
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5 Load address fault (mtval/mbadaddr is the address)
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6 Store/AMO address fault (mtval/mbadaddr is the address)
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7 Store/AMO access fault (mtval/mbadaddr is the address)
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8 Environment call from U-mode
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9 Environment call from S-mode
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A Environment call from M-mode
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B Instruction page fault
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C Load page fault (mtval/mbadaddr is the address)
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E Store page fault (mtval/mbadaddr is the address)
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*/
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uintptr_t mip = read_csr(mip); /* interrupt pending */
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uintptr_t mbadaddr = read_csr(mbadaddr); /* additional info and meaning depends on mcause */
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uintptr_t mtvec = read_csr(mtvec); /* trap vector */
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uintptr_t mscratch = read_csr(mscratch); /* temporary, sometimes might hold temporary value of a0 */
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uintptr_t mstatus = read_csr(mstatus); /* status contains many smaller fields: */
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/* breakpoint*/
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__asm("ebreak");
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#else
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_exit(1 + mcause);
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#endif
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}
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return mepc;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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PLIC->TARGET[hart_id].PRIORITY_THRESHOLD = 0;
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/* Enable machine external interrupts. */
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// set_csr(mie, MIP_MEIP);
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set_csr(mie, MIP_MEIP);
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}
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/*==============================================================================
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