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Add in an FM3/IAR

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Richard Barry 2011-05-04 19:05:31 +00:00
parent 4de76dbc82
commit 80db62e711
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/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.40
* @date 18. February 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ########################## Core Instruction Access ######################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
#if (__ARMCC_VERSION < 400677)
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
#if (__ARMCC_VERSION < 400677)
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __CLREX(void)
{
clrex
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
/* ########################### Core Function Access ########################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get IPSR Register value
*
* @return uint32_t IPSR value
*
* return the content of the IPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_IPSR(void)
{
mrs r0, ipsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get APSR Register value
*
* @return uint32_t APSR value
*
* return the content of the APSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_APSR(void)
{
mrs r0, apsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get xPSR Register value
*
* @return uint32_t xPSR value
*
* return the content of the xPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_xPSR(void)
{
mrs r0, xpsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the FPSCR value
*
* @return FloatingPointStatusControlRegister
*
* Return the content of the FPSCR register
*/
/**
* @brief Set the FPSCR value
*
* @param fpscr FloatingPointStatusControlRegister
*
* Set the FPSCR register
*/
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif

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;/************************************************************************/
;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
;/* */
;/* The following software deliverable is intended for and must only be */
;/* used for reference and in an evaluation laboratory environment. */
;/* It is provided on an as-is basis without charge and is subject to */
;/* alterations. */
;/* It is the user's obligation to fully test the software in its */
;/* environment and to ensure proper functionality, qualification and */
;/* compliance with component specifications. */
;/* */
;/* In the event the software deliverable includes the use of open */
;/* source components, the provisions of the governing open source */
;/* license agreement shall apply with respect to such software */
;/* deliverable. */
;/* FSEU does not warrant that the deliverables do not infringe any */
;/* third party intellectual property right (IPR). In the event that */
;/* the deliverables infringe a third party IPR it is the sole */
;/* responsibility of the customer to obtain necessary licenses to */
;/* continue the usage of the deliverable. */
;/* */
;/* To the maximum extent permitted by applicable law FSEU disclaims all */
;/* warranties, whether express or implied, in particular, but not */
;/* limited to, warranties of merchantability and fitness for a */
;/* particular purpose for which the deliverable is not designated. */
;/* */
;/* To the maximum extent permitted by applicable law, FSEU's liability */
;/* is restricted to intentional misconduct and gross negligence. */
;/* FSEU is not liable for consequential damages. */
;/* */
;/* (V1.5) */
;/************************************************************************/
;/* Startup for IAR */
;/* Version V1.02 */
;/* Date 2011-01-05 */
;/* Target-mcu MB9B5xx */
;/************************************************************************/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset
DCD NMI_Handler ; NMI
DCD HardFault_Handler ; Hard Fault
DCD MemManage_Handler ; MPU Fault
DCD BusFault_Handler ; Bus Fault
DCD UsageFault_Handler ; Usage Fault
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall
DCD DebugMon_Handler ; Debug Monitor
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV
DCD SysTick_Handler ; SysTick
DCD CSV_Handler ; 0: Clock Super Visor
DCD SWDT_Handler ; 1: Software Watchdog Timer
DCD LVD_Handler ; 2: Low Voltage Detector
DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
DCD DT_Handler ; 6: Dual Timer / Quad Decoder
DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
DCD PPG_Handler ; 23: PPG
DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
DCD ADC0_IRQHandler ; 25: ADC0
DCD ADC1_IRQHandler ; 26: ADC1
DCD ADC2_IRQHandler ; 27: ADC2
DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
DCD MFT_IPC_IRQHandler ; 29: Input Capture
DCD MFT_OPC_IRQHandler ; 30: Output Compare
DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
DCD CAN0_IRQHandler ; 32: CAN ch.0
DCD CAN1_IRQHandler ; 33: CAN ch.1
DCD USBF_Handler ; 34: USB Function
DCD USB_Handler ; 35: USB Function / USB HOST
DCD DummyHandler ; 36: Reserved
DCD DummyHandler ; 37: Reserved
DCD DMAC0_Handler ; 38: DMAC ch.0
DCD DMAC1_Handler ; 39: DMAC ch.1
DCD DMAC2_Handler ; 40: DMAC ch.2
DCD DMAC3_Handler ; 41: DMAC ch.3
DCD DMAC4_Handler ; 42: DMAC ch.4
DCD DMAC5_Handler ; 43: DMAC ch.5
DCD DMAC6_Handler ; 44: DMAC ch.6
DCD DMAC7_Handler ; 45: DMAC ch.7
DCD DummyHandler ; 46: Reserved
DCD DummyHandler ; 47: Reserved
THUMB
; Dummy Exception Handlers (infinite loops which can be modified)
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK CSV_Handler
SECTION .text:CODE:REORDER(1)
CSV_Handler
B CSV_Handler
PUBWEAK SWDT_Handler
SECTION .text:CODE:REORDER(1)
SWDT_Handler
B SWDT_Handler
PUBWEAK LVD_Handler
SECTION .text:CODE:REORDER(1)
LVD_Handler
B LVD_Handler
PUBWEAK MFT_WG_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_WG_IRQHandler
B MFT_WG_IRQHandler
PUBWEAK INT0_7_Handler
SECTION .text:CODE:REORDER(1)
INT0_7_Handler
B INT0_7_Handler
PUBWEAK INT8_15_Handler
SECTION .text:CODE:REORDER(1)
INT8_15_Handler
B INT8_15_Handler
PUBWEAK DT_Handler
SECTION .text:CODE:REORDER(1)
DT_Handler
B DT_Handler
PUBWEAK MFS0RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0RX_IRQHandler
B MFS0RX_IRQHandler
PUBWEAK MFS0TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0TX_IRQHandler
B MFS0TX_IRQHandler
PUBWEAK MFS1RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1RX_IRQHandler
B MFS1RX_IRQHandler
PUBWEAK MFS1TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1TX_IRQHandler
B MFS1TX_IRQHandler
PUBWEAK MFS2RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS2RX_IRQHandler
B MFS2RX_IRQHandler
PUBWEAK MFS2TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS2TX_IRQHandler
B MFS2TX_IRQHandler
PUBWEAK MFS3RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3RX_IRQHandler
B MFS3RX_IRQHandler
PUBWEAK MFS3TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3TX_IRQHandler
B MFS3TX_IRQHandler
PUBWEAK MFS4RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4RX_IRQHandler
B MFS4RX_IRQHandler
PUBWEAK MFS4TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4TX_IRQHandler
B MFS4TX_IRQHandler
PUBWEAK MFS5RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5RX_IRQHandler
B MFS5RX_IRQHandler
PUBWEAK MFS5TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5TX_IRQHandler
B MFS5TX_IRQHandler
PUBWEAK MFS6RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6RX_IRQHandler
B MFS6RX_IRQHandler
PUBWEAK MFS6TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6TX_IRQHandler
B MFS6TX_IRQHandler
PUBWEAK MFS7RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7RX_IRQHandler
B MFS7RX_IRQHandler
PUBWEAK MFS7TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7TX_IRQHandler
B MFS7TX_IRQHandler
PUBWEAK PPG_Handler
SECTION .text:CODE:REORDER(1)
PPG_Handler
B PPG_Handler
PUBWEAK TIM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM_IRQHandler
B TIM_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC0_IRQHandler
B ADC0_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK ADC2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC2_IRQHandler
B ADC2_IRQHandler
PUBWEAK MFT_FRT_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_FRT_IRQHandler
B MFT_FRT_IRQHandler
PUBWEAK MFT_IPC_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_IPC_IRQHandler
B MFT_IPC_IRQHandler
PUBWEAK MFT_OPC_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_OPC_IRQHandler
B MFT_OPC_IRQHandler
PUBWEAK BT_IRQHandler
SECTION .text:CODE:REORDER(1)
BT_IRQHandler
B BT_IRQHandler
PUBWEAK CAN0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN0_IRQHandler
B CAN0_IRQHandler
PUBWEAK CAN1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_IRQHandler
B CAN1_IRQHandler
PUBWEAK USBF_Handler
SECTION .text:CODE:REORDER(1)
USBF_Handler
B USBF_Handler
PUBWEAK USB_Handler
SECTION .text:CODE:REORDER(1)
USB_Handler
B USB_Handler
PUBWEAK DMAC0_Handler
SECTION .text:CODE:REORDER(1)
DMAC0_Handler
B DMAC0_Handler
PUBWEAK DMAC1_Handler
SECTION .text:CODE:REORDER(1)
DMAC1_Handler
B DMAC1_Handler
PUBWEAK DMAC2_Handler
SECTION .text:CODE:REORDER(1)
DMAC2_Handler
B DMAC2_Handler
PUBWEAK DMAC3_Handler
SECTION .text:CODE:REORDER(1)
DMAC3_Handler
B DMAC3_Handler
PUBWEAK DMAC4_Handler
SECTION .text:CODE:REORDER(1)
DMAC4_Handler
B DMAC4_Handler
PUBWEAK DMAC5_Handler
SECTION .text:CODE:REORDER(1)
DMAC5_Handler
B DMAC5_Handler
PUBWEAK DMAC6_Handler
SECTION .text:CODE:REORDER(1)
DMAC6_Handler
B DMAC6_Handler
PUBWEAK DMAC7_Handler
SECTION .text:CODE:REORDER(1)
DMAC7_Handler
B DMAC7_Handler
PUBWEAK DummyHandler
SECTION .text:CODE:REORDER(1)
DummyHandler
B DummyHandler
END

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/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user's obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intentional misconduct and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.5) */
/************************************************************************/
#include <stdint.h>
#include "mb9bf506n.h"
/*--------------------- Clock Configuration ----------------------------------*/
//
// <e0> Clock Configuration
// <h> System Clock Configuration
// <o1.1> SCM_CTL.MOSCE: Main clock oscillation enable
// <o2.0..3> CSW_TMR.MOWT: Main clock stabilization wait time
// <i> Default: ~ 500 ns
// < 0=> ~ 500 ns
// < 1=> ~ 8 us
// < 2=> ~ 16 us
// < 3=> ~ 32 us
// < 4=> ~ 64 us
// < 5=> ~ 128 us
// < 6=> ~ 256 us
// < 7=> ~ 512 us
// < 8=> ~ 1.0 ms
// < 9=> ~ 2.0 ms
// <10=> ~ 4.0 ms
// <11=> ~ 8.0 ms
// <12=> ~ 33.0 ms
// <13=> ~ 131 ms
// <14=> ~ 524 ms
// <15=> ~ 2.0 s
// <o1.3> SCM_CTL.SOSCE: Sub clock oscillation enable
// <o2.4..6> CSW_TMR.SOWT: SOWT: Sub clock stabilization wait time
// <i> Default: ~ 31.19 ms
// <0=> ~ 31.19 ms
// <1=> ~ 62.44 ms
// <2=> ~ 0.125 s
// <3=> ~ 0.25 s
// <4=> ~ 0.50 s
// <5=> ~ 1.00 s
// <6=> ~ 2.00 s
// <7=> ~ 4.00 s
// <e1.4> SCM_CTL.PLLE: PLL oscillation enable
// <i> fPLLO Max = 120MHz, CLKPLL Min = 60MHz
// <i> CLKPLL = (CLKMO / PLLK) * PLLN
// <o4.4..7> PLL_CTL1.PLLK: PLL input clock frequency division
// <1-16><#-1>
// <o5.0..4> PLL_CTL1.PLLN: PLL feedback frequency division
// <1-32><#-1>
// <o4.0..3> PLL_CTL1.PLLM: PLL VCO clock frequency division
// <1-16><#-1>
// <o3.0..2> PSW_TMR.POWT: PLL clock stabilization wait time
// <i> Default: ~ 128 us
// <0=> ~ 128 us
// <1=> ~ 256 us
// <2=> ~ 512 us
// <3=> ~ 1.02 ms
// <4=> ~ 2.05 ms
// <5=> ~ 4.10 ms
// <6=> ~ 8.20 ms
// <7=> ~ 16.40 ms
// </e>
// <o1.5..7> SCM_CTL.RCS: Master clock switch control
// <i> Default: Master Clock = CLKHC
// <0=> Master Clock = CLKHC
// <1=> Master Clock = CLKMO
// <2=> Master Clock = CLKPLL
// <4=> Master Clock = CLKLC
// <5=> Master Clock = CLKSO
// </h>
//
// <h> Base Clock Prescaler
// <o6.0..2> BSC_PSR.BSR: Base clock frequency division
// <i> Default: HCLK = Master Clock
// <i> HCLK Max = 80MHz
// <0=> HCLK = Master Clock
// <1=> HCLK = Master Clock / 2
// <2=> HCLK = Master Clock / 3
// <3=> HCLK = Master Clock / 4
// <4=> HCLK = Master Clock / 6
// <5=> HCLK = Master Clock / 8
// <6=> HCLK = Master Clock / 16
// </h>
//
// <h> APB0 Prescaler
// <o7.0..1> APBC0_PSR.APBC0: APB0 bus clock frequency division
// <i> PCLK0 Max = 40MHz
// <i> Default: PCLK0 = HCLK
// <0=> PCLK0 = HCLK
// <1=> PCLK0 = HCLK / 2
// <2=> PCLK0 = HCLK / 4
// <3=> PCLK0 = HCLK / 8
// </h>
//
// <h> APB1 Prescaler
// <o8.0..1> APBC1_PSR.APBC1: APB1 bus clock frequency
// <i> PCLK1 Max = 40MHz
// <i> Default: PCLK1 = HCLK
// <0=> PCLK1 = HCLK
// <1=> PCLK1 = HCLK / 2
// <2=> PCLK1 = HCLK / 4
// <3=> PCLK1 = HCLK / 8
// <o8.7> APBC1_PSR.APBC1EN: APB1 clock enable
// </h>
//
// <h> APB2 Prescaler
// <o9.0..1> APBC2_PSR.APBC2: APB2 bus clock frequency
// <i> PCLK2 Max = 40MHz
// <i> Default: PCLK2 = HCLK
// <0=> PCLK2 = HCLK
// <1=> PCLK2 = HCLK / 2
// <2=> PCLK2 = HCLK / 4
// <3=> PCLK2 = HCLK / 8
// <o9.7> APBC2_PSR.APBC2EN: APB2 clock enable
// </h>
//
// <h> SW Watchdog Clock Prescaler
// <o10.0..1>SWC_PSR.SWDS: Software watchdog clock frequency division
// <i> Default: SWDGOGCLK = PCLK0
// <0=> SWDGOGCLK = PCLK0
// <1=> SWDGOGCLK = PCLK0 / 2
// <2=> SWDGOGCLK = PCLK0 / 4
// <3=> SWDGOGCLK = PCLK0 / 8
// </h>
//
// <h> Trace Clock Prescaler
// <o11.0> TTC_PSR.TTC: Trace clock frequency division
// <i> Default: TPIUCLK = HCLK
// <0=> TPIUCLK = HCLK
// <1=> TPIUCLK = HCLK / 2
// </h>
//
// </e>
#define CLOCK_SETUP 1
#define SCM_CTL_Val 0x00000052
#define CSW_TMR_Val 0x0000005C
#define PSW_TMR_Val 0x00000000
#define PLL_CTL1_Val 0x00000000
#define PLL_CTL2_Val 0x00000013
#define BSC_PSR_Val 0x00000000
#define APBC0_PSR_Val 0x00000001
#define APBC1_PSR_Val 0x00000082
#define APBC2_PSR_Val 0x00000081
#define SWC_PSR_Val 0x00000003
#define TTC_PSR_Val 0x00000000
/*--------------------- WatchDog Configuration -------------------------------*/
//
// <o0.0> HW Watchdog disable
#define HWWD_DISABLE 0x00000001
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA))
#error "SCM_CTL: Invalid values of reserved bits!"
#endif
#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)
#error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
#endif
#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F))
#error "CSW_TMR: Invalid values of reserved bits!"
#endif
#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */
#if (CHECK_RSVD((PSW_TMR_val), ~0x00000007))
#error "PSW_TMR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))
#error "PLL_CTL1: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000001F))
#error "PLL_CTL2: Invalid values of reserved bits!"
#endif
#endif
#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007))
#error "BSC_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003))
#error "APBC0_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083))
#error "APBC1_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083))
#error "APBC2_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003))
#error "SWC_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001))
#error "TTC_PSR: Invalid values of reserved bits!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __CLKMO ( 4000000UL) /* External 4MHz Crystal */
#define __CLKSO ( 32768UL) /* External 32KHz Crystal */
#define __CLKHC ( 4000000UL) /* Internal 4MHz RC Oscillator */
#define __CLKLC ( 100000UL) /* Internal 100KHz RC Oscillator */
/* CLKPLL = (CLKMO / PLLK) * PLLN */
#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1)
#define __PLLN (((PLL_CTL2_Val ) & 0x1F) + 1)
#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK)
/* Determine core clock frequency according to settings */
#if (((SCM_CTL_Val >> 5) & 0x07) == 0)
#define __MASTERCLK (__CLKHC)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)
#define __MASTERCLK (__CLKMO)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)
#define __MASTERCLK (__PLLCLK)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)
#define __MASTERCLK (__CLKLC)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)
#define __MASTERCLK (__CLKSO)
#else
#define __MASTERCLK (0UL)
#endif
#if ((BSC_PSR_Val & 0x07) == 0)
#define __HCLK (__MASTERCLK / 1)
#elif ((BSC_PSR_Val & 0x07) == 1)
#define __HCLK (__MASTERCLK / 2)
#elif ((BSC_PSR_Val & 0x07) == 2)
#define __HCLK (__MASTERCLK / 3)
#elif ((BSC_PSR_Val & 0x07) == 3)
#define __HCLK (__MASTERCLK / 4)
#elif ((BSC_PSR_Val & 0x07) == 4)
#define __HCLK (__MASTERCLK / 6)
#elif ((BSC_PSR_Val & 0x07) == 5)
#define __HCLK (__MASTERCLK / 8)
#elif ((BSC_PSR_Val & 0x07) == 6)
#define __HCLK (__MASTERCLK /16)
#else
#define __HCLK (0UL)
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __HCLK; /*!< System Clock Frequency (Core Clock)*/
/**
* Retrieve the system core clock
*
* @param none
* @return none
*
* @brief retrieve system core clock from register settings.
*/
void SystemCoreClockUpdate (void) {
uint32_t masterClk;
uint32_t u32RegisterRead;
switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
case 0: /* internal High-speed Cr osc. */
masterClk = __CLKHC;
break;
case 1: /* external main osc. */
masterClk = __CLKMO;
break;
case 2: /* PLL clock */
u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
break;
case 4: /* internal Low-speed CR osc. */
masterClk = __CLKLC;
break;
case 5: /* external Sub osc. */
masterClk = __CLKSO;
break;
default:
masterClk = 0Ul;
break;
}
switch (FM3_CRG->BSC_PSR & 0x07) {
case 0:
SystemCoreClock = masterClk;
break;
case 1:
SystemCoreClock = masterClk / 2;
break;
case 2:
SystemCoreClock = masterClk / 3;
break;
case 3:
SystemCoreClock = masterClk / 4;
break;
case 4:
SystemCoreClock = masterClk / 6;
break;
case 5:
SystemCoreClock = masterClk /8;
break;
case 6:
SystemCoreClock = masterClk /16;
break;
default:
SystemCoreClock = 0Ul;
break;
}
}
/*
* Set CR Trimming Data
*
* @param none
* @return none
*
* @brief Update CR trimming with Flash
* trimming data.
*/
static void CrtrimSet(void)
{
/* CR Trimming Data */
if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
{
/* UnLock (MCR_FTRM) */
FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
/* Set MCR_FTRM */
FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
/* Lock (MCR_FTRM) */
FM3_CRTRIM->MCR_RLR = 0x00000000;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void) {
uint32_t u32RegisterRead;
#if (HWWD_DISABLE) /* HW Watchdog Disable */
FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */
FM3_HWWDT->WDG_LCK = 0xE5331AAE;
FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */
#endif
#if (CLOCK_SETUP) /* Clock Setup */
FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */
FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */
FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */
FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */
FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */
FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */
FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */
if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */
FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */
while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */
}
if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */
FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */
while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */
}
FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */
FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */
FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */
if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */
FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */
while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */
}
FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */
do
{
u32RegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
}while ((FM3_CRG->SCM_STR & 0xE0) != u32RegisterRead);
#endif
CrtrimSet();
}

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/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user's obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intentional misconduct and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.5) */
/************************************************************************/
#ifndef _SYSTEM_MB9B5XX_H_
#define _SYSTEM_MB9B5XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* Clock
*/
extern uint32_t SystemCoreClock; /* Core Clock CMSIS V 1.3 */
extern const uint32_t SystemFrequency; /* Master Clock */
extern uint32_t SysFreHCLK; /* HCLK */
extern uint32_t SysFrePCLK0; /* PCLK0 */
extern uint32_t SysFrePCLK1; /* PCLK1 */
extern uint32_t SysFrePCLK2; /* PCLK2 */
extern uint32_t SysFreTPIU; /* TPIU */
/*
* Setup the microcontroller system
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_MB9B5XX_H_ */