diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.ccsproject b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.ccsproject
new file mode 100644
index 000000000..893e3e02f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.ccsproject
@@ -0,0 +1,13 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.cproject b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.cproject
new file mode 100644
index 000000000..4e6af3968
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.cproject
@@ -0,0 +1,379 @@
+
+
+
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diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.project b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.project
new file mode 100644
index 000000000..4b13f734b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.project
@@ -0,0 +1,83 @@
+
+
+ CORTEX-R4_TI_CCS5
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+
+
+ ?name?
+
+
+
+ org.eclipse.cdt.make.core.append_environment
+ true
+
+
+ org.eclipse.cdt.make.core.autoBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.buildArguments
+ -k
+
+
+ org.eclipse.cdt.make.core.buildCommand
+ ${CCS_UTILS_DIR}/bin/gmake
+
+
+ org.eclipse.cdt.make.core.buildLocation
+ ${BuildDirectory}
+
+
+ org.eclipse.cdt.make.core.cleanBuildTarget
+ clean
+
+
+ org.eclipse.cdt.make.core.contents
+ org.eclipse.cdt.make.core.activeConfigSettings
+
+
+ org.eclipse.cdt.make.core.enableAutoBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableCleanBuild
+ true
+
+
+ org.eclipse.cdt.make.core.enableFullBuild
+ true
+
+
+ org.eclipse.cdt.make.core.fullBuildTarget
+ all
+
+
+ org.eclipse.cdt.make.core.stopOnError
+ false
+
+
+ org.eclipse.cdt.make.core.useDefaultBuildCmd
+ true
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ com.ti.ccstudio.core.ccsNature
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.core.ccnature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.settings/org.eclipse.cdt.codan.core.prefs b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.settings/org.eclipse.cdt.codan.core.prefs
new file mode 100644
index 000000000..98b635027
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.settings/org.eclipse.cdt.codan.core.prefs
@@ -0,0 +1,3 @@
+eclipse.preferences.version=1
+inEditor=false
+onBuild=false
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.settings/org.eclipse.cdt.debug.core.prefs b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.settings/org.eclipse.cdt.debug.core.prefs
new file mode 100644
index 000000000..58d4fb29d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.settings/org.eclipse.cdt.debug.core.prefs
@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.settings/org.eclipse.core.resources.prefs b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.settings/org.eclipse.core.resources.prefs
new file mode 100644
index 000000000..3cd646a2d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/.settings/org.eclipse.core.resources.prefs
@@ -0,0 +1,107 @@
+eclipse.preferences.version=1
+encoding//RM48\ with\ FPU/Common-Demo-Source/subdir_rules.mk=UTF-8
+encoding//RM48\ with\ FPU/Common-Demo-Source/subdir_vars.mk=UTF-8
+encoding//RM48\ with\ FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_rules.mk=UTF-8
+encoding//RM48\ with\ FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_vars.mk=UTF-8
+encoding//RM48\ with\ FPU/FreeRTOS/portable/MemMang/subdir_rules.mk=UTF-8
+encoding//RM48\ with\ FPU/FreeRTOS/portable/MemMang/subdir_vars.mk=UTF-8
+encoding//RM48\ with\ FPU/FreeRTOS/subdir_rules.mk=UTF-8
+encoding//RM48\ with\ FPU/FreeRTOS/subdir_vars.mk=UTF-8
+encoding//RM48\ with\ FPU/Library/subdir_rules.mk=UTF-8
+encoding//RM48\ with\ FPU/Library/subdir_vars.mk=UTF-8
+encoding//RM48\ with\ FPU/makefile=UTF-8
+encoding//RM48\ with\ FPU/objects.mk=UTF-8
+encoding//RM48\ with\ FPU/sources.mk=UTF-8
+encoding//RM48\ with\ FPU/startup/subdir_rules.mk=UTF-8
+encoding//RM48\ with\ FPU/startup/subdir_vars.mk=UTF-8
+encoding//RM48\ with\ FPU/subdir_rules.mk=UTF-8
+encoding//RM48\ with\ FPU/subdir_vars.mk=UTF-8
+encoding//RM48\ without\ FPU/Common-Demo-Source/subdir_rules.mk=UTF-8
+encoding//RM48\ without\ FPU/Common-Demo-Source/subdir_vars.mk=UTF-8
+encoding//RM48\ without\ FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_rules.mk=UTF-8
+encoding//RM48\ without\ FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_vars.mk=UTF-8
+encoding//RM48\ without\ FPU/FreeRTOS/portable/MemMang/subdir_rules.mk=UTF-8
+encoding//RM48\ without\ FPU/FreeRTOS/portable/MemMang/subdir_vars.mk=UTF-8
+encoding//RM48\ without\ FPU/FreeRTOS/subdir_rules.mk=UTF-8
+encoding//RM48\ without\ FPU/FreeRTOS/subdir_vars.mk=UTF-8
+encoding//RM48\ without\ FPU/Library/subdir_rules.mk=UTF-8
+encoding//RM48\ without\ FPU/Library/subdir_vars.mk=UTF-8
+encoding//RM48\ without\ FPU/makefile=UTF-8
+encoding//RM48\ without\ FPU/objects.mk=UTF-8
+encoding//RM48\ without\ FPU/sources.mk=UTF-8
+encoding//RM48\ without\ FPU/startup/subdir_rules.mk=UTF-8
+encoding//RM48\ without\ FPU/startup/subdir_vars.mk=UTF-8
+encoding//RM48\ without\ FPU/subdir_rules.mk=UTF-8
+encoding//RM48\ without\ FPU/subdir_vars.mk=UTF-8
+encoding//TMS570\ with\ FPU/Common-Demo-Source/subdir_rules.mk=UTF-8
+encoding//TMS570\ with\ FPU/Common-Demo-Source/subdir_vars.mk=UTF-8
+encoding//TMS570\ with\ FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_rules.mk=UTF-8
+encoding//TMS570\ with\ FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_vars.mk=UTF-8
+encoding//TMS570\ with\ FPU/FreeRTOS/portable/MemMang/subdir_rules.mk=UTF-8
+encoding//TMS570\ with\ FPU/FreeRTOS/portable/MemMang/subdir_vars.mk=UTF-8
+encoding//TMS570\ with\ FPU/FreeRTOS/subdir_rules.mk=UTF-8
+encoding//TMS570\ with\ FPU/FreeRTOS/subdir_vars.mk=UTF-8
+encoding//TMS570\ with\ FPU/Library/subdir_rules.mk=UTF-8
+encoding//TMS570\ with\ FPU/Library/subdir_vars.mk=UTF-8
+encoding//TMS570\ with\ FPU/makefile=UTF-8
+encoding//TMS570\ with\ FPU/objects.mk=UTF-8
+encoding//TMS570\ with\ FPU/sources.mk=UTF-8
+encoding//TMS570\ with\ FPU/startup/subdir_rules.mk=UTF-8
+encoding//TMS570\ with\ FPU/startup/subdir_vars.mk=UTF-8
+encoding//TMS570\ with\ FPU/subdir_rules.mk=UTF-8
+encoding//TMS570\ with\ FPU/subdir_vars.mk=UTF-8
+encoding//TMS570\ without\ FPU/Common-Demo-Source/subdir_rules.mk=UTF-8
+encoding//TMS570\ without\ FPU/Common-Demo-Source/subdir_vars.mk=UTF-8
+encoding//TMS570\ without\ FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_rules.mk=UTF-8
+encoding//TMS570\ without\ FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_vars.mk=UTF-8
+encoding//TMS570\ without\ FPU/FreeRTOS/portable/MemMang/subdir_rules.mk=UTF-8
+encoding//TMS570\ without\ FPU/FreeRTOS/portable/MemMang/subdir_vars.mk=UTF-8
+encoding//TMS570\ without\ FPU/FreeRTOS/subdir_rules.mk=UTF-8
+encoding//TMS570\ without\ FPU/FreeRTOS/subdir_vars.mk=UTF-8
+encoding//TMS570\ without\ FPU/Library/subdir_rules.mk=UTF-8
+encoding//TMS570\ without\ FPU/Library/subdir_vars.mk=UTF-8
+encoding//TMS570\ without\ FPU/makefile=UTF-8
+encoding//TMS570\ without\ FPU/objects.mk=UTF-8
+encoding//TMS570\ without\ FPU/sources.mk=UTF-8
+encoding//TMS570\ without\ FPU/startup/subdir_rules.mk=UTF-8
+encoding//TMS570\ without\ FPU/startup/subdir_vars.mk=UTF-8
+encoding//TMS570\ without\ FPU/subdir_rules.mk=UTF-8
+encoding//TMS570\ without\ FPU/subdir_vars.mk=UTF-8
+encoding//With_FPU/Common-Demo-Source/subdir_rules.mk=UTF-8
+encoding//With_FPU/Common-Demo-Source/subdir_vars.mk=UTF-8
+encoding//With_FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_rules.mk=UTF-8
+encoding//With_FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_vars.mk=UTF-8
+encoding//With_FPU/FreeRTOS/portable/MemMang/subdir_rules.mk=UTF-8
+encoding//With_FPU/FreeRTOS/portable/MemMang/subdir_vars.mk=UTF-8
+encoding//With_FPU/FreeRTOS/subdir_rules.mk=UTF-8
+encoding//With_FPU/FreeRTOS/subdir_vars.mk=UTF-8
+encoding//With_FPU/Library/subdir_rules.mk=UTF-8
+encoding//With_FPU/Library/subdir_vars.mk=UTF-8
+encoding//With_FPU/RM48_FreeRTOS_Demo/source/subdir_rules.mk=UTF-8
+encoding//With_FPU/RM48_FreeRTOS_Demo/source/subdir_vars.mk=UTF-8
+encoding//With_FPU/makefile=UTF-8
+encoding//With_FPU/objects.mk=UTF-8
+encoding//With_FPU/sources.mk=UTF-8
+encoding//With_FPU/startup/subdir_rules.mk=UTF-8
+encoding//With_FPU/startup/subdir_vars.mk=UTF-8
+encoding//With_FPU/subdir_rules.mk=UTF-8
+encoding//With_FPU/subdir_vars.mk=UTF-8
+encoding//Without_FPU/Common-Demo-Source/subdir_rules.mk=UTF-8
+encoding//Without_FPU/Common-Demo-Source/subdir_vars.mk=UTF-8
+encoding//Without_FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_rules.mk=UTF-8
+encoding//Without_FPU/FreeRTOS/portable/CCS/ARM_Cortex-R4/subdir_vars.mk=UTF-8
+encoding//Without_FPU/FreeRTOS/portable/MemMang/subdir_rules.mk=UTF-8
+encoding//Without_FPU/FreeRTOS/portable/MemMang/subdir_vars.mk=UTF-8
+encoding//Without_FPU/FreeRTOS/subdir_rules.mk=UTF-8
+encoding//Without_FPU/FreeRTOS/subdir_vars.mk=UTF-8
+encoding//Without_FPU/Library/subdir_rules.mk=UTF-8
+encoding//Without_FPU/Library/subdir_vars.mk=UTF-8
+encoding//Without_FPU/RM48_FreeRTOS_Demo/source/subdir_rules.mk=UTF-8
+encoding//Without_FPU/RM48_FreeRTOS_Demo/source/subdir_vars.mk=UTF-8
+encoding//Without_FPU/makefile=UTF-8
+encoding//Without_FPU/objects.mk=UTF-8
+encoding//Without_FPU/sources.mk=UTF-8
+encoding//Without_FPU/startup/subdir_rules.mk=UTF-8
+encoding//Without_FPU/startup/subdir_vars.mk=UTF-8
+encoding//Without_FPU/subdir_rules.mk=UTF-8
+encoding//Without_FPU/subdir_vars.mk=UTF-8
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/CreateProjectDirectoryStructure.bat b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/CreateProjectDirectoryStructure.bat
new file mode 100644
index 000000000..e3af12c9f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/CreateProjectDirectoryStructure.bat
@@ -0,0 +1,59 @@
+REM This file should be executed from the command line prior to the first
+REM build. It will be necessary to refresh the Eclipse project once the
+REM .bat file has been executed (normally just press F5 to refresh).
+
+REM Copies all the required files from their location within the standard
+REM FreeRTOS directory structure to under the Eclipse project directory.
+REM This permits the Eclipse project to be used in 'managed' mode and without
+REM having to setup any linked resources.
+
+REM Standard paths
+SET FREERTOS_SOURCE=..\..\Source
+SET COMMON_SOURCE=..\Common\minimal
+SET COMMON_INCLUDE=..\Common\include
+
+REM Have the files already been copied?
+IF EXIST .\FreeRTOS_Source Goto END
+
+ REM Create the required directory structure.
+ MD FreeRTOS
+ MD FreeRTOS\include
+ MD FreeRTOS\portable
+ MD FreeRTOS\portable\CCS
+ MD FreeRTOS\portable\CCS\ARM_Cortex-R4
+ MD FreeRTOS\portable\MemMang
+ MD Common-Demo-Source
+ MD Common-Demo-Source\include
+
+ REM Copy the core kernel files into the project directory
+ copy %FREERTOS_SOURCE%\tasks.c FreeRTOS
+ copy %FREERTOS_SOURCE%\queue.c FreeRTOS
+ copy %FREERTOS_SOURCE%\list.c FreeRTOS
+ copy %FREERTOS_SOURCE%\timers.c FreeRTOS
+
+ REM Copy the common header files into the project directory
+ copy %FREERTOS_SOURCE%\include\*.* FreeRTOS\include
+
+ REM Copy the portable layer files into the project directory
+ copy %FREERTOS_SOURCE%\portable\CCS\ARM_Cortex-R4\*.* FreeRTOS\portable\CCS\ARM_Cortex-R4
+
+ REM Copy the memory allocation files into the project directory
+ copy %FREERTOS_SOURCE%\portable\MemMang\heap_4.c FreeRTOS\portable\MemMang
+
+ REM Copy the files that define the common demo tasks.
+ copy %COMMON_SOURCE%\dynamic.c Common-Demo-Source
+ copy %COMMON_SOURCE%\BlockQ.c Common-Demo-Source
+ copy %COMMON_SOURCE%\death.c Common-Demo-Source
+ copy %COMMON_SOURCE%\blocktim.c Common-Demo-Source
+ copy %COMMON_SOURCE%\semtest.c Common-Demo-Source
+ copy %COMMON_SOURCE%\PollQ.c Common-Demo-Source
+ copy %COMMON_SOURCE%\GenQTest.c Common-Demo-Source
+ copy %COMMON_SOURCE%\recmutex.c Common-Demo-Source
+ copy %COMMON_SOURCE%\countsem.c Common-Demo-Source
+ copy %COMMON_SOURCE%\integer.c Common-Demo-Source
+ copy %COMMON_SOURCE%\comtest.c Common-Demo-Source
+
+ REM Copy the common demo file headers.
+ copy %COMMON_INCLUDE%\*.h Common-Demo-Source\include
+
+: END
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/FreeRTOSConfig.h
new file mode 100644
index 000000000..808b6da34
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/FreeRTOSConfig.h
@@ -0,0 +1,141 @@
+/*
+ FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license
+ and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/*
+ * The following #error directive is to remind users that a batch file must be
+ * executed prior to this project being built. Once it has been executed
+ * remove the #error line below.
+ */
+//#error Ensure CreateProjectDirectoryStructure.bat has been executed before building. See comment immediately above.
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION 1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#define configUSE_IDLE_HOOK 1
+#define configUSE_TICK_HOOK 1
+#define configUSE_TRACE_FACILITY 0
+#define configUSE_16_BIT_TICKS 0
+#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 90000000 ) /* Timer clock. */
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
+#define configMAX_PRIORITIES ( 8 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) 32768 )
+#define configMAX_TASK_NAME_LEN ( 16 )
+#define configIDLE_SHOULD_YIELD 1
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_MALLOC_FAILED_HOOK 1
+
+#define configCHECK_FOR_STACK_OVERFLOW 2
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Mutexes */
+#define configUSE_MUTEXES 1
+#define configUSE_RECURSIVE_MUTEXES 1
+
+/* Semaphores */
+#define configUSE_COUNTING_SEMAPHORES 1
+
+/* Timers */
+#define configUSE_TIMERS 1
+#define configTIMER_TASK_PRIORITY ( 2 )
+#define configTIMER_QUEUE_LENGTH 10
+#define configTIMER_TASK_STACK_DEPTH ( 128 )
+
+/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_xTaskResumeFromISR 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_xTaskGetSchedulerState 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 1
+
+#define configASSERT( x ) if( ( x ) == pdFALSE ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/gio.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/gio.c
new file mode 100644
index 000000000..d38105abf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/gio.c
@@ -0,0 +1,281 @@
+/** @file gio.c
+* @brief GIO Driver Inmplmentation File
+* @date 10.June.2010
+* @version 1.01.000
+*
+*/
+
+/* (c) Texas Instruments 2009-2010, All rights reserved. */
+
+
+#include "gio.h"
+
+
+/** @fn void gioInit(void)
+* @brief Initializes the GIO Driver
+*
+* This function initializes the GIO module and set the GIO ports
+* to the inital values.
+*/
+void gioInit(void)
+{
+ /** bring GIO module out of reset */
+ gioREG->GCR0 = 1;
+ gioREG->INTENACLR = 0xFF;
+ gioREG->LVLCLR = 0xFF;
+
+ /** @b initalise @b Port @b A */
+
+ /** - Port A output values */
+ gioPORTA->DOUT = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port A direction */
+ gioPORTA->DIR = 1 /* Bit 0 */
+ | (1 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port A open drain enable */
+ gioPORTA->PDR = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port A pullup / pulldown selection */
+ gioPORTA->PSL = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port A pullup / pulldown enable*/
+ gioPORTA->PULDIS = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** @b initalise @b Port @b B */
+
+ /** - Port B output values */
+ gioPORTB->DOUT = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port B direction */
+ gioPORTB->DIR = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port B open drain enable */
+ gioPORTB->PDR = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port B pullup / pulldown selection */
+ gioPORTB->PSL = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - Port B pullup / pulldown enable*/
+ gioPORTB->PULDIS = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+
+ /** @b initalise @b interrupts */
+
+ /** - interrupt polarity */
+ gioREG->POL = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+ /** - interrupt level */
+ gioREG->LVLSET = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+
+
+ /** - clear all pending interrupts */
+ gioREG->FLG = 0xFF;
+
+ /** - enable interrupts */
+ gioREG->INTENASET = 0 /* Bit 0 */
+ | (0 << 1) /* Bit 1 */
+ | (0 << 2) /* Bit 2 */
+ | (0 << 3) /* Bit 3 */
+ | (0 << 4) /* Bit 4 */
+ | (0 << 5) /* Bit 5 */
+ | (0 << 6) /* Bit 6 */
+ | (0 << 7); /* Bit 7 */
+}
+
+
+/** @fn void gioSetDirection(gioPORT_t *port, unsigned dir)
+* @brief Set Port Direction
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] dir value to write to DIR register
+*
+* Set the direction of GIO pins at runtime.
+*/
+void gioSetDirection(gioPORT_t *port, unsigned dir)
+{
+ port->DIR = dir;
+}
+
+
+/** @fn void gioSetBit(gioPORT_t *port, unsigned bit, unsigned value)
+* @brief Write Bit
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit number 0-7 that specifies the bit to be written to.
+* - 0: LSB
+* - 7: MSB
+* @param[in] value binrary value to write to bit
+*
+* Writes a value to the specified pin of the given GIO port
+*/
+void gioSetBit(gioPORT_t *port, unsigned bit, unsigned value)
+{
+ if (value)
+ {
+ port->DSET = 1 << bit;
+ }
+ else
+ {
+ port->DCLR = 1 << bit;
+ }
+}
+
+
+/** @fn void gioSetPort(gioPORT_t *port, unsigned value)
+* @brief Write Port Value
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] value value to write to port
+*
+* Writes a value to all pin of a given GIO port
+*/
+void gioSetPort(gioPORT_t *port, unsigned value)
+{
+ port->DOUT = value;
+}
+
+
+/** @fn unsigned gioGetBit(gioPORT_t *port, unsigned bit)
+* @brief Read Bit
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+* @param[in] bit number 0-7 that specifies the bit to be written to.
+* - 0: LSB
+* - 7: MSB
+*
+* Reads a the current value from the specified pin of the given GIO port
+*/
+unsigned gioGetBit(gioPORT_t *port, unsigned bit)
+{
+ return (port->DIN >> bit) & 1U;
+}
+
+
+/** @fn unsigned gioGetPort(gioPORT_t *port)
+* @brief Read Port Value
+* @param[in] port pointer to GIO port:
+* - gioPORTA: PortA pointer
+* - gioPORTB: PortB pointer
+*
+* Reads a the current value of a given GIO port
+*/
+unsigned gioGetPort(gioPORT_t *port)
+{
+ return port->DIN;
+}
+
+
+/** @fn void gioEnableNotification(unsigned bit)
+* @brief Enable Interrupt
+* @param[in] bit interrupt pin to enable
+* - 0: LSB
+* - 7: MSB
+*
+* Enables an innterrupt pin of PortA
+*/
+void gioEnableNotification(unsigned bit)
+{
+ gioREG->INTENASET = 1 << bit;
+}
+
+
+/** @fn void gioDisableNotification(unsigned bit)
+* @brief Disable Interrupt
+* @param[in] bit interrupt pin to enable
+* - 0: LSB
+* - 7: MSB
+*
+* Disables an innterrupt pin of PortA
+*/
+void gioDisableNotification(unsigned bit)
+{
+ gioREG->INTENACLR = 1 << bit;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/gio.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/gio.h
new file mode 100644
index 000000000..7947b4e2e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/gio.h
@@ -0,0 +1,94 @@
+/** @file gio.h
+* @brief GIO Driver Definition File
+* @date 11.August.2009
+* @version 1.01.000
+*
+*/
+
+/* (c) Texas Instruments 2009-2010, All rights reserved. */
+
+
+#ifndef __GIO_H__
+#define __GIO_H__
+
+/** @struct gioBase
+* @brief GIO Base Register Definition
+*
+* This structure is used to access the GIO module egisters.
+*/
+/** @typedef gioBASE_t
+* @brief GIO Register Frame Type Definition
+*
+* This type is used to access the GIO Registers.
+*/
+typedef volatile struct gioBase
+{
+ unsigned GCR0; /**< 0x0000: Global Control Register */
+ unsigned PWDN; /**< 0x0004: Power Down Register */
+ unsigned INTDET; /**< 0x0008: Interrupt Detect Regsiter*/
+ unsigned POL; /**< 0x000C: Interrupt Polarity Register */
+ unsigned INTENASET; /**< 0x0010: Interrupt Enable Set Register */
+ unsigned INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */
+ unsigned LVLSET; /**< 0x0018: Interrupt Priority Set Register */
+ unsigned LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */
+ unsigned FLG; /**< 0x0020: Interrupt Flag Register */
+ unsigned OFFSET0; /**< 0x0024: Interrupt Offset A Register */
+ unsigned OFFSET1; /**< 0x0028: Interrupt Offset B Register */
+} gioBASE_t;
+
+
+/** @struct gioPort
+* @brief GIO Port Register Definition
+*/
+/** @typedef gioPORT_t
+* @brief GIO Port Register Type Definition
+*
+* This type is used to access the GIO Port Registers.
+*/
+typedef volatile struct gioPort
+{
+ unsigned DIR; /**< 0x0000: Data Direction Register */
+ unsigned DIN; /**< 0x0004: Data Input Register */
+ unsigned DOUT; /**< 0x0008: Data Output Register */
+ unsigned DSET; /**< 0x000C: Data Output Set Register */
+ unsigned DCLR; /**< 0x0010: Data Output Clear Register */
+ unsigned PDR; /**< 0x0014: Open Drain Regsiter */
+ unsigned PULDIS; /**< 0x0018: Pullup Disable Register */
+ unsigned PSL; /**< 0x001C: Pull Up/Down Selection Register */
+} gioPORT_t;
+
+
+/** @def gioREG
+* @brief GIO Register Frame Pointer
+*
+* This pointer is used by the GIO driver to access the gio module registers.
+*/
+#define gioREG ((gioBASE_t *)0xFFF7BC00U)
+
+/** @def gioPORTA
+* @brief GIO Port (A) Register Pointer
+*
+* Pointer used by the GIO driver to access PORTA
+*/
+#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)
+
+/** @def gioPORTB
+* @brief GIO Port (B) Register Pointer
+*
+* Pointer used by the GIO driver to access PORTB
+*/
+#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)
+
+
+/* GIO Interface Functions */
+void gioInit(void);
+void gioSetDirection(gioPORT_t *port, unsigned dir);
+void gioSetBit(gioPORT_t *port, unsigned bit, unsigned value);
+void gioSetPort(gioPORT_t *port, unsigned value);
+unsigned gioGetBit(gioPORT_t *port, unsigned bit);
+unsigned gioGetPort(gioPORT_t *port);
+void gioEnableNotification(unsigned bit);
+void gioDisableNotification(unsigned bit);
+void gioNotification(int bit);
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/het.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/het.c
new file mode 100644
index 000000000..78def3344
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/het.c
@@ -0,0 +1,121 @@
+/*
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+#include "FreeRTOS.h"
+#include "Task.h"
+#include "gio.h"
+#include "het.h"
+
+/*
+ * Task that flashes the LEDS on the USB stick.
+ *
+ * This task is also run in Thumb mode to test the ARM/THUMB context switch
+ */
+
+#pragma TASK(vLedTask)
+#pragma CODE_STATE(vLedTask, 16)
+
+void vLedTask(void *pvParameters)
+{
+ unsigned led = 0;
+ unsigned count = 0;
+ unsigned colour = 0;
+
+ /* Initalise the IO ports that drive the LEDs */
+ gioSetDirection(hetPORT, 0xFFFFFFFF);
+ /* switch all leds off */
+ gioSetPort(hetPORT, 0x08110034);
+
+ for(;;)
+ {
+ /* toggle on/off */
+ led ^= 1;
+ /* switch TOP row */
+ gioSetBit(hetPORT, 25, led);
+ gioSetBit(hetPORT, 18, led);
+ gioSetBit(hetPORT, 29, led);
+ /* switch BOTTOM row */
+ gioSetBit(hetPORT, 17, led ^ 1);
+ gioSetBit(hetPORT, 31, led ^ 1);
+ gioSetBit(hetPORT, 0, led ^ 1);
+ vTaskDelay(500);
+
+ if (++count > 5)
+ {
+ count = 0;
+ /* both leds to off */
+ gioSetBit(hetPORT, 2, 1); gioSetBit(hetPORT, 5, 1); gioSetBit(hetPORT, 20, 1);
+ gioSetBit(hetPORT, 4, 1); gioSetBit(hetPORT, 27, 1); gioSetBit(hetPORT, 16, 1);
+ switch(colour)
+ {
+ case 0:
+ gioSetBit(hetPORT, 2, 0); /* red */
+ gioSetBit(hetPORT, 4, 0);
+ colour++;
+ continue;
+ case 1:
+ gioSetBit(hetPORT, 5, 0); /* blue */
+ gioSetBit(hetPORT, 27, 0);
+ colour++;
+ continue;
+ case 2:
+ gioSetBit(hetPORT, 20, 0); /* green */
+ gioSetBit(hetPORT, 16, 0);
+ colour++;
+ continue;
+ }
+ colour = 0;
+ }
+ }
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/het.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/het.h
new file mode 100644
index 000000000..5f0c47cdd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/Library/het.h
@@ -0,0 +1,128 @@
+/*
+ FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.
+
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+
+#ifndef __HET_H__
+#define __HET_H__
+
+#include "gio.h"
+
+/** @struct hetBase
+* @brief HET Register Definition
+*
+* This structure is used to access the HET module egisters.
+*/
+/** @typedef hetBASE_t
+* @brief HET Register Frame Type Definition
+*
+* This type is used to access the HET Registers.
+*/
+typedef volatile struct hetBase
+{
+ unsigned GCR; /**< 0x0000: Global control register */
+ unsigned PFR; /**< 0x0004: Prescale factor register */
+ unsigned ADDR; /**< 0x0008: Current address register */
+ unsigned OFF1; /**< 0x000C: Interrupt offset register 1 */
+ unsigned OFF2; /**< 0x0010: Interrupt offset register 2 */
+ unsigned INTENAS; /**< 0x0014: Interrupt enable set register */
+ unsigned INTENAC; /**< 0x0018: Interrupt enable clear register */
+ unsigned EXC1; /**< 0x001C: Exeption control register 1 */
+ unsigned EXC2; /**< 0x0020: Exeption control register 2 */
+ unsigned PRY; /**< 0x0024: Interrupt priority register */
+ unsigned FLG; /**< 0x0028: Interrupt flag register */
+ unsigned : 32U; /**< 0x002C: Reserved */
+ unsigned : 32U; /**< 0x0030: Reserved */
+ unsigned HRSH; /**< 0x0034: High resoltion share register */
+ unsigned XOR; /**< 0x0038: XOR share register */
+ unsigned REQENS; /**< 0x003C: Request enable set register */
+ unsigned REQENC; /**< 0x0040: Request enable clear register */
+ unsigned REQDS; /**< 0x0044: Request destination select register */
+ unsigned : 32U; /**< 0x0048: Reserved */
+ unsigned DIR; /**< 0x004C: Direction register */
+ unsigned DIN; /**< 0x0050: Data input register */
+ unsigned DOUT; /**< 0x0054: Data output register */
+ unsigned DSET; /**< 0x0058: Data output set register */
+ unsigned DCLR; /**< 0x005C: Data output clear register */
+ unsigned PDR; /**< 0x0060: Open drain register */
+ unsigned PULDIS; /**< 0x0064: Pull disable register */
+ unsigned PSL; /**< 0x0068: Pull select register */
+ unsigned : 32U; /**< 0x006C: Reserved */
+ unsigned : 32U; /**< 0x0070: Reserved */
+ unsigned PCREG; /**< 0x0074: Parity control register */
+ unsigned PAR; /**< 0x0078: Parity address register */
+ unsigned PPR; /**< 0x007C: Parity pin select register */
+ unsigned SFPRLD; /**< 0x0080: Suppression filter preload register */
+ unsigned SFENA; /**< 0x0084: Suppression filter enable register */
+ unsigned : 32U; /**< 0x0088: Reserved */
+ unsigned LBPSEL; /**< 0x008C: Loop back pair select register */
+ unsigned LBPDIR; /**< 0x0090: Loop back pair direction register */
+} hetBASE_t;
+
+
+/** @def hetREG
+* @brief HET Register Frame Pointer
+*
+* This pointer is used by the HET driver to access the het module registers.
+*/
+#define hetREG ((hetBASE_t *)0xFFF7B800U)
+
+
+/** @def hetPORT
+* @brief HET GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of HET
+* (use the GIO drivers to access the port pins).
+*/
+#define hetPORT ((gioPORT_t *)0xFFF7B84CU)
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/ParTest.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/ParTest.c
new file mode 100644
index 000000000..4ac4170dd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/ParTest.c
@@ -0,0 +1,144 @@
+/*
+ FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license
+ and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/*-----------------------------------------------------------
+ * Simple IO routines to control the LEDs.
+ *-----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo includes. */
+#include "partest.h"
+
+/* Library includes. */
+#include "het.h"
+
+/* Port bits connected to LEDs. */
+const unsigned long ulLEDBits[] = { 25, 18, 29, /* Bottom row. */
+ 17, 31, 0, /* Top row. */
+ 2, 5, 20, /* Red1, blue1, green1 */
+ 4, 27, 16 }; /* Red2, blue2, green2 */
+
+/* 1 turns a white LED on, or a coloured LED off. */
+const unsigned long ulOnStates[] = { 1, 1, 1,
+ 1, 1, 1,
+ 0, 0, 0,
+ 0, 0, 0 };
+
+const unsigned long ulNumLEDs = sizeof( ulLEDBits ) / sizeof( unsigned long );
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+unsigned long ul;
+
+ /* Initalise the IO ports that drive the LEDs */
+ gioSetDirection( hetPORT, 0xFFFFFFFF );
+
+ /* Turn all the LEDs off. */
+ for( ul = 0; ul < ulNumLEDs; ul++ )
+ {
+ gioSetBit( hetPORT, ulLEDBits[ ul ], !ulOnStates[ ul ] );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned long ulLED, signed long xValue )
+{
+ if( ulLED < ulNumLEDs )
+ {
+ if( xValue == pdFALSE )
+ {
+ xValue = !ulOnStates[ ulLED ];
+ }
+ else
+ {
+ xValue = ulOnStates[ ulLED ];
+ }
+
+ gioSetBit( hetPORT, ulLEDBits[ ulLED ], xValue );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned long ulLED )
+{
+unsigned long ulBitState;
+
+ if( ulLED < ulNumLEDs )
+ {
+ ulBitState = gioGetBit( hetPORT, ulLEDBits[ ulLED ] );
+ gioSetBit( hetPORT, ulLEDBits[ ulLED ], !ulBitState );
+ }
+}
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/RM48L950.ccxml b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/RM48L950.ccxml
new file mode 100644
index 000000000..5aa66e4cd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/RM48L950.ccxml
@@ -0,0 +1,14 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/TMS570LS3137.ccxml b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/TMS570LS3137.ccxml
new file mode 100644
index 000000000..9a3328fe7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/TMS570LS3137.ccxml
@@ -0,0 +1,14 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/flop_hercules.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/flop_hercules.c
new file mode 100644
index 000000000..3b211fbf2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/flop_hercules.c
@@ -0,0 +1,402 @@
+/*
+ FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license
+ and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/*
+ * Creates eight tasks, each of which loops continuously performing an (emulated)
+ * floating point calculation.
+ *
+ * All the tasks run at the idle priority and never block or yield. This causes
+ * all eight tasks to time slice with the idle task. Running at the idle priority
+ * means that these tasks will get pre-empted any time another task is ready to run
+ * or a time slice occurs. More often than not the pre-emption will occur mid
+ * calculation, creating a good test of the schedulers context switch mechanism - a
+ * calculation producing an unexpected result could be a symptom of a corruption in
+ * the context of a task.
+ */
+
+#include
+#include
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "flop.h"
+
+#define mathSTACK_SIZE configMINIMAL_STACK_SIZE
+#define mathNUMBER_OF_TASKS ( 8 )
+
+/* Four tasks, each of which performs a different floating point calculation.
+Each of the four is created twice. */
+static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters );
+static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters );
+
+/* These variables are used to check that all the tasks are still running. If a
+task gets a calculation wrong it will
+stop incrementing its check variable. */
+static volatile unsigned short usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+
+/* Must be called before any hardware floating point operations are
+performed to let the RTOS portable layer know that this task requires
+a floating point context. */
+#if __TI_VFP_SUPPORT__
+ extern void vPortTaskUsesFPU( void );
+#endif
+
+/*-----------------------------------------------------------*/
+
+void vStartMathTasks( unsigned portBASE_TYPE uxPriority )
+{
+ xTaskCreate( vCompetingMathTask1, ( signed char * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask2, ( signed char * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask3, ( signed char * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask4, ( signed char * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask1, ( signed char * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask2, ( signed char * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask3, ( signed char * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, NULL );
+ xTaskCreate( vCompetingMathTask4, ( signed char * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, NULL );
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask1, pvParameters )
+{
+volatile portDOUBLE d1, d2, d3, d4;
+volatile unsigned short *pusTaskCheckVariable;
+volatile portDOUBLE dAnswer;
+short sError = pdFALSE;
+
+
+ /* Must be called before any hardware floating point operations are
+ performed to let the RTOS portable layer know that this task requires
+ a floating point context. */
+ #if __TI_VFP_SUPPORT__
+ vPortTaskUsesFPU();
+ #endif
+
+ d1 = 123.4567;
+ d2 = 2345.6789;
+ d3 = -918.222;
+
+ dAnswer = ( d1 + d2 ) * d3;
+
+ /* The variable this task increments to show it is still running is passed in
+ as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for(;;)
+ {
+ d1 = 123.4567;
+ d2 = 2345.6789;
+ d3 = -918.222;
+
+ d4 = ( d1 + d2 ) * d3;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the calculation does not match the expected constant, stop the
+ increment of the check variable. */
+ if( fabs( d4 - dAnswer ) > 0.001 )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ }
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask2, pvParameters )
+{
+volatile portDOUBLE d1, d2, d3, d4;
+volatile unsigned short *pusTaskCheckVariable;
+volatile portDOUBLE dAnswer;
+short sError = pdFALSE;
+
+ /* Must be called before any hardware floating point operations are
+ performed to let the RTOS portable layer know that this task requires
+ a floating point context. */
+ #if __TI_VFP_SUPPORT__
+ vPortTaskUsesFPU();
+ #endif
+
+ d1 = -389.38;
+ d2 = 32498.2;
+ d3 = -2.0001;
+
+ dAnswer = ( d1 / d2 ) * d3;
+
+
+ /* The variable this task increments to show it is still running is passed in
+ as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ /* Keep performing a calculation and checking the result against a constant. */
+ for( ;; )
+ {
+ d1 = -389.38;
+ d2 = 32498.2;
+ d3 = -2.0001;
+
+ d4 = ( d1 / d2 ) * d3;
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ /* If the calculation does not match the expected constant, stop the
+ increment of the check variable. */
+ if( fabs( d4 - dAnswer ) > 0.001 )
+ {
+ sError = pdTRUE;
+ }
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ variable so we know
+ this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+ }
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask3, pvParameters )
+{
+volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
+volatile unsigned short *pusTaskCheckVariable;
+const size_t xArraySize = 10;
+size_t xPosition;
+short sError = pdFALSE;
+
+ /* Must be called before any hardware floating point operations are
+ performed to let the RTOS portable layer know that this task requires
+ a floating point context. */
+ #if __TI_VFP_SUPPORT__
+ vPortTaskUsesFPU();
+ #endif
+
+ /* The variable this task increments to show it is still running is passed in
+ as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ array. Then run through the array adding up all the values. If the two totals
+ do not match, stop the check variable from incrementing. */
+ for( ;; )
+ {
+ dTotal1 = 0.0;
+ dTotal2 = 0.0;
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ pdArray[ xPosition ] = ( portDOUBLE ) xPosition + 5.5;
+ dTotal1 += ( portDOUBLE ) xPosition + 5.5;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ dTotal2 += pdArray[ xPosition ];
+ }
+
+ dDifference = dTotal1 - dTotal2;
+ if( fabs( dDifference ) > 0.001 )
+ {
+ sError = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+static portTASK_FUNCTION( vCompetingMathTask4, pvParameters )
+{
+volatile portDOUBLE *pdArray, dTotal1, dTotal2, dDifference;
+volatile unsigned short *pusTaskCheckVariable;
+const size_t xArraySize = 10;
+size_t xPosition;
+short sError = pdFALSE;
+
+ /* Must be called before any hardware floating point operations are
+ performed to let the RTOS portable layer know that this task requires
+ a floating point context. */
+ #if __TI_VFP_SUPPORT__
+ vPortTaskUsesFPU();
+ #endif
+
+ /* The variable this task increments to show it is still running is passed in
+ as the parameter. */
+ pusTaskCheckVariable = ( unsigned short * ) pvParameters;
+
+ pdArray = ( portDOUBLE * ) pvPortMalloc( xArraySize * sizeof( portDOUBLE ) );
+
+ /* Keep filling an array, keeping a running total of the values placed in the
+ array. Then run through the array adding up all the values. If the two totals
+ do not match, stop the check variable from incrementing. */
+ for( ;; )
+ {
+ dTotal1 = 0.0;
+ dTotal2 = 0.0;
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ pdArray[ xPosition ] = ( portDOUBLE ) xPosition * 12.123;
+ dTotal1 += ( portDOUBLE ) xPosition * 12.123;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ for( xPosition = 0; xPosition < xArraySize; xPosition++ )
+ {
+ dTotal2 += pdArray[ xPosition ];
+ }
+
+ dDifference = dTotal1 - dTotal2;
+ if( fabs( dDifference ) > 0.001 )
+ {
+ sError = pdTRUE;
+ }
+
+ #if configUSE_PREEMPTION == 0
+ taskYIELD();
+ #endif
+
+ if( sError == pdFALSE )
+ {
+ /* If the calculation has always been correct, increment the check
+ variable so we know this task is still running okay. */
+ ( *pusTaskCheckVariable )++;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+/* This is called to check that all the created tasks are still running. */
+portBASE_TYPE xAreMathsTaskStillRunning( void )
+{
+/* Keep a history of the check variables so we know if they have been incremented
+since the last call. */
+static unsigned short usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned short ) 0 };
+portBASE_TYPE xReturn = pdTRUE, xTask;
+
+ /* Check the maths tasks are still running by ensuring their check variables
+ are still incrementing. */
+ for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ )
+ {
+ if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] )
+ {
+ /* The check has not incremented so an error exists. */
+ xReturn = pdFALSE;
+ }
+
+ usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ];
+ }
+
+ return xReturn;
+}
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/flop_hercules.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/flop_hercules.h
new file mode 100644
index 000000000..145876c76
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/flop_hercules.h
@@ -0,0 +1,77 @@
+/*
+ FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license
+ and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+#ifndef FLOP_TASKS_H
+#define FLOP_TASKS_H
+
+void vStartMathTasks( unsigned portBASE_TYPE uxPriority );
+portBASE_TYPE xAreMathsTaskStillRunning( void );
+
+#endif
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/main.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/main.c
new file mode 100644
index 000000000..60874e929
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/main.c
@@ -0,0 +1,200 @@
+/*
+ FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license
+ and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/******************************************************************************
+ * This project provides two demo applications. A simple blinky style project,
+ * and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to
+ * select between the two. The simply blinky demo is implemented and described
+ * in main_blinky.c. The more comprehensive test and demo application is
+ * implemented and described in main_full.c.
+ *
+ * This file implements the code that is not demo specific, including the
+ * hardware setup and FreeRTOS hook functions.
+ *
+ */
+
+/* Standard includes. */
+#include
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard demo includes - just needed for the LED (ParTest) initialisation
+function. */
+#include "partest.h"
+
+/* Library includes. */
+#include "het.h"
+
+/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo,
+or 0 to run the more comprehensive test and demo application. */
+#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Set up the hardware ready to run this demo.
+ */
+static void prvSetupHardware( void );
+
+/*
+ * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0.
+ */
+extern void main_blinky( void );
+extern void main_full( void );
+
+/*-----------------------------------------------------------*/
+
+/* See the documentation page for this demo on the FreeRTOS.org web site for
+full information - including hardware setup requirements. */
+int main( void )
+{
+ /* Prepare the hardware to run this demo. */
+ prvSetupHardware();
+
+ /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top
+ of this file. */
+ #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1
+ {
+ main_blinky();
+ }
+ #else
+ {
+ main_full();
+ }
+ #endif
+
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupHardware( void )
+{
+ /* Perform any configuration necessary to use the ParTest LED output
+ functions. */
+ vParTestInitialise();
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+ /* vApplicationMallocFailedHook() will only be called if
+ configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook
+ function that will get called if a call to pvPortMalloc() fails.
+ pvPortMalloc() is called internally by the kernel whenever a task, queue,
+ timer or semaphore is created. It is also called by various parts of the
+ demo application. If heap_1.c or heap_2.c are used, then the size of the
+ heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+ FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+ to query the size of free heap space that remains (although it does not
+ provide information on how the remaining heap might be fragmented). */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+ /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+ to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle
+ task. It is essential that code added to this hook function never attempts
+ to block in any way (for example, call xQueueReceive() with a block time
+ specified, or call vTaskDelay()). If the application makes use of the
+ vTaskDelete() API function (as this demo application does) then it is also
+ important that vApplicationIdleHook() is permitted to return to its calling
+ function, because it is the responsibility of the idle task to clean up
+ memory allocated by the kernel to any task that has since been deleted. */
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName )
+{
+ ( void ) pcTaskName;
+ ( void ) pxTask;
+
+ /* Run time stack overflow checking is performed if
+ configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
+ function is called if a stack overflow is detected. */
+ taskDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationTickHook( void )
+{
+ /* This function will be called by each tick interrupt if
+ configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be
+ added here, but the tick hook is called from an interrupt context, so
+ code must not attempt to block, and only the interrupt safe FreeRTOS API
+ functions can be used (those that end in FromISR()). */
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/main_blinky.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/main_blinky.c
new file mode 100644
index 000000000..c920a7c32
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/main_blinky.c
@@ -0,0 +1,239 @@
+/*
+ FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license
+ and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/******************************************************************************
+ * NOTE 1: This project provides two demo applications. A simple blinky style
+ * project, and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c. This file implements the simply blinky style version.
+ *
+ * NOTE 2: This file only contains the source code that is specific to the
+ * basic demo. Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks. It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 200 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky(). Once the value is sent, the task loops
+ * back around to block for another 200 milliseconds.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky(). When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, toggles an LED. The 'block
+ * time' parameter passed to the queue receive function specifies that the
+ * task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue. The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue. As the queue
+ * send task writes to the queue every 200 milliseconds, the queue receive
+ * task leaves the Blocked state every 200 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Standard includes. */
+#include
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+/* Common demo includes. */
+#include "partest.h"
+
+/* Priorities at which the tasks are created. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue. The 200ms value is converted
+to ticks using the portTICK_RATE_MS constant. */
+#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
+
+/* The number of items the queue can hold. This is 1 as the receive task
+will remove items as they are added, meaning the send task should always find
+the queue empty. */
+#define mainQUEUE_LENGTH ( 1 )
+
+/* Values passed to the two tasks just to check the task parameter
+functionality. */
+#define mainQUEUE_SEND_PARAMETER ( 0x1111UL )
+#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*
+ * Called by main() to create the simply blinky style application if
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1.
+ */
+void main_blinky( void );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static xQueueHandle xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+void main_blinky( void )
+{
+ /* Create the queue. */
+ xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
+
+ if( xQueue != NULL )
+ {
+ /* Start the two tasks as described in the comments at the top of this
+ file. */
+ xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */
+ ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */
+ configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */
+ ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */
+ mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */
+ NULL ); /* The task handle is not required, so NULL is passed. */
+
+ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+ /* Start the tasks and timer running. */
+ vTaskStartScheduler();
+ }
+
+ /* If all is well, the scheduler will now be running, and the following
+ line will never be reached. If the following line does execute, then
+ there was insufficient FreeRTOS heap memory available for the idle and/or
+ timer tasks to be created. See the memory management section on the
+ FreeRTOS web site for more details. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+portTickType xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+
+ /* Check the task parameter is as expected. */
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER );
+
+ /* Initialise xNextWakeTime - this only needs to be done once. */
+ xNextWakeTime = xTaskGetTickCount();
+
+ for( ;; )
+ {
+ /* Place this task in the blocked state until it is time to run again.
+ The block time is specified in ticks, the constant used converts ticks
+ to ms. While in the Blocked state this task will not consume any CPU
+ time. */
+ vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+ /* Send to the queue - causing the queue receive task to unblock and
+ toggle the LED. 0 is used as the block time so the sending operation
+ will not block - it shouldn't need to block as the queue should always
+ be empty at this point in the code. */
+ xQueueSend( xQueue, &ulValueToSend, 0U );
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+
+ /* Check the task parameter is as expected. */
+ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER );
+
+ for( ;; )
+ {
+ /* Wait until something arrives in the queue - this task will block
+ indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+ FreeRTOSConfig.h. */
+ xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+ /* To get here something must have been received from the queue, but
+ is it the expected value? If it is, toggle the LED. */
+ if( ulReceivedValue == 100UL )
+ {
+ vParTestToggleLED( 0 );
+ ulReceivedValue = 0U;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/main_full.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/main_full.c
new file mode 100644
index 000000000..12cb97f74
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/main_full.c
@@ -0,0 +1,383 @@
+/*
+ FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license
+ and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/******************************************************************************
+ * NOTE 1: This project provides two demo applications. A simple blinky style
+ * project, and a more comprehensive test and demo application. The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c. This file implements the comprehensive test and demo version.
+ *
+ * NOTE 2: This file only contains the source code that is specific to the
+ * full demo. Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware, are defined in main.c.
+ ******************************************************************************
+ *
+ * main_full() creates all the demo application tasks and software timers,
+ * then starts the scheduler. The web documentation provides more details of
+ * the standard demo application tasks, which provide no particular
+ * functionality, but do provide a good example of how to use the FreeRTOS API.
+ *
+ * In addition to the standard demo tasks, the following tasks and tests are
+ * defined and/or created within this file:
+ *
+ * "Check" timer - The check software timer period is set to three seconds.
+ * The callback function associated with the check software timer checks that
+ * all the standard demo tasks are not only still executing, but are executing
+ * without reporting any errors. If the check software timer discovers that a
+ * task has either stalled, or reported an error, then the error is logged and
+ * the check software timer toggles the red LEDs. If an error has never been
+ * latched, the check software timer toggles the green LEDs. Therefore, if the
+ * system is executing correctly, the green LEDs will toggle every three
+ * seconds, and if an error has ever been detected, the red LEDs will toggle
+ * every three seconds.
+ *
+ * "Reg test" tasks - These fill both the core and floating point registers
+ * with known values, then check that each register maintains its expected
+ * value for the lifetime of the tasks. Each task uses a different set of
+ * values. The reg test tasks execute with a very low priority, so get
+ * preempted very frequently. A register containing an unexpected value is
+ * indicative of an error in the context switching mechanism.
+ *
+ * "LED" software timer - The callback function associated with the LED
+ * software time maintains a pattern of spinning white LEDs.
+ *
+ * See the documentation page for this demo on the FreeRTOS.org web site for
+ * full information, including hardware setup requirements.
+ */
+
+/* Standard includes. */
+#include
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "semphr.h"
+
+/* Standard demo application includes. */
+#include "integer.h"
+#include "PollQ.h"
+#include "semtest.h"
+#include "dynamic.h"
+#include "BlockQ.h"
+#include "blocktim.h"
+#include "countsem.h"
+#include "GenQTest.h"
+#include "recmutex.h"
+#include "death.h"
+#include "partest.h"
+#include "flop.h"
+#include "serial.h"
+#include "comtest.h"
+
+/* Priorities for the demo application tasks. */
+#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL )
+#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL )
+#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL )
+#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL )
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
+#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
+#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY )
+
+/* A block time of zero simply means "don't block". */
+#define mainDONT_BLOCK ( 0UL )
+
+/* The period after which the check timer will expire, converted to ticks. */
+#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
+
+/* The period after which the LED timer will expire, converted to ticks. */
+#define mainLED_TIMER_PERIOD_MS ( 75UL / portTICK_RATE_MS )
+
+/* Constants for the ComTest tasks. */
+#define mainCOM_TEST_BAUD_RATE ( ( unsigned long ) 19200 )
+#define mainCOM_TEST_LED ( 100 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The check timer callback function, as described at the top of this file.
+ */
+static void prvCheckTimerCallback( xTimerHandle xTimer );
+
+/*
+ * The LED timer callback function, as described at the top of this file.
+ */
+static void prvLEDTimerCallback( xTimerHandle xTimer );
+
+/*
+ * The reg test tasks, as described at the top of this file.
+ */
+extern void vRegTestTask1( void *pvParameters );
+extern void vRegTestTask2( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* Variables that are incremented on each iteration of the reg test tasks -
+provided the tasks have not reported any errors. The check task inspects these
+variables to ensure they are still incrementing as expected. If a variable
+stops incrementing then it is likely that its associate task has stalled. */
+volatile unsigned long ulRegTest1Counter = 0, ulRegTest2Counter = 0;
+
+/*-----------------------------------------------------------*/
+
+void main_full( void )
+{
+xTimerHandle xTimer = NULL;
+
+ /* Start all the standard demo/test tasks. These have not particular
+ functionality, but do demonstrate how to use the FreeRTOS API, and test the
+ kernel port. */
+ vStartIntegerMathTasks( tskIDLE_PRIORITY );
+ vStartDynamicPriorityTasks();
+ vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
+ vCreateBlockTimeTasks();
+ vStartCountingSemaphoreTasks();
+ vStartGenericQueueTasks( tskIDLE_PRIORITY );
+ vStartRecursiveMutexTasks();
+ vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
+ vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
+ vStartMathTasks( mainFLOP_TASK_PRIORITY );
+ vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
+
+ /* Create the register test tasks, as described at the top of this file. */
+ xTaskCreate( vRegTestTask1, ( const signed char * ) "Reg1...", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ xTaskCreate( vRegTestTask2, ( const signed char * ) "Reg2...", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+
+ /* Create the software timer that performs the 'check' functionality,
+ as described at the top of this file. */
+ xTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
+ ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */
+ prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
+ );
+
+ if( xTimer != NULL )
+ {
+ xTimerStart( xTimer, mainDONT_BLOCK );
+ }
+
+ /* Create the software timer that performs the 'LED spin' functionality,
+ as described at the top of this file. */
+ xTimer = xTimerCreate( ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */
+ ( mainLED_TIMER_PERIOD_MS ), /* The timer period, in this case 75ms. */
+ pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
+ ( void * ) 0, /* The ID is not used, so can be set to anything. */
+ prvLEDTimerCallback /* The callback function that toggles the white LEDs. */
+ );
+
+ if( xTimer != NULL )
+ {
+ xTimerStart( xTimer, mainDONT_BLOCK );
+ }
+
+ /* The set of tasks created by the following function call have to be
+ created last as they keep account of the number of tasks they expect to see
+ running. */
+ vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
+
+ /* Start the scheduler. */
+ vTaskStartScheduler();
+
+ /* If all is well, the scheduler will now be running, and the following line
+ will never be reached. If the following line does execute, then there was
+ insufficient FreeRTOS heap memory available for the idle and/or timer tasks
+ to be created. See the memory management section on the FreeRTOS web site
+ for more details. */
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTimerCallback( xTimerHandle xTimer )
+{
+static long lChangeToRedLEDsAlready = pdFALSE;
+static unsigned long ulLastRegTest1Counter = 0, ulLastRegTest2Counter = 0;
+unsigned long ulErrorFound = pdFALSE;
+/* LEDs are defaulted to use the Green LEDs. The Red LEDs are used if an error
+is found. */
+static unsigned long ulLED1 = 8, ulLED2 = 11;
+const unsigned long ulRedLED1 = 6, ulRedLED2 = 9;
+
+ /* Check all the demo tasks (other than the flash tasks) to ensure
+ they are all still running, and that none have detected an error. */
+
+ if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreBlockingQueuesStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if ( xAreGenericQueueTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xIsCreateTaskStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xArePollingQueuesStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreSemaphoreTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreMathsTaskStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( xAreComTestTasksStillRunning() != pdTRUE )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ /* Check the reg test tasks are still cycling. They will stop
+ incrementing their loop counters if they encounter an error. */
+ if( ulRegTest1Counter == ulLastRegTest1Counter )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ if( ulRegTest2Counter == ulLastRegTest2Counter )
+ {
+ ulErrorFound = pdTRUE;
+ }
+
+ ulLastRegTest1Counter = ulRegTest1Counter;
+ ulLastRegTest2Counter = ulRegTest2Counter;
+
+ /* Toggle the check LEDs to give an indication of the system status. If
+ the green LEDs are toggling, then no errors have been detected. If the red
+ LEDs are toggling, then an error has been reported in at least one task. */
+ vParTestToggleLED( ulLED1 );
+ vParTestToggleLED( ulLED2 );
+
+ /* Have any errors been latch in ulErrorFound? If so, ensure the gree LEDs
+ are off, then switch to using the red LEDs. */
+ if( ulErrorFound != pdFALSE )
+ {
+ if( lChangeToRedLEDsAlready == pdFALSE )
+ {
+ lChangeToRedLEDsAlready = pdTRUE;
+
+ /* An error has been found. Switch to use the red LEDs. */
+ vParTestSetLED( ulLED1, pdFALSE );
+ vParTestSetLED( ulLED2, pdFALSE );
+ ulLED1 = ulRedLED1;
+ ulLED2 = ulRedLED2;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvLEDTimerCallback( xTimerHandle xTimer )
+{
+const unsigned long ulNumWhiteLEDs = 6;
+static unsigned long ulLit1 = 2, ulLit2 = 1;
+
+ vParTestSetLED( ulLit2, pdFALSE );
+
+ ulLit2 = ulLit1;
+ ulLit1++;
+
+ if( ulLit1 >= ulNumWhiteLEDs )
+ {
+ ulLit1 = 0;
+ }
+
+ vParTestSetLED( ulLit1, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/reg_test.asm b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/reg_test.asm
new file mode 100644
index 000000000..b35f07f5b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/reg_test.asm
@@ -0,0 +1,483 @@
+;/*
+; FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
+;
+;
+; ***************************************************************************
+; * *
+; * FreeRTOS tutorial books are available in pdf and paperback. *
+; * Complete, revised, and edited pdf reference manuals are also *
+; * available. *
+; * *
+; * Purchasing FreeRTOS documentation will not only help you, by *
+; * ensuring you get running as quickly as possible and with an *
+; * in-depth knowledge of how to use FreeRTOS, it will also help *
+; * the FreeRTOS project to continue with its mission of providing *
+; * professional grade, cross platform, de facto standard solutions *
+; * for microcontrollers - completely free of charge! *
+; * *
+; * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+; * *
+; * Thank you for using FreeRTOS, and thank you for your support! *
+; * *
+; ***************************************************************************
+;
+;
+; This file is part of the FreeRTOS distribution.
+;
+; FreeRTOS is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License (version 2) as published by the
+; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+; >>>NOTE<<< The modification to the GPL is included to allow you to
+; distribute a combined work that includes FreeRTOS without being obliged to
+; provide the source code for proprietary components outside of the FreeRTOS
+; kernel. FreeRTOS is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+; more details. You should have received a copy of the GNU General Public
+; License and the FreeRTOS license exception along with FreeRTOS; if not it
+; can be viewed here: http://www.freertos.org/a00114.html and also obtained
+; by writing to Richard Barry, contact details for whom are available on the
+; FreeRTOS WEB site.
+;
+; 1 tab == 4 spaces!
+;
+; ***************************************************************************
+; * *
+; * Having a problem? Start by reading the FAQ "My application does *
+; * not run, what could be wrong? *
+; * *
+; * http://www.FreeRTOS.org/FAQHelp.html *
+; * *
+; ***************************************************************************
+;
+;
+; http://www.FreeRTOS.org - Documentation, training, latest information,
+; license and contact details.
+;
+; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+; including FreeRTOS+Trace - an indispensable productivity tool.
+;
+; Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+; the code with commercial support, indemnification, and middleware, under
+; the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+; provide a safety engineered and independently SIL3 certified version under
+; the SafeRTOS brand: http://www.SafeRTOS.com.
+;*/
+
+;-------------------------------------------------
+;
+ .def vRegTestTask1
+ .ref ulRegTest1Counter
+
+ .if (__TI_VFP_SUPPORT__)
+ .ref vPortTaskUsesFPU
+ .endif ;__TI_VFP_SUPPORT__
+
+ .text
+ .arm
+
+vRegTestTask1:
+ .if (__TI_VFP_SUPPORT__)
+ ; Let the port layer know that this task needs its FPU context saving.
+ BL vPortTaskUsesFPU
+ .endif
+
+ ; Fill each general purpose register with a known value.
+ mov r0, #0xFF
+ mov r1, #0x11
+ mov r2, #0x22
+ mov r3, #0x33
+ mov r4, #0x44
+ mov r5, #0x55
+ mov r6, #0x66
+ mov r7, #0x77
+ mov r8, #0x88
+ mov r9, #0x99
+ mov r10, #0xAA
+ mov r11, #0xBB
+ mov r12, #0xCC
+ mov r14, #0xEE
+
+ .if (__TI_VFP_SUPPORT__)
+ ; Fill each FPU register with a known value.
+ vmov d0, r0, r1
+ vmov d1, r2, r3
+ vmov d2, r4, r5
+ vmov d3, r6, r7
+ vmov d4, r8, r9
+ vmov d5, r10, r11
+ vmov d6, r0, r1
+ vmov d7, r2, r3
+ vmov d8, r4, r5
+ vmov d9, r6, r7
+ vmov d10, r8, r9
+ vmov d11, r10, r11
+ vmov d12, r0, r1
+ vmov d13, r2, r3
+ vmov d14, r4, r5
+ vmov d15, r6, r7
+ .endif
+
+
+vRegTestLoop1:
+
+ ; Force yeild
+ swi #0
+
+ .if (__TI_VFP_SUPPORT__)
+ ; Check all the VFP registers still contain the values set above.
+ ; First save registers that are clobbered by the test.
+ push { r0-r1 }
+
+ vmov r0, r1, d0
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d1
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d2
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d3
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+ vmov r0, r1, d4
+ cmp r0, #0x88
+ bne reg1_error_loopf
+ cmp r1, #0x99
+ bne reg1_error_loopf
+ vmov r0, r1, d5
+ cmp r0, #0xAA
+ bne reg1_error_loopf
+ cmp r1, #0xBB
+ bne reg1_error_loopf
+ vmov r0, r1, d6
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d7
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d8
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d9
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+ vmov r0, r1, d10
+ cmp r0, #0x88
+ bne reg1_error_loopf
+ cmp r1, #0x99
+ bne reg1_error_loopf
+ vmov r0, r1, d11
+ cmp r0, #0xAA
+ bne reg1_error_loopf
+ cmp r1, #0xBB
+ bne reg1_error_loopf
+ vmov r0, r1, d12
+ cmp r0, #0xFF
+ bne reg1_error_loopf
+ cmp r1, #0x11
+ bne reg1_error_loopf
+ vmov r0, r1, d13
+ cmp r0, #0x22
+ bne reg1_error_loopf
+ cmp r1, #0x33
+ bne reg1_error_loopf
+ vmov r0, r1, d14
+ cmp r0, #0x44
+ bne reg1_error_loopf
+ cmp r1, #0x55
+ bne reg1_error_loopf
+ vmov r0, r1, d15
+ cmp r0, #0x66
+ bne reg1_error_loopf
+ cmp r1, #0x77
+ bne reg1_error_loopf
+
+ ; Restore the registers that were clobbered by the test.
+ pop {r0-r1}
+
+ ; VFP register test passed. Jump to the core register test.
+ b reg1_loopf_pass
+
+reg1_error_loopf:
+ ; If this line is hit then a VFP register value was found to be
+ ; incorrect.
+ b reg1_error_loopf
+
+reg1_loopf_pass:
+
+ .endif ;__TI_VFP_SUPPORT__
+
+ ; Test each general purpose register to check that it still contains the
+ ; expected known value, jumping to vRegTestError1 if any register contains
+ ; an unexpected value.
+ cmp r0, #0xFF
+ bne vRegTestError1
+ cmp r1, #0x11
+ bne vRegTestError1
+ cmp r2, #0x22
+ bne vRegTestError1
+ cmp r3, #0x33
+ bne vRegTestError1
+ cmp r4, #0x44
+ bne vRegTestError1
+ cmp r5, #0x55
+ bne vRegTestError1
+ cmp r6, #0x66
+ bne vRegTestError1
+ cmp r7, #0x77
+ bne vRegTestError1
+ cmp r8, #0x88
+ bne vRegTestError1
+ cmp r9, #0x99
+ bne vRegTestError1
+ cmp r10, #0xAA
+ bne vRegTestError1
+ cmp r11, #0xBB
+ bne vRegTestError1
+ cmp r12, #0xCC
+ bne vRegTestError1
+ cmp r14, #0xEE
+ bne vRegTestError1
+
+ ; This task is still running without jumping to vRegTestError1, so increment
+ ; the loop counter so the check task knows the task is running error free.
+ stmfd sp!, { r0-r1 }
+ ldr r0, Count1Const
+ ldr r1, [r0]
+ add r1, r1, #1
+ str r1, [r0]
+ ldmfd sp!, { r0-r1 }
+
+ ; Loop again, performing the same tests.
+ b vRegTestLoop1
+
+Count1Const .word ulRegTest1Counter
+
+vRegTestError1:
+ b vRegTestError1
+
+
+;-------------------------------------------------
+;
+ .def vRegTestTask2
+ .ref ulRegTest2Counter
+ .text
+ .arm
+;
+vRegTestTask2:
+ .if (__TI_VFP_SUPPORT__)
+ ; Let the port layer know that this task needs its FPU context saving.
+ BL vPortTaskUsesFPU
+ .endif
+
+ ; Fill each general purpose register with a known value.
+ mov r0, #0xFF000000
+ mov r1, #0x11000000
+ mov r2, #0x22000000
+ mov r3, #0x33000000
+ mov r4, #0x44000000
+ mov r5, #0x55000000
+ mov r6, #0x66000000
+ mov r7, #0x77000000
+ mov r8, #0x88000000
+ mov r9, #0x99000000
+ mov r10, #0xAA000000
+ mov r11, #0xBB000000
+ mov r12, #0xCC000000
+ mov r14, #0xEE000000
+
+ .if (__TI_VFP_SUPPORT__)
+
+ ; Fill each FPU register with a known value.
+ vmov d0, r0, r1
+ vmov d1, r2, r3
+ vmov d2, r4, r5
+ vmov d3, r6, r7
+ vmov d4, r8, r9
+ vmov d5, r10, r11
+ vmov d6, r0, r1
+ vmov d7, r2, r3
+ vmov d8, r4, r5
+ vmov d9, r6, r7
+ vmov d10, r8, r9
+ vmov d11, r10, r11
+ vmov d12, r0, r1
+ vmov d13, r2, r3
+ vmov d14, r4, r5
+ vmov d15, r6, r7
+ .endif
+
+vRegTestLoop2:
+
+ .if (__TI_VFP_SUPPORT__)
+ ; Check all the VFP registers still contain the values set above.
+ ; First save registers that are clobbered by the test.
+ push { r0-r1 }
+
+ vmov r0, r1, d0
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d1
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d2
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d3
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+ vmov r0, r1, d4
+ cmp r0, #0x88000000
+ bne reg2_error_loopf
+ cmp r1, #0x99000000
+ bne reg2_error_loopf
+ vmov r0, r1, d5
+ cmp r0, #0xAA000000
+ bne reg2_error_loopf
+ cmp r1, #0xBB000000
+ bne reg2_error_loopf
+ vmov r0, r1, d6
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d7
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d8
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d9
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+ vmov r0, r1, d10
+ cmp r0, #0x88000000
+ bne reg2_error_loopf
+ cmp r1, #0x99000000
+ bne reg2_error_loopf
+ vmov r0, r1, d11
+ cmp r0, #0xAA000000
+ bne reg2_error_loopf
+ cmp r1, #0xBB000000
+ bne reg2_error_loopf
+ vmov r0, r1, d12
+ cmp r0, #0xFF000000
+ bne reg2_error_loopf
+ cmp r1, #0x11000000
+ bne reg2_error_loopf
+ vmov r0, r1, d13
+ cmp r0, #0x22000000
+ bne reg2_error_loopf
+ cmp r1, #0x33000000
+ bne reg2_error_loopf
+ vmov r0, r1, d14
+ cmp r0, #0x44000000
+ bne reg2_error_loopf
+ cmp r1, #0x55000000
+ bne reg2_error_loopf
+ vmov r0, r1, d15
+ cmp r0, #0x66000000
+ bne reg2_error_loopf
+ cmp r1, #0x77000000
+ bne reg2_error_loopf
+
+ ; Restore the registers that were clobbered by the test.
+ pop {r0-r1}
+
+ ; VFP register test passed. Jump to the core register test.
+ b reg2_loopf_pass
+
+reg2_error_loopf:
+ ; If this line is hit then a VFP register value was found to be
+ ; incorrect.
+ b reg2_error_loopf
+
+reg2_loopf_pass:
+
+ .endif ;__TI_VFP_SUPPORT__
+
+ ; Test each general purpose register to check that it still contains the
+ ; expected known value, jumping to vRegTestError2 if any register contains
+ ; an unexpected value.
+ cmp r0, #0xFF000000
+ bne vRegTestError2
+ cmp r1, #0x11000000
+ bne vRegTestError2
+ cmp r2, #0x22000000
+ bne vRegTestError2
+ cmp r3, #0x33000000
+ bne vRegTestError2
+ cmp r4, #0x44000000
+ bne vRegTestError2
+ cmp r5, #0x55000000
+ bne vRegTestError2
+ cmp r6, #0x66000000
+ bne vRegTestError2
+ cmp r7, #0x77000000
+ bne vRegTestError2
+ cmp r8, #0x88000000
+ bne vRegTestError2
+ cmp r9, #0x99000000
+ bne vRegTestError2
+ cmp r10, #0xAA000000
+ bne vRegTestError2
+ cmp r11, #0xBB000000
+ bne vRegTestError2
+ cmp r12, #0xCC000000
+ bne vRegTestError2
+ cmp r14, #0xEE000000
+ bne vRegTestError2
+
+ ; This task is still running without jumping to vRegTestError2, so increment
+ ; the loop counter so the check task knows the task is running error free.
+ stmfd sp!, { r0-r1 }
+ ldr r0, Count2Const
+ ldr r1, [r0]
+ add r1, r1, #1
+ str r1, [r0]
+ ldmfd sp!, { r0-r1 }
+
+ ; Loop again, performing the same tests.
+ b vRegTestLoop2
+
+Count2Const .word ulRegTest2Counter
+
+vRegTestError2:
+ b vRegTestError2
+
+;-------------------------------------------------
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/serial.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/serial.c
new file mode 100644
index 000000000..46da7308c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/serial.c
@@ -0,0 +1,328 @@
+/*
+ FreeRTOS V7.3.0 - Copyright (C) 2012 Real Time Engineers Ltd.
+
+ FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
+ http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS tutorial books are available in pdf and paperback. *
+ * Complete, revised, and edited pdf reference manuals are also *
+ * available. *
+ * *
+ * Purchasing FreeRTOS documentation will not only help you, by *
+ * ensuring you get running as quickly as possible and with an *
+ * in-depth knowledge of how to use FreeRTOS, it will also help *
+ * the FreeRTOS project to continue with its mission of providing *
+ * professional grade, cross platform, de facto standard solutions *
+ * for microcontrollers - completely free of charge! *
+ * *
+ * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
+ * *
+ * Thank you for using FreeRTOS, and thank you for your support! *
+ * *
+ ***************************************************************************
+
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ >>>NOTE<<< The modification to the GPL is included to allow you to
+ distribute a combined work that includes FreeRTOS without being obliged to
+ provide the source code for proprietary components outside of the FreeRTOS
+ kernel. FreeRTOS is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+
+ http://www.FreeRTOS.org - Documentation, training, latest versions, license
+ and contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool.
+
+ Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
+ the code with commercial support, indemnification, and middleware, under
+ the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
+ provide a safety engineered and independently SIL3 certified version under
+ the SafeRTOS brand: http://www.SafeRTOS.com.
+*/
+
+/*
+ BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
+
+ ***NOTE***
+ The implementation provided in this file is intended to demonstrate using
+ queues to pass data into and out of interrupts, and to demonstrate context
+ switching from inside an interrupt service routine. It is *not* intended to
+ represent an efficient implementation. Real implementations should not pass
+ individual characters on queues, but instead use RAM buffers, DMA and/or
+ FIFO features as appropriate. Semaphores can be used to signal a task that
+ data is available to be processed.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "semphr.h"
+
+/* Demo application includes. */
+#include "serial.h"
+
+/*-----------------------------------------------------------*/
+
+/* Registers required to configure the SCI. */
+#define serialSCI_GCR0_REG ( * ( ( volatile unsigned long * ) 0xFFF7E400 ) )
+#define serialSCI_GCR1_REG ( * ( ( volatile unsigned long * ) 0xFFF7E404 ) )
+#define serialSCI_GCR2_REG ( * ( ( volatile unsigned long * ) 0xFFF7E408 ) )
+#define serialSCI_SETINT_REG ( * ( ( volatile unsigned long * ) 0xFFF7E40C ) )
+#define serialSCI_CLRINT_REG ( * ( ( volatile unsigned long * ) 0xFFF7E410 ) )
+#define serialSCI_SETINTLVL_REG ( * ( ( volatile unsigned long * ) 0xFFF7E414 ) )
+#define serialSCI_CLRINTLVL_REG ( * ( ( volatile unsigned long * ) 0xFFF7E418 ) )
+#define serialSCI_FLR_REG ( * ( ( volatile unsigned long * ) 0xFFF7E41C ) )
+#define serialSCI_INTVEC0_REG ( * ( ( volatile unsigned long * ) 0xFFF7E420 ) )
+#define serialSCI_INTVEC1_REG ( * ( ( volatile unsigned long * ) 0xFFF7E424 ) )
+#define serialSCI_LENGTH_REG ( * ( ( volatile unsigned long * ) 0xFFF7E428 ) )
+#define serialSCI_BAUD_REG ( * ( ( volatile unsigned long * ) 0xFFF7E42C ) )
+#define serialSCI_RD_REG ( * ( ( volatile unsigned long * ) 0xFFF7E434 ) )
+#define serialSCI_TD_REG ( * ( ( volatile unsigned long * ) 0xFFF7E438 ) )
+#define serialSCI_FUN_REG ( * ( ( volatile unsigned long * ) 0xFFF7E43C ) )
+#define serialSCI_DIR_REG ( * ( ( volatile unsigned long * ) 0xFFF7E440 ) )
+#define serialSCI_DIN_REG ( * ( ( volatile unsigned long * ) 0xFFF7E444 ) )
+#define serialSCI_DOUT_REG ( * ( ( volatile unsigned long * ) 0xFFF7E448 ) )
+#define serialSCI_DSET_REG ( * ( ( volatile unsigned long * ) 0xFFF7E44C ) )
+#define serialSCI_DCLR_REG ( * ( ( volatile unsigned long * ) 0xFFF7E450 ) )
+
+/* SCI constants */
+#define serialSCI_FE_INT ( 0x04000000 ) /* framming error */
+#define serialSCI_OE_INT ( 0x02000000 ) /* overrun error */
+#define serialSCI_PE_INT ( 0x01000000 ) /* parity error */
+#define serialSCI_RX_INT ( 0x00000200 ) /* receive buffer ready */
+#define serialSCI_TX_INT ( 0x00000100 ) /* transmit buffer ready */
+#define serialSCI_WAKE_INT ( 0x00000002 ) /* wakeup */
+#define serialSCI_BREAK_INT ( 0x00000001 ) /* break detect */
+#define serialSCI_IDLE_FLG ( 0x00000004 ) /* IDLE flasg */
+
+/* Registers required to configure the VIM. */
+#define serialVIM_REQMASKSET0_REG ( * ( ( volatile unsigned long * ) 0xFFFFFE30 ) )
+#define serialVIM_SCIHINT_RAM ( * ( ( void (**)(void) ) 0xFFF82038 ) )
+
+
+/*-----------------------------------------------------------*/
+
+/* Misc defines. */
+#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
+#define serNO_BLOCK ( ( portTickType ) 0 )
+#define serTX_BLOCK_TIME ( 40 / portTICK_RATE_MS )
+
+/*-----------------------------------------------------------*/
+
+/* The queue used to hold received characters. */
+static xQueueHandle xRxedChars = NULL;
+static xQueueHandle xCharsForTx = NULL;
+
+/*-----------------------------------------------------------*/
+
+/* UART interrupt handler. */
+__interrupt void vSCIInterruptHandler( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See the serial2.h header file.
+ */
+xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+xComPortHandle xReturn = ( xComPortHandle ) 0;
+
+ /* unused parameters, demo has a fixed baud rate (19200) */
+ ( void ) ulWantedBaud;
+
+ /* Create the queues used to hold Rx/Tx characters. */
+ xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
+ xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
+
+ /* If the queue/semaphore was created correctly then setup the serial port
+ hardware. */
+ if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
+ {
+ /* Initalise SCI1 */
+ /* Bring SCI out of reset */
+ serialSCI_GCR0_REG = 0x00000001UL;
+ /* Disable all interrupts */
+ serialSCI_CLRINT_REG = 0xFFFFFFFFUL;
+ /* All Interrupt to SCI High Level */
+ serialSCI_CLRINTLVL_REG = 0xFFFFFFFFUL;
+ /* Global control 1 */
+ serialSCI_GCR1_REG = 0x03010032UL;
+ /* Baudrate */
+ serialSCI_BAUD_REG = 292;
+ /* Transmission length (8-bit) */
+ serialSCI_LENGTH_REG = 8 - 1;
+ /* Set SCI pins functional mode */
+ serialSCI_FUN_REG = 0x00000006UL;
+ /* Enable RX interrupt */
+ serialSCI_SETINT_REG = 0x00000200UL;
+ /* Finally start SCI1 */
+ serialSCI_GCR1_REG |= 0x00000080UL;
+
+ /* Setup interrupt routine address in VIM table */
+ serialVIM_SCIHINT_RAM = &vSCIInterruptHandler;
+ /* Enable SCI interrupt in VIM */
+ serialVIM_REQMASKSET0_REG = 0x00002000UL;
+ }
+
+ /* This demo file only supports a single port but we have to return
+ something to comply with the standard demo header file. */
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
+{
+ /* The port handle is not required as this driver only supports one port. */
+ ( void ) pxPort;
+
+ /* Get the next character from the buffer. Return false if no characters
+ are available, or arrive before xBlockTime expires. */
+ if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+ {
+ return pdTRUE;
+ }
+ else
+ {
+ return pdFALSE;
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned portSHORT usStringLength )
+{
+signed char *pxNext;
+
+ /* A couple of parameters that this port does not use. */
+ ( void ) usStringLength;
+
+ /* NOTE: This implementation does not handle the queue being full as no
+ block time is used! */
+
+ /* Send each character in the string, one at a time. */
+ pxNext = ( signed char * ) pcString;
+ while( *pxNext )
+ {
+ xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
+ pxNext++;
+ }
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
+{
+signed portBASE_TYPE xReturn;
+
+ /* check if we are already transmitting */
+ if ( (serialSCI_SETINT_REG & serialSCI_TX_INT) == 0)
+ {
+ /* First byte */
+
+ /* Wait until IDLE idle period is finished */
+ while ( (serialSCI_FLR_REG & serialSCI_IDLE_FLG) != 0 )
+ {
+ /* wait */
+ };
+
+ /* Need to send first byte before interrupts flags are set. */
+ serialSCI_TD_REG = cOutChar;
+
+ /* Enable the TX interrupt. */
+ serialSCI_SETINT_REG = serialSCI_TX_INT;
+
+ xReturn = pdPASS;
+ }
+ else if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )
+ {
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+ /* Not supported as not required by the demo application. */
+}
+/*-----------------------------------------------------------*/
+
+__interrupt void vSCIInterruptHandler( void )
+{
+/* xHigherPriorityTaskWoken must be initialised to pdFALSE. */
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+char cChar;
+portBASE_TYPE xVectorValue = serialSCI_INTVEC0_REG;
+
+ switch( xVectorValue )
+ {
+ case 11:
+ /* Receive buffer full interrupt, send received char to queue */
+ cChar = serialSCI_RD_REG;
+ xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
+ break;
+
+ case 12:
+ /* Transmit buffer empty interrupt received */
+ /* Are there any more characters to transmit? */
+ if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
+ {
+ /* A character was retrieved from the queue so can be sent to
+ the TD now. */
+ serialSCI_TD_REG = cChar;
+ }
+ else
+ {
+ /* no more bytes, clear the TX interrupt */
+ serialSCI_CLRINT_REG = serialSCI_TX_INT;
+ }
+ break;
+
+ default:
+ /* unused interrupt, clear flags */
+ serialSCI_FLR_REG = 0x07000003;
+ }
+
+ /* If calling xQueueSendFromISR() above caused a task to leave the blocked
+ state, and the task that left the blocked state has a priority above the
+ task that this interrupt interrupted, then xHighPriorityTaskWoken will have
+ been set to pdTRUE. If xHigherPriorityTaskWoken equals true then calling
+ portYIELD_FROM_ISR() will result in this interrupt returning directly to the
+ unblocked task. */
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+}
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_common.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_common.h
new file mode 100644
index 000000000..89825366f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_common.h
@@ -0,0 +1,198 @@
+/*----------------------------------------------------------------------------*/
+/* sys_common.h 10/20/10 15:19:19 */
+/* */
+/* (c) Texas Instruments 2003-2010, All rights reserved. */
+/* */
+
+
+#ifndef __sys_common_h__
+#define __sys_common_h__
+
+/*----------------------------------------------------------------------------*/
+/* NULL */
+
+#ifndef NULL
+#define NULL ((void *) 0)
+#endif
+
+/*----------------------------------------------------------------------------*/
+/* Error Codes */
+
+#define IO_E_OK 0U
+#define IO_E_BUSY 1U
+#define IO_E_UNKNOWN_MODE 2U
+#define IO_E_OVR 3U
+#define IO_E_FCN_SUSPENDED 16U
+#define IO_E_PARAM_IGNORED 17U
+#define IO_E_INVALID_CHANNEL_ID 18U
+#define IO_E_INVALID_VALUE 19U
+#define IO_E_INVALID_SIZE 20U
+#define IO_E_INVALID_POSITION 21U
+#define IO_E_INVALID_NOTIF_TYPE 22U
+#define IO_E_MISSING_INIT 64U
+#define IO_E_INVALID_GROUP_ID 66U
+#define IO_E_INVALID_POINTER 67U
+#define IO_E_INVALID_NODE 68U
+#define IO_E_INVALID_CAN_ID 69U
+#define IO_E_INVALID_OVR 70U
+#define IO_E_INVALID_CONFIG 72U
+#define IO_E_MISSING_CONNECT 73U
+#define IO_E_MISSING_DISCONNECT 74U
+#define IO_E_ALREADY_CONNECTED 75U
+#define IO_E_GRP_NOTACTIVATED 80U
+#define IO_E_INVALID_RESULT 81U
+#define IO_E_TIMEOUT 82U
+#define IO_E_INVALID_PARITY 83U
+#define IO_E_SINGLE_ERROR 84U
+#define IO_E_DOUBLE_ERROR 85U
+#define IO_E_SINGLE_ERROR_EVEN 86U
+#define IO_E_SINGLE_ERROR_ODD 87U
+#define IO_E_DOUBLE_ERROR_EVEN 88U
+#define IO_E_DOUBLE_ERROR_ODD 89U
+
+/*----------------------------------------------------------------------------*/
+/* Device Types */
+
+#define IO_SPI 0U
+#define IO_DIO 1U
+#define IO_TIM 2U
+#define IO_PWM 3U
+#define IO_CCU 4U
+#define IO_RTI 5U
+#define IO_WDT 6U
+#define IO_ADC 7U
+#define IO_SCI 8U
+#define IO_FLS 9U
+#define IO_CAN 10U
+#define IO_QSPI 11U
+#define IO_MSPI 11U
+#define IO_LIN 12U
+#define IO_CRC 13U
+#define IO_DMA 14U
+#define IO_HTU 15U
+#define IO_PWD 16U
+#define IO_HET 17U
+#define IO_ESM 18U
+#define IO_I2C 19U
+#define IO_ECC 20U
+#define IO_VIM 21U
+#define IO_STC 22U
+
+/*----------------------------------------------------------------------------*/
+/* Device States */
+
+#define IO_STATE_IDLE 0U
+#define IO_STATE_ACTIVE 1U
+
+/*----------------------------------------------------------------------------*/
+/* Notification Types */
+
+#define IO_N_RISING_EDGE 0U
+#define IO_N_FALLING_EDGE 1U
+#define IO_N_THRESHOLD_1 2U
+#define IO_N_THRESHOLD_2 3U
+#define IO_N_CAPTURE 4U
+#define IO_N_ALL 5U
+#define IO_N_ROLLOVER 6U
+#define IO_N_READY 7U
+#define IO_N_FCN_SUSPENDED 8U
+#define IO_N_PARITY_ERROR 9U
+#define IO_N_FRAMING_ERROR 10U
+#define IO_N_BUFFER_OVERRUN 11U
+#define IO_N_RECEIVE 12U
+#define IO_N_TRANSMIT 13U
+#define IO_N_TX_ERROR 15U
+#define IO_N_RX_ERROR 16U
+#define IO_N_BAUDRATE_ERROR 17U
+#define IO_N_PHASE_ERROR 18U
+#define IO_N_OCSET 19U
+#define IO_N_OCRESET 20U
+#define IO_N_RX_LOST 21U
+#define IO_N_ACTIVE 22U
+#define IO_N_WARNING 23U
+#define IO_N_PASSIVE 24U
+#define IO_N_BUS_OFF 25U
+#define IO_N_WAKE_UP 26U
+#define IO_N_LAST_ERROR 27U
+#define IO_N_GRP_READY 30U
+#define IO_N_ERROR 31U
+#define IO_N_HDR_RECEIVE 32U
+#define IO_N_HDR_TRANSMIT 33U
+#define IO_N_ID_ERROR 34U
+#define IO_N_CHECKSUM_ERROR 35U
+#define IO_N_BIT_ERROR 36U
+#define IO_N_FRAME_TIMEOUT 37U
+#define IO_N_BUS_ERROR 38U
+#define IO_N_SYNC_FIELD_ERROR 39U
+#define IO_N_WAKE_UP_RECEIVE 40U
+#define IO_N_WAKE_UP_TRANSMIT 41U
+#define IO_N_ADJUST_BAUDRATE 42U
+#define IO_N_BUS_IDLE_TIMEOUT 43U
+#define IO_N_WAKE_UP_TIMEOUT 44U
+
+/*----------------------------------------------------------------------------*/
+/* Programming Interface Constants */
+
+#define IO_LOW 0U
+#define IO_HIGH 1U
+#define IO_INVALID 0xFFFFU
+
+/*----------------------------------------------------------------------------*/
+/* Data Types */
+
+typedef T_U32 IO_ErrorType;
+typedef T_U32 IO_DeviceType;
+typedef T_U32 IO_FunctionNrType;
+typedef T_U32 IO_DeviceStateType;
+typedef T_U32 IO_ChannelType;
+typedef T_U32 IO_ModeType;
+typedef T_U32 IO_ValueType;
+typedef T_U32 IO_U32;
+
+/*----------------------------------------------------------------------------*/
+/* Error hook */
+
+void IO_ErrorHook(IO_DeviceType device, IO_ErrorType error);
+
+/*----------------------------------------------------------------------------*/
+/* ISR Function Prototypes */
+
+void IO_PHANTOM_INT(void);
+void IO_ESM_INT_HIGH(void);
+void IO_TIM0_INT(void);
+void IO_TIM1_INT(void);
+void IO_DIO_INT_HIGH(void);
+void IO_HET_INT_HIGH(void);
+void IO_HTU_INT_HIGH(void);
+void IO_MIBSPI1_INT_HIGH(void);
+void IO_LIN_INT_HIGH(void);
+void IO_MIBADC_INT_GROUP0(void);
+void IO_MIBADC_INT_GROUP1(void);
+void IO_CAN1_INT_HIGH(void);
+void IO_SPI2_INT_HIGH(void);
+void IO_ESM_INT_LOW(void);
+void IO_DIO_INT_LOW(void);
+void IO_HET_INT_LOW(void);
+void IO_HTU_INT_LOW(void);
+void IO_MIBSPI1_INT_LOW(void);
+void IO_LIN_INT_LOW(void);
+void IO_MIBADC_INT_GROUP2(void);
+void IO_CAN1_INT_LOW(void);
+void IO_SPI2_INT_LOW(void);
+void IO_MIBADC_INT_MAG(void);
+void IO_DMA_INT_FTCA(void);
+void IO_DMA_INT_LFSA(void);
+void IO_CAN2_INT_HIGH(void);
+void IO_MIBSPI3_INT_HIGH(void);
+void IO_MIBSPI3_INT_LOW(void);
+void IO_DMA_INT_HBCA(void);
+void IO_DMA_INT_BTCA(void);
+void IO_CAN2_INT_LOW(void);
+
+/*----------------------------------------------------------------------------*/
+/* Notification Function Prototypes */
+
+
+#endif
+/*----------------------------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_core.asm b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_core.asm
new file mode 100644
index 000000000..3cb2accdb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_core.asm
@@ -0,0 +1,165 @@
+;-------------------------------------------------------------------------------
+; sys_core.asm
+;
+; (c) Texas Instruments 2009, All rights reserved.
+;
+
+ .text
+ .arm
+
+;-------------------------------------------------------------------------------
+; Initialize CPU Registers
+
+ .def _coreInitRegisters
+
+_coreInitRegisters:
+ mov r0, lr
+ mov r1, #0x0000
+ mov r2, #0x0000
+ mov r3, #0x0000
+ mov r4, #0x0000
+ mov r5, #0x0000
+ mov r6, #0x0000
+ mov r7, #0x0000
+ mov r8, #0x0000
+ mov r9, #0x0000
+ mov r10, #0x0000
+ mov r11, #0x0000
+ mov r12, #0x0000
+ mov r13, #0x0000
+ cps #0x11
+ mov lr, r0
+ mov r8, #0x0000
+ mov r9, #0x0000
+ mov r10, #0x0000
+ mov r11, #0x0000
+ mov r12, #0x0000
+ mov r13, #0x0000
+ cps #0x12
+ mov r13, #0x0000
+ mov lr, r0
+ cps #0x17
+ mov r13, #0x0000
+ mov lr, r0
+ cps #0x1B
+ mov r13, #0x0000
+ mov lr, r0
+ cps #0x13
+ mov r13, #0x0000
+
+ .if (__TI_VFPV3D16_SUPPORT__)
+ fmdrr d0, r1, r1
+ fmdrr d1, r1, r1
+ fmdrr d2, r1, r1
+ fmdrr d3, r1, r1
+ fmdrr d4, r1, r1
+ fmdrr d5, r1, r1
+ fmdrr d6, r1, r1
+ fmdrr d7, r1, r1
+ fmdrr d8, r1, r1
+ fmdrr d9, r1, r1
+ fmdrr d10, r1, r1
+ fmdrr d11, r1, r1
+ fmdrr d12, r1, r1
+ fmdrr d13, r1, r1
+ fmdrr d14, r1, r1
+ fmdrr d15, r1, r1
+ .endif
+
+ bl $+4
+ bl $+4
+ bl $+4
+ bl $+4
+ bx r0
+
+
+;-------------------------------------------------------------------------------
+; Initialize Stack Pointers
+
+ .def _coreInitStackPointer
+
+_coreInitStackPointer:
+ msr cpsr_c, #0xD1
+ ldr sp, fiqSp
+ msr cpsr_c, #0xD2
+ ldr sp, irqSp
+ msr cpsr_c, #0xD7
+ ldr sp, abortSp
+ msr cpsr_c, #0xDB
+ ldr sp, undefSp
+ msr cpsr_c, #0xDF
+ ldr sp, userSp
+ msr cpsr_c, #0xD3
+ ldr sp, svcSp
+ bx lr
+
+userSp .word 0x00000000+0x00000000
+svcSp .word 0x08000000+0x00000100
+fiqSp .word 0x00000000+0x00000000
+irqSp .word 0x08000100+0x00000100
+abortSp .word 0x00000000+0x00000000
+undefSp .word 0x00000000+0x00000000
+
+
+;-------------------------------------------------------------------------------
+; Enable VFP Unit
+
+ .def _coreEnableVfp
+
+_coreEnableVfp:
+ .if (__TI_VFPV3D16_SUPPORT__)
+ mrc p15, #0x00, r0, c1, c0, #0x02
+ orr r0, r0, #0xF00000
+ mcr p15, #0x00, r0, c1, c0, #0x02
+ mov r0, #0x40000000
+ fmxr fpexc, r0
+ .endif
+ bx lr
+
+
+;-------------------------------------------------------------------------------
+; Enable Event Bus Export
+
+ .def _coreEnableEventBusExport
+
+_coreEnableEventBusExport:
+ mrc p15, #0x00, r0, c9, c12, #0x00
+ orr r0, r0, #0x10
+ mcr p15, #0x00, r0, c9, c12, #0x00
+ bx lr
+
+;-------------------------------------------------------------------------------
+; Enable RAM ECC Support
+
+ .def _coreEnableRamEcc
+
+_coreEnableRamEcc:
+ mrc p15, #0x00, r0, c1, c0, #0x01
+ orr r0, r0, #0x0C000000
+ mcr p15, #0x00, r0, c1, c0, #0x01
+ bx lr
+
+;-------------------------------------------------------------------------------
+; Enable Flash ECC Support
+
+ .def _coreEnableFlashEcc
+
+_coreEnableFlashEcc:
+ mrc p15, #0x00, r0, c1, c0, #0x01
+ orr r0, r0, #0x02000000
+ mcr p15, #0x00, r0, c1, c0, #0x01
+ bx lr
+
+;-------------------------------------------------------------------------------
+; Enable Offset via Vic controller
+
+ .def _coreEnableIrqVicOffset
+
+_coreEnableIrqVicOffset:
+ mrc p15, #0, r0, c1, c0, #0
+ orr r0, r0, #0x01000000
+ mcr p15, #0, r0, c1, c0, #0
+ bx lr
+
+;-------------------------------------------------------------------------------
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_core.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_core.h
new file mode 100644
index 000000000..32d172ace
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_core.h
@@ -0,0 +1,61 @@
+/** @file sys_core.h
+* @brief System Core Header File
+* @date 23.July.2009
+* @version 1.00.000
+*
+* This file contains:
+* - Core Interface Functions
+* .
+* which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009, All rights reserved. */
+
+#ifndef __SYS_CORE_H__
+#define __SYS_CORE_H__
+
+/* System Core Interface Functions */
+
+/** @fn void _coreInitRegisters_(void)
+* @brief Initialize Core register
+*/
+void _coreInitRegisters(void);
+
+/** @fn void _coreInitStackPointer_(void)
+* @brief Initialize Core stack pointer
+*/
+void _coreInitStackPointer(void);
+
+/** @fn void _coreEnableIrqVicOffset_(void)
+* @brief Enable Irq offset propagation via Vic controller
+*/
+void _coreEnableIrqVicOffset(void);
+
+
+/** @fn void _coreEnableEventBusExport_(void)
+* @brief Enable event bus export for external monitoring modules
+* @note It is required to enable event bus export to process ecc issues.
+*
+* This function enables event bus exports to external monitoring modules
+* like tightly coupled RAM wrapper, Flash wrapper and error signaling module.
+*/
+void _coreEnableEventBusExport(void);
+
+/** @fn void _coreEnableRamEcc_(void)
+* @brief Enable external ecc error for RAM odd and even bank
+* @note It is required to enable event bus export to process ecc issues.
+*/
+void _coreEnableRamEcc(void);
+
+/** @fn void _coreEnableFlashEcc_(void)
+* @brief Enable external ecc error for the Flash
+* @note It is required to enable event bus export to process ecc issues.
+*/
+void _coreEnableFlashEcc(void);
+
+/** @fn void _coreEnableVfp(void)
+* @brief Enable Cortex-R4 FPU
+*/
+void _coreEnableVfp();
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_esm.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_esm.c
new file mode 100644
index 000000000..88005e930
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_esm.c
@@ -0,0 +1,31 @@
+/** @file sys_esm.c
+* @brief Phantom Interrupt Source File
+* @date 15.July.2009
+* @version 1.00.000
+*
+* This file contains:
+* - Phantom Interrupt Handler
+*/
+
+#include "gio.h"
+#include "het.h"
+
+
+/* ESM (Non-Maskable) Interrupt Handler */
+
+#pragma INTERRUPT(esmHighLevelInterrupt, FIQ)
+
+void esmHighLevelInterrupt(void)
+{
+ /* too indicate we are in the ESM interrupt light up the BLUE leds */
+
+ /* Initalise the IO ports that drive the LEDs */
+ gioSetDirection(hetPORT, 0xFFFFFFFF);
+ /* switch all leds off */
+ gioSetPort(hetPORT, 0x08110034);
+ /* switch on blue leds */
+ gioSetBit(hetPORT, 5, 0);
+ gioSetBit(hetPORT, 27, 0);
+
+ for(;;);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_intvecs.asm b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_intvecs.asm
new file mode 100644
index 000000000..443b5ba90
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_intvecs.asm
@@ -0,0 +1,28 @@
+;-------------------------------------------------------------------------------
+; sys_intvecs.asm
+;
+; (c) Texas Instruments 2009-2010, All rights reserved.
+;
+
+ .sect ".intvecs"
+
+;-------------------------------------------------------------------------------
+; import reference for interrupt routines
+
+ .ref _c_int00
+ .ref vPortYieldProcessor
+
+;-------------------------------------------------------------------------------
+; interrupt vectors
+
+ b _c_int00 ; reset
+ b #-8 ; undefined instruction
+ b vPortYieldProcessor ; software interrupt
+ b #-8 ; Abort (prefetch)
+ b #-8 ; Abort (data)
+ b #-8 ; Reserved
+ ldr pc,[pc,#-0x1b0] ; IRQ
+ ldr pc,[pc,#-0x1b0] ; FIQ
+
+
+;-------------------------------------------------------------------------------
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_memory.asm b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_memory.asm
new file mode 100644
index 000000000..eed00b2ea
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_memory.asm
@@ -0,0 +1,36 @@
+;-------------------------------------------------------------------------------
+; sys_memory.asm
+;
+; (c) Texas Instruments 2009, All rights reserved.
+;
+
+ .text
+ .arm
+
+
+;-------------------------------------------------------------------------------
+; Initialize memory
+
+ .def _memoryInit
+
+_memoryInit:
+ ldr r12, regMinitGcr ; MINITGCR register pointer
+ mov r4, #0xA
+ str r4, [r12]
+ ldr r4, ramInitMask ; load RAM initialization mask
+ str r4, [r12, #4]
+mloop
+ ldr r5, [r12, #12]
+ tst r5, #0x100
+ beq mloop
+ mov r4, #5
+ str r4, [r12]
+ bx lr
+
+ramInitMask .word 0x00000001
+regMinitGcr .word 0xFFFFFF5C
+
+
+
+;-------------------------------------------------------------------------------
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_memory.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_memory.h
new file mode 100644
index 000000000..34c59e005
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_memory.h
@@ -0,0 +1,22 @@
+/** @file sys_memory.h
+* @brief System Memory Header File
+* @date 23.July.2009
+* @version 1.00.000
+*
+* This file contains:
+* - Memory Interface Functions
+* .
+* which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009, All rights reserved. */
+
+#ifndef __SYS_MEMORY_H__
+#define __SYS_MEMORY_H__
+
+/** @fn void _memoryInit_(void)
+* @brief Automatic hardware memory initialization
+*/
+void _memoryInit(void);
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_phantom.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_phantom.c
new file mode 100644
index 000000000..9dfee7d71
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_phantom.c
@@ -0,0 +1,31 @@
+/** @file sys_phantom.c
+* @brief Phantom Interrupt Source File
+* @date 15.July.2009
+* @version 1.00.000
+*
+* This file contains:
+* - Phantom Interrupt Handler
+*/
+
+#include "gio.h"
+#include "het.h"
+
+
+/* Phantom Interrupt Handler */
+
+#pragma INTERRUPT(phantomInterrupt, IRQ)
+
+void phantomInterrupt(void)
+{
+ /* too indicate we are in the phantom interrupt light up the BLUE leds */
+
+ /* Initalise the IO ports that drive the LEDs */
+ gioSetDirection(hetPORT, 0xFFFFFFFF);
+ /* switch all leds off */
+ gioSetPort(hetPORT, 0x08110034);
+ /* switch on blue leds */
+ gioSetBit(hetPORT, 5, 0);
+ gioSetBit(hetPORT, 27, 0);
+
+ for(;;);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_startup.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_startup.c
new file mode 100644
index 000000000..c4679c53e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_startup.c
@@ -0,0 +1,315 @@
+/** @file sys_startup.c
+* @brief Startup Source File
+* @date 05.November.2010
+* @version 1.01.001
+*
+* This file contains:
+* - Include Files
+* - Type Definitions
+* - External Functions
+* - VIM RAM Setup
+* - Startup Routine
+* .
+* which are relevant for the Starup.
+*/
+
+/* (c) Texas Instruments 2010, All rights reserved. */
+
+/* Include Files */
+
+#include "sys_types.h"
+#include "sys_common.h"
+#include "sys_system.h"
+#include "sys_vim.h"
+#include "sys_core.h"
+#include "sys_memory.h"
+
+
+/* External Functions */
+
+extern void __TI_auto_init(void);
+extern void main(void);
+extern void exit(int);
+
+/* Vim Ram Definition */
+/** @struct vimRam
+* @brief Vim Ram Definition
+*
+* This type is used to access the Vim Ram.
+*/
+
+static const t_isrFuncPTR s_vim_init[] =
+{
+ phantomInterrupt,
+ esmHighLevelInterrupt,
+ phantomInterrupt,
+ vPortPreemptiveTick, /* RTI */
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ vPortYeildWithinAPI, /* software interrupt */
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+ phantomInterrupt,
+};
+
+
+/* Startup Routine */
+
+#pragma INTERRUPT(_c_int00, RESET)
+
+void _c_int00()
+{
+ /* Enable VFP Unit */
+ _coreEnableVfp();
+
+ /* Initialize Core Registers */
+ _coreInitRegisters();
+
+ /* Initialize Stack Pointers */
+ _coreInitStackPointer();
+
+ /* Enable IRQ offset via Vic controller */
+ _coreEnableIrqVicOffset();
+
+ /* Initialize System */
+ systemInit();
+
+ /* Initialize VIM table */
+ {
+ unsigned i;
+
+ for (i = 0; i < 96U; i++)
+ {
+ vimRAM->ISR[i] = s_vim_init[i];
+ }
+ }
+
+ /* set IRQ/FIQ priorities */
+ vimREG->FIRQPR0 = SYS_FIQ
+ | (SYS_FIQ << 1U)
+ | (SYS_IRQ << 2U)
+ | (SYS_IRQ << 3U)
+ | (SYS_IRQ << 4U)
+ | (SYS_IRQ << 5U)
+ | (SYS_IRQ << 6U)
+ | (SYS_IRQ << 7U)
+ | (SYS_IRQ << 8U)
+ | (SYS_IRQ << 9U)
+ | (SYS_IRQ << 10U)
+ | (SYS_IRQ << 11U)
+ | (SYS_IRQ << 12U)
+ | (SYS_IRQ << 13U)
+ | (SYS_IRQ << 14U)
+ | (SYS_IRQ << 15U)
+ | (SYS_IRQ << 16U)
+ | (SYS_IRQ << 17U)
+ | (SYS_IRQ << 18U)
+ | (SYS_IRQ << 19U)
+ | (SYS_IRQ << 20U)
+ | (SYS_IRQ << 21U)
+ | (SYS_IRQ << 22U)
+ | (SYS_IRQ << 23U)
+ | (SYS_IRQ << 24U)
+ | (SYS_IRQ << 25U)
+ | (SYS_IRQ << 26U)
+ | (SYS_IRQ << 27U)
+ | (SYS_IRQ << 28U)
+ | (SYS_IRQ << 29U)
+ | (SYS_IRQ << 30U)
+ | (SYS_IRQ << 31U);
+
+ vimREG->FIRQPR1 = SYS_IRQ
+ | (SYS_IRQ << 1U)
+ | (SYS_IRQ << 2U)
+ | (SYS_IRQ << 3U)
+ | (SYS_IRQ << 4U)
+ | (SYS_IRQ << 5U)
+ | (SYS_IRQ << 6U)
+ | (SYS_IRQ << 7U)
+ | (SYS_IRQ << 8U)
+ | (SYS_IRQ << 9U)
+ | (SYS_IRQ << 10U)
+ | (SYS_IRQ << 11U)
+ | (SYS_IRQ << 12U)
+ | (SYS_IRQ << 13U)
+ | (SYS_IRQ << 14U)
+ | (SYS_IRQ << 15U)
+ | (SYS_IRQ << 16U)
+ | (SYS_IRQ << 17U)
+ | (SYS_IRQ << 18U)
+ | (SYS_IRQ << 19U)
+ | (SYS_IRQ << 20U)
+ | (SYS_IRQ << 21U)
+ | (SYS_IRQ << 22U)
+ | (SYS_IRQ << 23U)
+ | (SYS_IRQ << 24U)
+ | (SYS_IRQ << 25U)
+ | (SYS_IRQ << 26U)
+ | (SYS_IRQ << 27U)
+ | (SYS_IRQ << 28U)
+ | (SYS_IRQ << 29U)
+ | (SYS_IRQ << 30U);
+
+ /* enable interrupts */
+ vimREG->REQMASKSET0 = 1U
+ | (0U << 1)
+ | (1U << 2) /* RTI */
+ | (0U << 3)
+ | (0U << 4)
+ | (0U << 5)
+ | (0U << 6)
+ | (0U << 7)
+ | (0U << 8)
+ | (0U << 9)
+ | (0U << 10)
+ | (0U << 11)
+ | (0U << 12)
+ | (0U << 13)
+ | (0U << 14)
+ | (0U << 15)
+ | (0U << 16)
+ | (0U << 17)
+ | (0U << 18)
+ | (0U << 19)
+ | (0U << 20)
+ | (1U << 21) /* Software Interrupt */
+ | (0U << 22)
+ | (0U << 23)
+ | (0U << 24)
+ | (0U << 25)
+ | (0U << 26)
+ | (0U << 27)
+ | (0U << 28)
+ | (0U << 29)
+ | (0U << 30)
+ | (0U << 31);
+
+ vimREG->REQMASKSET1 = 0U
+ | (0U << 1)
+ | (0U << 2)
+ | (0U << 3)
+ | (0U << 4)
+ | (0U << 5)
+ | (0U << 6)
+ | (0U << 7)
+ | (0U << 8)
+ | (0U << 9)
+ | (0U << 10)
+ | (0U << 11)
+ | (0U << 12)
+ | (0U << 13)
+ | (0U << 14)
+ | (0U << 15)
+ | (0U << 16)
+ | (0U << 17)
+ | (0U << 18)
+ | (0U << 19)
+ | (0U << 20)
+ | (0U << 21)
+ | (0U << 22)
+ | (0U << 23)
+ | (0U << 24)
+ | (0U << 25)
+ | (0U << 26)
+ | (0U << 27)
+ | (0U << 28)
+ | (0U << 29)
+ | (0U << 30);
+
+
+ /* initalise global variable and constructors */
+ __TI_auto_init();
+
+ /* call the application */
+ main();
+ exit(0);
+}
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_system.c b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_system.c
new file mode 100644
index 000000000..378210b7f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_system.c
@@ -0,0 +1,158 @@
+/** @file system.c
+* @brief System Driver Source File
+* @date 05.November.2010
+* @version 1.01.000
+*
+* This file contains:
+* - API Funcions
+* .
+* which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2010, All rights reserved. */
+
+
+/* Include Files */
+
+#include "sys_system.h"
+
+
+/** @fn void systemInit(void)
+* @brief Initializes System Driver
+*
+* This function initializes the System driver.
+*
+*/
+
+
+void systemInit(void)
+{
+ /** @b Initialize @b Flash @b Wrapper: */
+
+ /** - Setup flash read mode, address wait states and data wait states */
+ flashWREG->FRDCNTL = 0x01000000U
+ | (3U << 8U)
+ | (1U << 4U)
+ | 1U;
+
+#if 0
+ /** - Setup flash bank power modes */
+ flashWREG->FBFALLBACK = 0x05050000
+ | (SYS_ACTIVE << 14U)
+ | (SYS_SLEEP << 12U)
+ | (SYS_SLEEP << 10U)
+ | (SYS_SLEEP << 8U)
+ | (SYS_SLEEP << 6U)
+ | (SYS_SLEEP << 4U)
+ | (SYS_ACTIVE << 2U)
+ | SYS_ACTIVE;
+
+ /** @b Initialize @b Lpo: */
+ {
+ unsigned trim = *(volatile unsigned short *)0xF00801B4;
+
+ if (trim != 0xFFFF)
+ {
+ systemREG1->LPOMONCTL = (1U << 24U)
+ | (0U << 16U)
+ | trim;
+ }
+ else
+ {
+ systemREG1->LPOMONCTL = (1U << 24U)
+ | (0U << 16U)
+ | (systemREG1->LPOMONCTL & 0xFFFF);
+ }
+ }
+#endif
+
+ /** @b Initialize @b Pll: */
+
+ /** - Setup pll control register 1:
+ * - Setup reset on oscillator slip
+ * - Setup bypass on pll slip
+ * - Setup Pll output clock divider
+ * - Setup reset on oscillator fail
+ * - Setup reference clock divider
+ * - Setup Pll multiplier
+ */
+
+ /* 180Mhz */
+ systemREG1->PLLCTL1 = 0x00000000U
+ | 0x20000000U
+ | (0U << 24U)
+ | 0x00000000U
+ | (5U << 16U)
+ | (134U << 8U);
+
+ /** - Setup pll control register 1
+ * - Enable/Disable frequency modulation
+ * - Setup spreading rate
+ * - Setup bandwidth adjustment
+ * - Setup internal Pll output divider
+ * - Setup spreading amount
+ */
+ systemREG1->PLLCTL2 = 0x00000000U
+ | (255U << 22U)
+ | (7U << 12U)
+ | (1U << 9U)
+ | 61U;
+
+ /** @b Initialize @b Clock @b Tree: */
+
+ /** - Start clock source lock */
+ systemREG1->CSDISCLR = 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000000U
+ | 0x00000002U;
+
+ /** - Wait for until clocks are locked */
+ while ((systemREG1->CSVSTAT & 0x00000002U) == 0x00); /* wait for PLL */
+
+ /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */
+ systemREG1->GHVSRC = (SYS_PLL << 24U)
+ | (SYS_PLL << 16U)
+ | SYS_PLL;
+
+ /** - Power-up all peripharals */
+ pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;
+ pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;
+ pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;
+ pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;
+
+ /** - Setup synchronous peripheral clock dividers for VCLK1 and VCLK2 */
+ systemREG1->PENA = 0U;
+ systemREG1->VCLKR = 15U;
+ systemREG1->VCLK2R = 1U;
+ systemREG1->VCLKR = 1U;
+
+ systemREG2->CLK2CNTRL = (1U << 8U)
+ | 1U;
+
+ /** - Setup RTICLK1 and RTICLK2 clocks */
+ systemREG1->RCLKSRC = (1U << 24U)
+ | (SYS_VCLK << 16U)
+ | (1U << 8U)
+ | SYS_VCLK;
+
+#if 0
+ /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */
+ systemREG1->VCLKASRC = (SYS_FR_PLL << 8U)
+ | SYS_VCLK;
+
+ /** - Setup asynchronous peripheral clock sources for AVCLK3 and AVCLK4 */
+ systemREG2->VCLKACON1 = (0U << 24U)
+ | (0U << 20U)
+ | (SYS_EXTERNAL2 << 16U)
+ | (3U << 8U)
+ | (0U << 4U)
+ | SYS_EXTERNAL;
+#endif
+
+ /** - Enable Peripherals */
+ systemREG1->PENA = 1U;
+
+ /** @note: HCLK >= VCLK2 >= VCLK_sys */
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_system.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_system.h
new file mode 100644
index 000000000..d3b5fab43
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_system.h
@@ -0,0 +1,434 @@
+/** @file system.h
+* @brief System Driver Header File
+* @date 23.July.2009
+* @version 1.01.001
+*
+* This file contains:
+* - Definitions
+* - Types
+* .
+* which are relevant for the System driver.
+*/
+
+/* (c) Texas Instruments 2009-2010, All rights reserved. */
+
+#ifndef __SYS_SYSTEM_H__
+#define __SYS_SYSTEM_H__
+
+
+/* System General Definitions */
+
+/** @enum systemInterrupt
+* @brief Alias names for clock sources
+*
+* This enumeration is used to provide alias names for the clock sources:
+* - IRQ
+* - FIQ
+*/
+enum systemInterrupt
+{
+ SYS_IRQ, /**< Alias for IRQ interrupt */
+ SYS_FIQ /**< Alias for FIQ interrupt */
+};
+
+/** @enum systemClockSource
+* @brief Alias names for clock sources
+*
+* This enumeration is used to provide alias names for the clock sources:
+* - Oscillator
+* - Pll
+* - 32 kHz Oscillator
+* - External1
+* - Low Power Oscillator Low
+* - Low Power Oscillator High
+* - Flexray Pll
+* - External2
+* - Synchronous VCLK1
+*/
+enum systemClockSource
+{
+ SYS_OSC = 0, /**< Alias for oscillator clock Source */
+ SYS_PLL = 1, /**< Alias for Pll clock Source */
+ SYS_O32 = 2, /**< Alias for 32 kHz oscillator clock Source */
+ SYS_EXTERNAL = 3, /**< Alias for external clock Source */
+ SYS_LPO_LOW = 4, /**< Alias for low power oscillator low clock Source */
+ SYS_LPO_HIGH = 5, /**< Alias for low power oscillator high clock Source */
+ SYS_FR_PLL = 6, /**< Alias for flexray pll clock Source */
+ SYS_EXTERNAL2 = 7, /**< Alias for external 2 clock Source */
+ SYS_VCLK = 9 /**< Alias for synchronous VCLK1 clock Source */
+};
+
+#define SYS_DOZE_MODE 0x000F3F02U
+#define SYS_SNOOZE_MODE 0x000F3F03U
+#define SYS_SLEEP_MODE 0x000FFFFFU
+
+
+/** @def SYS_PRE1
+* @brief Alias name for RTI1CLK PRE clock source
+*
+* This is an alias name for the RTI1CLK pre clock source.
+* This can be either:
+* - Oscillator
+* - Pll
+* - 32 kHz Oscillator
+* - External
+* - Low Power Oscillator Low
+* - Low Power Oscillator High
+* - Flexray Pll
+*/
+#define SYS_PRE1 SYS_PLL
+
+/** @def SYS_PRE2
+* @brief Alias name for RTI2CLK pre clock source
+*
+* This is an alias name for the RTI2CLK pre clock source.
+* This can be either:
+* - Oscillator
+* - Pll
+* - 32 kHz Oscillator
+* - External
+* - Low Power Oscillator Low
+* - Low Power Oscillator High
+* - Flexray Pll
+*/
+#define SYS_PRE2 SYS_PLL
+
+
+/* System Register Frame 1 Definition */
+/** @struct systemBase1
+* @brief System Register Frame 1 Definition
+*
+* This type is used to access the System 1 Registers.
+*/
+/** @typedef systemBASE1_t
+* @brief System Register Frame 1 Type Definition
+*
+* This type is used to access the System 1 Registers.
+*/
+typedef volatile struct systemBase1
+{
+ unsigned SYSPC1; /* 0x0000 */
+ unsigned SYSPC2; /* 0x0004 */
+ unsigned SYSPC3; /* 0x0008 */
+ unsigned SYSPC4; /* 0x000C */
+ unsigned SYSPC5; /* 0x0010 */
+ unsigned SYSPC6; /* 0x0014 */
+ unsigned SYSPC7; /* 0x0018 */
+ unsigned SYSPC8; /* 0x001C */
+ unsigned SYSPC9; /* 0x0020 */
+ unsigned SSWPLL1; /* 0x0024 */
+ unsigned SSWPLL2; /* 0x0028 */
+ unsigned SSWPLL3; /* 0x002C */
+ unsigned CSDIS; /* 0x0030 */
+ unsigned CSDISSET; /* 0x0034 */
+ unsigned CSDISCLR; /* 0x0038 */
+ unsigned CSDDIS; /* 0x003C */
+ unsigned CSDDISSET; /* 0x0040 */
+ unsigned CSDDISCLR; /* 0x0044 */
+ unsigned GHVSRC; /* 0x0048 */
+ unsigned VCLKASRC; /* 0x004C */
+ unsigned RCLKSRC; /* 0x0050 */
+ unsigned CSVSTAT; /* 0x0054 */
+ unsigned MSTGCR; /* 0x0058 */
+ unsigned MINITGCR; /* 0x005C */
+ unsigned MSINENA; /* 0x0060 */
+ unsigned MSTFAIL; /* 0x0064 */
+ unsigned MSTCGSTAT; /* 0x0068 */
+ unsigned MINISTAT; /* 0x006C */
+ unsigned PLLCTL1; /* 0x0070 */
+ unsigned PLLCTL2; /* 0x0074 */
+ unsigned UERFLAG; /* 0x0078 */
+ unsigned DIEIDL; /* 0x007C */
+ unsigned DIEIDH; /* 0x0080 */
+ unsigned VRCTL; /* 0x0084 */
+ unsigned LPOMONCTL; /* 0x0088 */
+ unsigned CLKTEST; /* 0x008C */
+ unsigned DFTCTRLREG1; /* 0x0090 */
+ unsigned DFTCTRLREG2; /* 0x0094 */
+ unsigned : 32U; /* 0x0098 */
+ unsigned : 32U; /* 0x009C */
+ unsigned GPREG1; /* 0x00A0 */
+ unsigned BTRMSEL; /* 0x00A4 */
+ unsigned IMPFASTS; /* 0x00A8 */
+ unsigned IMPFTADD; /* 0x00AC */
+ unsigned SSISR1; /* 0x00B0 */
+ unsigned SSISR2; /* 0x00B4 */
+ unsigned SSISR3; /* 0x00B8 */
+ unsigned SSISR4; /* 0x00BC */
+ unsigned RAMGCR; /* 0x00C0 */
+ unsigned BMMCR1; /* 0x00C4 */
+ unsigned BMMCR2; /* 0x00C8 */
+ unsigned MMUGCR; /* 0x00CC */
+#ifdef __little_endian__
+ unsigned : 8U; /* 0x00D0 */
+ unsigned PENA : 1U; /* 0x00D0 */
+ unsigned : 7U; /* 0x00D0 */
+ unsigned VCLKR : 4U; /* 0x00D0 */
+ unsigned : 4U; /* 0x00D0 */
+ unsigned VCLK2R : 4U; /* 0x00D0 */
+ unsigned : 4U; /* 0x00D0 */
+#else
+ unsigned : 4U; /* 0x00D0 */
+ unsigned VCLK2R : 4U; /* 0x00D0 */
+ unsigned : 4U; /* 0x00D0 */
+ unsigned VCLKR : 4U; /* 0x00D0 */
+ unsigned : 7U; /* 0x00D0 */
+ unsigned PENA : 1U; /* 0x00D0 */
+ unsigned : 8U; /* 0x00D0 */
+#endif
+ unsigned ECPCNTL; /* 0x00D4 */
+ unsigned DSPGCR; /* 0x00D8 */
+ unsigned DEVCR1; /* 0x00DC */
+ unsigned SYSECR; /* 0x00E0 */
+ unsigned SYSESR; /* 0x00E4 */
+ unsigned ITIFLAG; /* 0x00E8 */
+ unsigned GBLSTAT; /* 0x00EC */
+ unsigned DEV; /* 0x00F0 */
+ unsigned SSIVEC; /* 0x00F4 */
+ unsigned SSIF; /* 0x00F8 */
+} systemBASE1_t;
+
+
+/** @def systemREG1
+* @brief System Register Frame 1 Pointer
+*
+* This pointer is used by the system driver to access the system frame 1 registers.
+*/
+#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)
+
+/** @def systemPORT
+* @brief ECLK GIO Port Register Pointer
+*
+* Pointer used by the GIO driver to access I/O PORT of System/Eclk
+* (use the GIO drivers to access the port pins).
+*/
+#define systemPORT ((gioPORT_t *)0xFFFFFF04U)
+
+
+/* System Register Frame 2 Definition */
+/** @struct systemBase2
+* @brief System Register Frame 2 Definition
+*
+* This type is used to access the System 2 Registers.
+*/
+/** @typedef systemBASE2_t
+* @brief System Register Frame 2 Type Definition
+*
+* This type is used to access the System 2 Registers.
+*/
+typedef volatile struct systemBase2
+{
+ unsigned PLLCTL3; /* 0x0000 */
+ unsigned : 32U; /* 0x0004 */
+ unsigned STCCLKDIV; /* 0x0008 */
+ unsigned CLKHB_GLBREG; /* 0x000C */
+ unsigned CLKHB_RTIDREG; /* 0x0010 */
+ unsigned HBCD_STAT; /* 0x0014 */
+ unsigned : 32U; /* 0x0018 */
+ unsigned : 32U; /* 0x001C */
+ unsigned CLKTRMI1; /* 0x0020 */
+ unsigned ECPCNTRL0; /* 0x0024 */
+ unsigned ECPCNTRL1; /* 0x0028 */
+ unsigned ECPCNTRL2; /* 0x002C */
+ unsigned ECPCNTRL3; /* 0x0030 */
+ unsigned : 32U; /* 0x0034 */
+ unsigned : 32U; /* 0x0038 */
+ unsigned CLK2CNTRL; /* 0x003C */
+ unsigned VCLKACON1; /* 0x0040 */
+} systemBASE2_t;
+
+
+/** @def systemREG2
+* @brief System Register Frame 2 Pointer
+*
+* This pointer is used by the system driver to access the system frame 2 registers.
+*/
+#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)
+
+
+/** @struct pcrBase
+* @brief Pcr Register Frame Definition
+*
+* This type is used to access the Pcr Registers.
+*/
+/** @typedef pcrBASE_t
+* @brief PCR Register Frame Type Definition
+*
+* This type is used to access the PCR Registers.
+*/
+typedef volatile struct pcrBase
+{
+ unsigned PMPROTSET0; /* 0x0000 */
+ unsigned PMPROTSET1; /* 0x0004 */
+ unsigned : 32U; /* 0x0008 */
+ unsigned : 32U; /* 0x000C */
+ unsigned PMPROTCLR0; /* 0x0010 */
+ unsigned PMPROTCLR1; /* 0x0014 */
+ unsigned : 32U; /* 0x0018 */
+ unsigned : 32U; /* 0x001C */
+ unsigned PPROTSET0; /* 0x0020 */
+ unsigned PPROTSET1; /* 0x0024 */
+ unsigned PPROTSET2; /* 0x0028 */
+ unsigned PPROTSET3; /* 0x002C */
+ unsigned : 32U; /* 0x0030 */
+ unsigned : 32U; /* 0x0034 */
+ unsigned : 32U; /* 0x0038 */
+ unsigned : 32U; /* 0x003C */
+ unsigned PPROTCLR0; /* 0x0040 */
+ unsigned PPROTCLR1; /* 0x0044 */
+ unsigned PPROTCLR2; /* 0x0048 */
+ unsigned PPROTCLR3; /* 0x004C */
+ unsigned : 32U; /* 0x0050 */
+ unsigned : 32U; /* 0x0054 */
+ unsigned : 32U; /* 0x0058 */
+ unsigned : 32U; /* 0x005C */
+ unsigned PCSPWRDWNSET0; /* 0x0060 */
+ unsigned PCSPWRDWNSET1; /* 0x0064 */
+ unsigned : 32U; /* 0x0068 */
+ unsigned : 32U; /* 0x006C */
+ unsigned PCSPWRDWNCLR0; /* 0x0070 */
+ unsigned PCSPWRDWNCLR1; /* 0x0074 */
+ unsigned : 32U; /* 0x0078 */
+ unsigned : 32U; /* 0x007C */
+ unsigned PSPWRDWNSET0; /* 0x0080 */
+ unsigned PSPWRDWNSET1; /* 0x0084 */
+ unsigned PSPWRDWNSET2; /* 0x0088 */
+ unsigned PSPWRDWNSET3; /* 0x008C */
+ unsigned : 32U; /* 0x0090 */
+ unsigned : 32U; /* 0x0094 */
+ unsigned : 32U; /* 0x0098 */
+ unsigned : 32U; /* 0x009C */
+ unsigned PSPWRDWNCLR0; /* 0x00A0 */
+ unsigned PSPWRDWNCLR1; /* 0x00A4 */
+ unsigned PSPWRDWNCLR2; /* 0x00A8 */
+ unsigned PSPWRDWNCLR3; /* 0x00AC */
+} pcrBASE_t;
+
+/** @def pcrREG
+* @brief Pcr Register Frame Pointer
+*
+* This pointer is used by the system driver to access the Pcr registers.
+*/
+#define pcrREG ((pcrBASE_t *)0xFFFFE000U)
+
+/* FlashW General Definitions */
+
+
+/** @enum flashWPowerModes
+* @brief Alias names for flash bank power modes
+*
+* This enumeration is used to provide alias names for the flash bank power modes:
+* - sleep
+* - standby
+* - active
+*/
+enum flashWPowerModes
+{
+ SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */
+ SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */
+ SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */
+};
+
+
+/** @struct flashWBase
+* @brief Flash Wrapper Register Frame Definition
+*
+* This type is used to access the Flash Wrapper Registers.
+*/
+/** @typedef flashWBASE_t
+* @brief Flash Wrapper Register Frame Type Definition
+*
+* This type is used to access the Flash Wrapper Registers.
+*/
+typedef volatile struct flashWBase
+{
+ unsigned FRDCNTL; /* 0x0000 */
+ unsigned FSPRD; /* 0x0004 */
+ unsigned FEDACCTRL1; /* 0x0008 */
+ unsigned FEDACCTRL2; /* 0x000C */
+ unsigned FCORERRCNT; /* 0x0010 */
+ unsigned FCORERRADD; /* 0x0014 */
+ unsigned FCORERRPOS; /* 0x0018 */
+ unsigned FEDACSTATUS; /* 0x001C */
+ unsigned FUNCERRADD; /* 0x0020 */
+ unsigned FEDACSDIS; /* 0x0024 */
+ unsigned FPRIMADDTAG; /* 0x0028 */
+ unsigned FREDUADDTAG; /* 0x002C */
+ unsigned FBPROT; /* 0x0030 */
+ unsigned FBSE; /* 0x0034 */
+ unsigned FBBUSY; /* 0x0038 */
+ unsigned FBAC; /* 0x003C */
+ unsigned FBFALLBACK; /* 0x0040 */
+ unsigned FBPRDY; /* 0x0044 */
+ unsigned FPAC1; /* 0x0048 */
+ unsigned FPAC2; /* 0x004C */
+ unsigned FMAC; /* 0x0050 */
+ unsigned FMSTAT; /* 0x0054 */
+ unsigned FEMUDMSW; /* 0x0058 */
+ unsigned FEMUDLSW; /* 0x005C */
+ unsigned FEMUECC; /* 0x0060 */
+ unsigned FLOCK; /* 0x0064 */
+ unsigned FEMUADDR; /* 0x0068 */
+ unsigned FDIAGCTRL; /* 0x006C */
+ unsigned FRAWDATAH; /* 0x0070 */
+ unsigned FRAWDATAL; /* 0x0074 */
+ unsigned FRAWECC; /* 0x0078 */
+ unsigned FPAROVR; /* 0x007C */
+ unsigned FVREADCT; /* 0x0080 */
+ unsigned FVHVCT1; /* 0x0084 */
+ unsigned FVHVCT2; /* 0x0088 */
+ unsigned FVNVCT; /* 0x008C */
+ unsigned FVPPCT; /* 0x0090 */
+ unsigned FVWLCT; /* 0x0094 */
+ unsigned FEFUSE; /* 0x0098 */
+ unsigned : 32U; /* 0x009C */
+ unsigned : 32U; /* 0x00A0 */
+ unsigned : 32U; /* 0x00A4 */
+ unsigned : 32U; /* 0x00A8 */
+ unsigned : 32U; /* 0x00AC */
+ unsigned : 32U; /* 0x00B0 */
+ unsigned : 32U; /* 0x00B4 */
+ unsigned : 32U; /* 0x00B8 */
+ unsigned : 32U; /* 0x00BC */
+ unsigned FEDACSDIS2; /* 0x00C0 */
+ unsigned : 32U; /* 0x00C4 */
+ unsigned : 32U; /* 0x00C8 */
+ unsigned : 32U; /* 0x00CC */
+ unsigned : 32U; /* 0x00D0 */
+ unsigned : 32U; /* 0x00D4 */
+ unsigned : 32U; /* 0x00D8 */
+ unsigned : 32U; /* 0x00DC */
+ unsigned : 32U; /* 0x00E0 */
+ unsigned : 32U; /* 0x00E4 */
+ unsigned : 32U; /* 0x00E8 */
+ unsigned : 32U; /* 0x00EC */
+ unsigned : 32U; /* 0x00F0 */
+ unsigned : 32U; /* 0x00F4 */
+ unsigned : 32U; /* 0x00F8 */
+ unsigned : 32U; /* 0x00FC */
+ unsigned FBSTROBES; /* 0x0100 */
+ unsigned FPSTROBES; /* 0x0104 */
+ unsigned FBMODE; /* 0x0108 */
+ unsigned FTCR; /* 0x010C */
+ unsigned FADDR; /* 0x0110 */
+ unsigned FWRITE; /* 0x0114 */
+ unsigned FCBITSEL; /* 0x0118 */
+ unsigned FTCTRL; /* 0x011C */
+ unsigned FWPWRITE0; /* 0x0120 */
+ unsigned FWPWRITE1; /* 0x0124 */
+ unsigned FWPWRITE2; /* 0x0128 */
+ unsigned FWPWRITE3; /* 0x012C */
+ unsigned FWPWRITE4; /* 0x0130 */
+} flashWBASE_t;
+
+/** @def flashWREG
+* @brief Flash Wrapper Register Frame Pointer
+*
+* This pointer is used by the system driver to access the flash wrapper registers.
+*/
+#define flashWREG ((flashWBASE_t *)(0xFFF87000U))
+
+/* System Interface Functions */
+void systemInit(void);
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_types.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_types.h
new file mode 100644
index 000000000..229f0509c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_types.h
@@ -0,0 +1,49 @@
+/*----------------------------------------------------------------------------*/
+/* sys_types.h 10/20/10 15:19:19 */
+/* */
+/* (c) Texas Instruments 2003-2010, All rights reserved. */
+/* */
+
+
+#ifndef __sys_types_h__
+#define __sys_types_h__
+
+/*----------------------------------------------------------------------------*/
+/* Standard Types */
+
+typedef signed char T_S8;
+#define MAX_S8 (127)
+#define MIN_S8 (-128)
+
+typedef unsigned char T_U8;
+#define MAX_U8 (255)
+#define MIN_U8 (0)
+
+typedef signed short T_S16;
+#define MAX_S16 (32767)
+#define MIN_S16 (-32767-1)
+
+typedef unsigned short T_U16;
+#define MAX_U16 (0xFFFFU)
+#define MIN_U16 (0)
+
+typedef signed int T_S32;
+#define MAX_S32 (2147483647L)
+#define MIN_S32 (-2147483647L-1)
+
+typedef unsigned int T_U32;
+#define MAX_U32 (0xFFFFFFFFU)
+#define MIN_U32 (0)
+
+typedef float T_F32;
+#define MAX_F32 (3.39e+38)
+#define MIN_F32 (1.18e-38)
+
+typedef double T_F64;
+#define MAX_F64 (1.79e+308)
+#define MIN_F64 (2.23e-308)
+
+
+#endif
+/*----------------------------------------------------------------------------*/
+
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_vim.h b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_vim.h
new file mode 100644
index 000000000..7ce7e64dd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/startup/sys_vim.h
@@ -0,0 +1,110 @@
+/** @file sys_vim.h
+* @brief Vectored Interrupt Module Header File
+* @date 05.November.2010
+* @version 1.01.000
+*
+* This file contains:
+* - VIM Type Definitions
+* - VIM General Definitions
+* .
+* which are relevant for the Vectored Interrupt Controller.
+*/
+
+/* (c) Texas Instruments 2010, All rights reserved. */
+
+#ifndef __SYS_VIM_H__
+#define __SYS_VIM_H__
+
+
+/* VIM Type Definitions */
+
+/** @typedef t_isrFuncPTR
+* @brief ISR Function Pointer Type Definition
+*
+* This type is used to access the ISR handler.
+*/
+typedef void (*t_isrFuncPTR)();
+
+
+/* VIM General Configuration */
+
+#define VIM_CHANNELS 96U
+
+/* Interrupt Handlers */
+
+extern void phantomInterrupt(void);
+extern void esmHighLevelInterrupt(void);
+
+extern void vPortPreemptiveTick(void);
+extern void vPortNonPreemptiveTick(void);
+extern void vPortYeildWithinAPI(void);
+
+
+/* Vim Register Frame Definition */
+/** @struct vimBase
+* @brief Vim Register Frame Definition
+*
+* This type is used to access the Vim Registers.
+*/
+/** @typedef vimBASE_t
+* @brief VIM Register Frame Type Definition
+*
+* This type is used to access the VIM Registers.
+*/
+typedef volatile struct vimBase
+{
+ unsigned : 24U; /* 0x0000 */
+ unsigned IRQIVEC : 8U; /* 0x0000 */
+ unsigned : 24U; /* 0x0004 */
+ unsigned FIQIVEC : 8U; /* 0x0004 */
+ unsigned : 32U; /* 0x0008 */
+ unsigned : 32U; /* 0x000C */
+ unsigned FIRQPR0; /* 0x0010 */
+ unsigned FIRQPR1; /* 0x0014 */
+ unsigned FIRQPR2; /* 0x0018 */
+ unsigned FIRQPR3; /* 0x001C */
+ unsigned INTREQ0; /* 0x0020 */
+ unsigned INTREQ1; /* 0x0024 */
+ unsigned INTREQ2; /* 0x0028 */
+ unsigned INTREQ3; /* 0x002C */
+ unsigned REQMASKSET0; /* 0x0030 */
+ unsigned REQMASKSET1; /* 0x0034 */
+ unsigned REQMASKSET2; /* 0x0038 */
+ unsigned REQMASKSET3; /* 0x003C */
+ unsigned REQMASKCLR0; /* 0x0040 */
+ unsigned REQMASKCLR1; /* 0x0044 */
+ unsigned REQMASKCLR2; /* 0x0048 */
+ unsigned REQMASKCLR3; /* 0x004C */
+ unsigned WAKEMASKSET0; /* 0x0050 */
+ unsigned WAKEMASKSET1; /* 0x0054 */
+ unsigned WAKEMASKSET2; /* 0x0058 */
+ unsigned WAKEMASKSET3; /* 0x005C */
+ unsigned WAKEMASKCLR0; /* 0x0060 */
+ unsigned WAKEMASKCLR1; /* 0x0064 */
+ unsigned WAKEMASKCLR2; /* 0x0068 */
+ unsigned WAKEMASKCLR3; /* 0x006C */
+ unsigned IRQVECREG; /* 0x0070 */
+ unsigned FIQVECREQ; /* 0x0074 */
+ unsigned : 9U; /* 0x0078 */
+ unsigned CAPEVTSRC1 : 7U; /* 0x0078 */
+ unsigned : 9U; /* 0x0078 */
+ unsigned CAPEVTSRC0 : 7U; /* 0x0078 */
+ unsigned : 32U; /* 0x007C */
+ unsigned char CHANMAP[64U]; /* 0x0080-0x017C */
+} vimBASE_t;
+
+#define vimREG ((vimBASE_t *)0xFFFFFE00U)
+
+/** @typedef vimRAM_t
+* @brief Vim Ram Type Definition
+*
+* This type is used to access the Vim Ram.
+*/
+typedef volatile struct vimRam
+{
+ t_isrFuncPTR ISR[VIM_CHANNELS];
+} vimRAM_t;
+
+#define vimRAM ((vimRAM_t *)0xFFF82000U)
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/sys_link.cmd b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/sys_link.cmd
new file mode 100644
index 000000000..ae4257e54
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R4_RM48_TMS570_CCS5/sys_link.cmd
@@ -0,0 +1,37 @@
+/*----------------------------------------------------------------------------*/
+/* sys_link.cmd */
+/* */
+
+/*----------------------------------------------------------------------------*/
+/* Linker Settings */
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map */
+
+MEMORY
+{
+ VECTORS (X) : origin=0x00000000 length=0x00000020
+ FLASH0 (RX) : origin=0x00000020 length=0x0017FFE0
+ FLASH1 (RX) : origin=0x00180000 length=0x00180000
+ STACKS (RW) : origin=0x08000000 length=0x00000200
+ RAM (RW) : origin=0x08000200 length=0x0003FE00
+ }
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration */
+
+SECTIONS
+{
+ .intvecs : {} > VECTORS
+ .text : {} > FLASH0 | FLASH1
+ .const : {} > FLASH0 | FLASH1
+ .cinit : {} > FLASH0 | FLASH1
+ .pinit : {} > FLASH0 | FLASH1
+ .heap : {} > RAM
+ .bss : {} > RAM
+ .data : {} > RAM
+/* .sysmem : {} > RAM */
+}
+
+/*----------------------------------------------------------------------------*/
+