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Add support for 16 MPU regions to Cortex-M4 MPU ports (#96)

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ARMv7-M supports 8 or 16 MPU regions. FreeRTOS Cortex-M4 MPU ports so
far assumed 8 regions. This change adds support for 16 MPU regions. The
hardware with 16 MPU regions must define configTOTAL_MPU_REGIONS to 16
in their FreeRTOSConfig.h.

If left undefined, it defaults to 8 for backward compatibility.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Gaurav-Aggarwal-AWS 2020-07-24 07:47:41 -07:00 committed by GitHub
parent 367faab135
commit 7dd6b76011
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GPG key ID: 4AEE18F83AFDEB23
7 changed files with 167 additions and 98 deletions
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30
portable/GCC/ARM_CM4_MPU/port.c
View file

@ -69,7 +69,7 @@
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ #define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
#define portMPU_ENABLE ( 0x01UL ) #define portMPU_ENABLE ( 0x01UL )
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@ -360,8 +360,15 @@ static void prvRestoreContextOfFirstTask( void )
" str r3, [r2] \n"/* Disable MPU. */ " str r3, [r2] \n"/* Disable MPU. */
" \n" " \n"
" ldr r2, =0xe000ed9c \n"/* Region Base Address register. */ " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers from TCB. */ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
" stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */ " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
" \n"
#if ( portTOTAL_NUM_REGIONS == 16 )
" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* portTOTAL_NUM_REGIONS == 16. */
" \n" " \n"
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
@ -577,8 +584,15 @@ void xPortPendSVHandler( void )
" str r3, [r2] \n"/* Disable MPU. */ " str r3, [r2] \n"/* Disable MPU. */
" \n" " \n"
" ldr r2, =0xe000ed9c \n"/* Region Base Address register. */ " ldr r2, =0xe000ed9c \n"/* Region Base Address register. */
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers from TCB. */ " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
" stmia r2!, {r4-r11} \n"/* Write 4 sets of MPU registers. */ " stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
" \n"
#if ( portTOTAL_NUM_REGIONS == 16 )
" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
" ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
" stmia r2, {r4-r11} \n" /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* portTOTAL_NUM_REGIONS == 16. */
" \n" " \n"
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */ " ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */ " ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
@ -674,6 +688,12 @@ static void prvSetupMPU( void )
extern uint32_t __privileged_data_end__[]; extern uint32_t __privileged_data_end__[];
#endif /* if defined( __ARMCC_VERSION ) */ #endif /* if defined( __ARMCC_VERSION ) */
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check the expected MPU is present. */ /* Check the expected MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{ {

12
portable/GCC/ARM_CM4_MPU/portmacro.h
View file

@ -81,15 +81,21 @@
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
#endif
#define portUNPRIVILEGED_FLASH_REGION ( 0UL ) #define portUNPRIVILEGED_FLASH_REGION ( 0UL )
#define portPRIVILEGED_FLASH_REGION ( 1UL ) #define portPRIVILEGED_FLASH_REGION ( 1UL )
#define portPRIVILEGED_RAM_REGION ( 2UL ) #define portPRIVILEGED_RAM_REGION ( 2UL )
#define portGENERAL_PERIPHERALS_REGION ( 3UL ) #define portGENERAL_PERIPHERALS_REGION ( 3UL )
#define portSTACK_REGION ( 4UL ) #define portSTACK_REGION ( 4UL )
#define portFIRST_CONFIGURABLE_REGION ( 5UL ) #define portFIRST_CONFIGURABLE_REGION ( 5UL )
#define portLAST_CONFIGURABLE_REGION ( 7UL ) #define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) #define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ #define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" ) #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )

8
portable/IAR/ARM_CM4F_MPU/port.c
View file

@ -76,7 +76,7 @@
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ #define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
#define portMPU_ENABLE ( 0x01UL ) #define portMPU_ENABLE ( 0x01UL )
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@ -527,6 +527,12 @@ static void prvSetupMPU( void )
extern uint32_t __privileged_data_start__[]; extern uint32_t __privileged_data_start__[];
extern uint32_t __privileged_data_end__[]; extern uint32_t __privileged_data_end__[];
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check the expected MPU is present. */ /* Check the expected MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{ {

38
portable/IAR/ARM_CM4F_MPU/portasm.s
View file

@ -91,10 +91,23 @@ xPortPendSVHandler:
/* Region Base Address register. */ /* Region Base Address register. */
ldr r2, =0xe000ed9c ldr r2, =0xe000ed9c
/* Read 4 sets of MPU registers. */ /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
ldmia r1!, {r4-r11} ldmia r1!, {r4-r11}
/* Write 4 sets of MPU registers. */ /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
stmia r2!, {r4-r11} stmia r2, {r4-r11}
#ifdef configTOTAL_MPU_REGIONS
#if ( configTOTAL_MPU_REGIONS == 16 )
/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
ldmia r1!, {r4-r11}
/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
stmia r2, {r4-r11}
/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
ldmia r1!, {r4-r11}
/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
stmia r2, {r4-r11}
#endif /* configTOTAL_MPU_REGIONS == 16. */
#endif /* configTOTAL_MPU_REGIONS */
ldr r2, =0xe000ed94 /* MPU_CTRL register. */ ldr r2, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [r2] /* Read the value of MPU_CTRL. */ ldr r3, [r2] /* Read the value of MPU_CTRL. */
@ -178,10 +191,23 @@ vPortRestoreContextOfFirstTask:
/* Region Base Address register. */ /* Region Base Address register. */
ldr r2, =0xe000ed9c ldr r2, =0xe000ed9c
/* Read 4 sets of MPU registers. */ /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
ldmia r1!, {r4-r11} ldmia r1!, {r4-r11}
/* Write 4 sets of MPU registers. */ /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
stmia r2!, {r4-r11} stmia r2, {r4-r11}
#ifdef configTOTAL_MPU_REGIONS
#if ( configTOTAL_MPU_REGIONS == 16 )
/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
ldmia r1!, {r4-r11}
/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
stmia r2, {r4-r11}
/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
ldmia r1!, {r4-r11}
/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
stmia r2, {r4-r11}
#endif /* configTOTAL_MPU_REGIONS == 16. */
#endif /* configTOTAL_MPU_REGIONS */
ldr r2, =0xe000ed94 /* MPU_CTRL register. */ ldr r2, =0xe000ed94 /* MPU_CTRL register. */
ldr r3, [r2] /* Read the value of MPU_CTRL. */ ldr r3, [r2] /* Read the value of MPU_CTRL. */

12
portable/IAR/ARM_CM4F_MPU/portmacro.h
View file

@ -84,15 +84,21 @@
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
#endif
#define portUNPRIVILEGED_FLASH_REGION ( 0UL ) #define portUNPRIVILEGED_FLASH_REGION ( 0UL )
#define portPRIVILEGED_FLASH_REGION ( 1UL ) #define portPRIVILEGED_FLASH_REGION ( 1UL )
#define portPRIVILEGED_RAM_REGION ( 2UL ) #define portPRIVILEGED_RAM_REGION ( 2UL )
#define portGENERAL_PERIPHERALS_REGION ( 3UL ) #define portGENERAL_PERIPHERALS_REGION ( 3UL )
#define portSTACK_REGION ( 4UL ) #define portSTACK_REGION ( 4UL )
#define portFIRST_CONFIGURABLE_REGION ( 5UL ) #define portFIRST_CONFIGURABLE_REGION ( 5UL )
#define portLAST_CONFIGURABLE_REGION ( 7UL ) #define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) #define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ #define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1UL )
#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" ) #define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )

153
portable/RVDS/ARM_CM4_MPU/port.c
View file

@ -58,7 +58,7 @@
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) ) #define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) ) #define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) ) #define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
#define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */ #define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
#define portMPU_ENABLE ( 0x01UL ) #define portMPU_ENABLE ( 0x01UL )
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL ) #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL ) #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@ -310,7 +310,7 @@ __asm void vPortSVCHandler( void )
{ {
extern prvSVCHandler extern prvSVCHandler
PRESERVE8 PRESERVE8
/* Assumes psp was in use. */ /* Assumes psp was in use. */
#ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */ #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
@ -321,6 +321,7 @@ __asm void vPortSVCHandler( void )
#else #else
mrs r0, psp mrs r0, psp
#endif #endif
b prvSVCHandler b prvSVCHandler
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -329,44 +330,45 @@ __asm void prvRestoreContextOfFirstTask( void )
{ {
PRESERVE8 PRESERVE8
ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */ ldr r0, = 0xE000ED08 /* Use the NVIC offset register to locate the stack. */
ldr r0, [ r0 ]
ldr r0, [ r0 ] ldr r0, [ r0 ]
msr msp, r0 /* Set the msp back to the start of the stack. */ ldr r0, [ r0 ]
ldr r3, = pxCurrentTCB /* Restore the context. */ msr msp, r0 /* Set the msp back to the start of the stack. */
ldr r1, [ r3 ] ldr r3, = pxCurrentTCB /* Restore the context. */
ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */ ldr r1, [ r3 ]
add r1, r1, # 4 /* Move onto the second item in the TCB... */ ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
add r1, r1, # 4 /* Move onto the second item in the TCB... */
dmb /* Complete outstanding transfers before disabling MPU. */ dmb /* Complete outstanding transfers before disabling MPU. */
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
str r3, [ r2 ] /* Disable MPU. */ str r3, [ r2 ] /* Disable MPU. */
ldr r2, = 0xe000ed9c /* Region Base Address register. */ ldr r2, = 0xe000ed9c /* Region Base Address register. */
ldmia r1 !, { ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
r4 - r11 stmia r2, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
} /* Read 4 sets of MPU registers. */
stmia r2 !, {
r4 - r11
} /* Write 4 sets of MPU registers. */
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ #if ( portTOTAL_NUM_REGIONS == 16 )
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
str r3, [ r2 ] /* Enable MPU. */ ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
dsb /* Force memory writes before continuing. */ stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* portTOTAL_NUM_REGIONS == 16. */
ldmia r0 !, { ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
r3 - r11, r14 ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
} /* Pop the registers that are not automatically saved on exception entry. */ orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
str r3, [ r2 ] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
msr control, r3 msr control, r3
msr psp, r0 /* Restore the task stack pointer. */ msr psp, r0 /* Restore the task stack pointer. */
mov r0, # 0 mov r0, # 0
msr basepri, r0 msr basepri, r0
bx r14 bx r14
nop nop
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -478,7 +480,7 @@ __asm void prvStartFirstTask( void )
/* Use the NVIC offset register to locate the stack. */ /* Use the NVIC offset register to locate the stack. */
ldr r0, = 0xE000ED08 ldr r0, = 0xE000ED08
ldr r0, [ r0 ] ldr r0, [ r0 ]
ldr r0, [ r0 ] ldr r0, [ r0 ]
/* Set the msp back to the start of the stack. */ /* Set the msp back to the start of the stack. */
msr msp, r0 msr msp, r0
@ -496,7 +498,7 @@ __asm void prvStartFirstTask( void )
isb isb
svc portSVC_START_SCHEDULER /* System call to start first task. */ svc portSVC_START_SCHEDULER /* System call to start first task. */
nop nop
nop nop
} }
void vPortEndScheduler( void ) void vPortEndScheduler( void )
@ -544,24 +546,18 @@ __asm void xPortPendSVHandler( void )
mrs r0, psp mrs r0, psp
ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */ ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
ldr r2, [ r3 ] ldr r2, [ r3 ]
tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */ tst r14, # 0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
it eq it eq
vstmdbeq r0 !, { vstmdbeq r0!, {s16-s31}
s16 - s31
}
mrs r1, control mrs r1, control
stmdb r0 !, { stmdb r0!, {r1, r4-r11, r14} /* Save the remaining registers. */
r1, r4 - r11, r14 str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
} /* Save the remaining registers. */
str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
stmdb sp !, { stmdb sp!, {r0, r3}
r0, r3
}
mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0 msr basepri, r0
dsb dsb
@ -569,48 +565,45 @@ __asm void xPortPendSVHandler( void )
bl vTaskSwitchContext bl vTaskSwitchContext
mov r0, # 0 mov r0, # 0
msr basepri, r0 msr basepri, r0
ldmia sp !, { ldmia sp!, {r0, r3}
r0, r3
}
/* Restore the context. */ /* Restore the context. */
ldr r1, [ r3 ] ldr r1, [ r3 ]
ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */ ldr r0, [ r1 ] /* The first item in the TCB is the task top of stack. */
add r1, r1, # 4 /* Move onto the second item in the TCB... */ add r1, r1, # 4 /* Move onto the second item in the TCB... */
dmb /* Complete outstanding transfers before disabling MPU. */ dmb /* Complete outstanding transfers before disabling MPU. */
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */ bic r3, r3, # 1 /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
str r3, [ r2 ] /* Disable MPU. */ str r3, [ r2 ] /* Disable MPU. */
ldr r2, = 0xe000ed9c /* Region Base Address register. */ ldr r2, = 0xe000ed9c /* Region Base Address register. */
ldmia r1 !, { ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
r4 - r11 stmia r2, {r4-r11} /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
} /* Read 4 sets of MPU registers. */
stmia r2 !, {
r4 - r11
} /* Write 4 sets of MPU registers. */
ldr r2, = 0xe000ed94 /* MPU_CTRL register. */ #if ( portTOTAL_NUM_REGIONS == 16 )
ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */ ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
orr r3, r3, # 1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */ stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
str r3, [ r2 ] /* Enable MPU. */ ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
dsb /* Force memory writes before continuing. */ stmia r2, {r4-r11} /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
#endif /* portTOTAL_NUM_REGIONS == 16. */
ldmia r0 !, { ldr r2, = 0xe000ed94 /* MPU_CTRL register. */
r3 - r11, r14 ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
} /* Pop the registers that are not automatically saved on exception entry. */ orr r3, r3, #1 /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
str r3, [ r2 ] /* Enable MPU. */
dsb /* Force memory writes before continuing. */
ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
msr control, r3 msr control, r3
tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */ tst r14, # 0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
it eq it eq
vldmiaeq r0 !, { vldmiaeq r0!, {s16-s31}
s16 - s31
}
msr psp, r0 msr psp, r0
bx r14 bx r14
nop nop
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -663,7 +656,7 @@ __asm void vPortEnableVFP( void )
PRESERVE8 PRESERVE8
ldr.w r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */ ldr.w r0, = 0xE000ED88 /* The FPU enable bits are in the CPACR. */
ldr r1, [ r0 ] ldr r1, [ r0 ]
orr r1, r1, # ( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */ orr r1, r1, # ( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
str r1, [ r0 ] str r1, [ r0 ]
@ -682,6 +675,12 @@ static void prvSetupMPU( void )
extern uint32_t __privileged_data_start__; extern uint32_t __privileged_data_start__;
extern uint32_t __privileged_data_end__; extern uint32_t __privileged_data_end__;
/* The only permitted number of regions are 8 or 16. */
configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
/* Check the expected MPU is present. */ /* Check the expected MPU is present. */
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE ) if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
{ {

12
portable/RVDS/ARM_CM4_MPU/portmacro.h
View file

@ -81,15 +81,21 @@
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL ) #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL ) #define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
/* MPU settings that can be overriden in FreeRTOSConfig.h. */
#ifndef configTOTAL_MPU_REGIONS
/* Define to 8 for backward compatibility. */
#define configTOTAL_MPU_REGIONS ( 8UL )
#endif
#define portUNPRIVILEGED_FLASH_REGION ( 0UL ) #define portUNPRIVILEGED_FLASH_REGION ( 0UL )
#define portPRIVILEGED_FLASH_REGION ( 1UL ) #define portPRIVILEGED_FLASH_REGION ( 1UL )
#define portPRIVILEGED_RAM_REGION ( 2UL ) #define portPRIVILEGED_RAM_REGION ( 2UL )
#define portGENERAL_PERIPHERALS_REGION ( 3UL ) #define portGENERAL_PERIPHERALS_REGION ( 3UL )
#define portSTACK_REGION ( 4UL ) #define portSTACK_REGION ( 4UL )
#define portFIRST_CONFIGURABLE_REGION ( 5UL ) #define portFIRST_CONFIGURABLE_REGION ( 5UL )
#define portLAST_CONFIGURABLE_REGION ( 7UL ) #define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 ) #define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */ #define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
void vPortSwitchToUserMode( void ); void vPortSwitchToUserMode( void );
#define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode() #define portSWITCH_TO_USER_MODE() vPortSwitchToUserMode()