mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
FreeRTOS source:
+ Previously, if a task was deleted, the memory allocated to the task by the RTOS was freed in the Idle task. Now if a task deletes another task the memory is freed immediately. The idle task is however still responsible for freeing the memory when a task deletes itself. + Added pcQueueGetQueueName() function to return the name of a queue from its handle, assuming the queue is registers. Demo application: + Update GenQTest to exercise the new pcQueueGetQueueName() function. + Delete workspaces from old Eclipse examples, leaving just the projects. + Rework comments in the MSVC simply blinky demo.
This commit is contained in:
Richard Barry
parent
94dd3f871b
commit
7d6609f8db
347 changed files with 256 additions and 25411 deletions
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<?xml version="1.0" encoding="UTF-8"?>
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#Tue Aug 05 14:13:37 BST 2008
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eclipse.preferences.version=1
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environment/workspace=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<environment append\="true" appendContributed\="true"/>\r\n
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#Tue Aug 05 11:49:38 BST 2008
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eclipse.preferences.version=1
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indexer/preferenceScope=0
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#Tue Aug 05 11:54:06 BST 2008
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org.eclipse.cdt.debug.core.cDebug.common_source_containers=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<sourceLookupDirector>\r\n<sourceContainers duplicates\="false"/>\r\n</sourceLookupDirector>\r\n
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eclipse.preferences.version=1
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#Fri Aug 08 13:44:18 BST 2008
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org.eclipse.debug.ui.DebugView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true
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columnOrderKeyEXE=0,1,2,3,4,5
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visibleColumnsKeySF=1,1,0,0,0,0
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org.eclipse.debug.ui.BreakpointView.org.eclipse.cdt.debug.ui.cDebug.show_full_paths=true
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visibleColumnsKeyEXE=1,1,1,0,0,0
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columnSortDirectionKeyEXE=128
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eclipse.preferences.version=1
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columnOrderKeySF=0,1,2,3,4,5
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columnSortDirectionKeySF=128
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#Thu Aug 14 13:44:43 BST 2008
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eclipse.preferences.version=1
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properties/RTOSDemo.null.38326818/0.1348192838=\#\r\n\#Thu Aug 14 13\:44\:43 BST 2008\r\norg.eclipse.cdt.build.core.settings.holder.1053974197\=\\\#\\r\\n\\\#Thu Aug 14 13\\\:44\\\:43 BST 2008\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.804763436\=\\\#\\r\\n\\\#Thu Aug 14 13\\\:44\\\:43 BST 2008\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.libs.1997217404\=\\\#\\r\\n\\\#Thu Aug 14 13\\\:44\\\:43 BST 2008\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.99587291\=\\\#\\r\\n\\\#Thu Aug 14 13\\\:44\\\:43 BST 2008\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.prefbase.toolchain.1423010524\=\\\#\\r\\n\\\#Thu Aug 14 13\\\:44\\\:43 BST 2008\\r\\nrebuildState\\\=false\\r\\n\r\n0.1348192838\=\\\#\\r\\n\\\#Thu Aug 14 13\\\:44\\\:43 BST 2008\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\n
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#Tue Aug 05 17:26:23 BST 2008
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org.eclipse.mylyn.ui.first.run.0_4_9=false
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eclipse.preferences.version=1
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#Tue Aug 05 14:13:37 BST 2008
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useQuickDiffPrefPage=true
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closeBrackets=false
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useAnnotationsPrefPage=true
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spelling_locale=en_GB
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sourceHoverBackgroundColor=255,255,225
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org.eclipse.cdt.ui.text.custom_code_templates=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?><templates/>
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closeAngularBrackets=false
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spelling_locale_initialized=true
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eclipse.preferences.version=1
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org.eclipse.cdt.ui.text.templates.custom=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?><templates/>
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content_assist_disabled_computers=org.eclipse.cdt.ui.cdtNoTypeProposalCategory\u0000org.eclipse.cdt.ui.cdtTypeProposalCategory\u0000org.eclipse.cdt.ui.textProposalCategory\u0000org.eclipse.cdt.ui.templateProposalCategory\u0000
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version=1
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pathvariable.FREERTOS_ROOT=C\:/E/Dev/FreeRTOS/WorkingCopy2
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prefWatchExpressions=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<watchExpressions/>\r\n
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org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<launchPerspectives/>\r\n
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pref_state_memento.org.eclipse.debug.ui.VariableView=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<VariablesViewMemento org.eclipse.debug.ui.SASH_DETAILS_PART\="315" org.eclipse.debug.ui.SASH_VIEW_PART\="684">\r\n<PRESENTATION_CONTEXT_PROPERTIES IMemento.internal.id\="org.eclipse.debug.ui.VariableView"/>\r\n</VariablesViewMemento>
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pref_state_memento.org.eclipse.debug.ui.RegisterView=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<VariablesViewMemento org.eclipse.debug.ui.SASH_DETAILS_PART\="136" org.eclipse.debug.ui.SASH_VIEW_PART\="863">\r\n<COLUMN_SIZES IMemento.internal.id\="org.eclipse.debug.ui.VARIALBE_COLUMN_PRESENTATION.COL_VAR_NAME" SIZE\="130"/>\r\n<COLUMN_SIZES IMemento.internal.id\="org.eclipse.debug.ui.VARIALBE_COLUMN_PRESENTATION.COL_VAR_VALUE" SIZE\="414"/>\r\n<PRESENTATION_CONTEXT_PROPERTIES IMemento.internal.id\="org.eclipse.debug.ui.RegisterView"/>\r\n</VariablesViewMemento>
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org.eclipse.debug.ui.memory.columnSize\:org.eclipse.cdt.debug.core=4
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pref_state_memento.org.eclipse.debug.ui.ExpressionView=<?xml version\="1.0" encoding\="UTF-8"?>\r\n<VariablesViewMemento org.eclipse.debug.ui.SASH_DETAILS_PART\="315" org.eclipse.debug.ui.SASH_VIEW_PART\="684"/>
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preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane|
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org.eclipse.debug.ui.switch_perspective_on_suspend=always
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org.eclipse.debug.ui.memory.rowSize\:org.eclipse.cdt.debug.core=16
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org.eclipse.debug.ui.user_view_bindings=<?xml version\="1.0" encoding\="UTF-8" standalone\="no"?>\r\n<viewBindings>\r\n<view id\="org.eclipse.debug.ui.MemoryView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="closed"/>\r\n</view>\r\n<view id\="org.eclipse.debug.ui.RegisterView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="closed"/>\r\n</view>\r\n<view id\="org.eclipse.debug.ui.DebugView">\r\n<perspective id\="org.eclipse.cdt.ui.CPerspective" userAction\="closed"/>\r\n</view>\r\n<view id\="org.eclipse.debug.ui.ExpressionView">\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="opened"/>\r\n<perspective id\="org.eclipse.cdt.ui.CPerspective" userAction\="closed"/>\r\n</view>\r\n<view id\="org.eclipse.ui.console.ConsoleView">\r\n<perspective id\="org.eclipse.cdt.ui.CPerspective" userAction\="opened"/>\r\n<perspective id\="org.eclipse.debug.ui.DebugPerspective" userAction\="opened"/>\r\n</view>\r\n</viewBindings>\r\n
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autoUpdateInit=true
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#Mon Aug 11 13:09:15 BST 2008
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org.eclipse.debug.ui.VariableView.org.eclipse.jdt.debug.ui.show_null_entries=true
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eclipse.preferences.version=1
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org.eclipse.debug.ui.ExpressionView.org.eclipse.jdt.debug.ui.show_null_entries=true
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#Tue Aug 05 13:17:49 BST 2008
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useQuickDiffPrefPage=true
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proposalOrderMigrated=true
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tabWidthPropagated=true
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content_assist_proposals_background=255,255,255
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org.eclipse.jdt.ui.javadoclocations.migrated=true
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useAnnotationsPrefPage=true
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spelling_locale=en_GB
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org.eclipse.jdt.internal.ui.navigator.layout=2
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org.eclipse.jface.textfont=1|Courier New|10.0|0|WINDOWS|1|0|0|0|0|0|0|0|0|1|0|0|0|0|Courier New;
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org.eclipse.jdt.ui.editor.tab.width=
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org.eclipse.jdt.ui.formatterprofiles.version=11
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content_assist_number_of_computers=9
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spelling_locale_initialized=true
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eclipse.preferences.version=1
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content_assist_proposals_foreground=0,0,0
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fontPropagated=true
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#Tue Aug 05 11:47:26 BST 2008
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eclipse.preferences.version=1
|
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mylyn.attention.migrated=true
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|
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#Mon Aug 11 07:30:25 BST 2008
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org.eclipse.search.defaultPerspective=org.eclipse.search.defaultPerspective.none
|
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eclipse.preferences.version=1
|
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#Fri Aug 08 13:44:18 BST 2008
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eclipse.preferences.version=1
|
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org.eclipse.team.ui.first_time=false
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#Thu Aug 14 11:07:33 BST 2008
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eclipse.preferences.version=1
|
||||
internalWebBrowserHistory=http\://www.eclipse.org/|*|http\://www.eclipse.org|*|C\:\\E\\Dev\\FreeRTOS\\DOC\\CurrentWebSite\\banners\\ColdFire-RTOS-Port-Using-Eclipse.html|*|file\:/C\:/E/Dev/FreeRTOS/DOC/CurrentWebSite/banners/ColdFire-RTOS-Port-Using-Eclipse.html|*|
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
#Tue Aug 05 11:56:04 BST 2008
|
||||
eclipse.preferences.version=1
|
||||
overviewRuler_migration=migrated_3.1
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
#Thu Aug 14 14:16:27 BST 2008
|
||||
eclipse.preferences.version=1
|
||||
TASKS_FILTERS_MIGRATE=true
|
||||
tipsAndTricks=true
|
||||
platformState=1218719749090
|
||||
PROBLEMS_FILTERS_MIGRATE=true
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
#Tue Aug 12 16:13:20 BST 2008
|
||||
eclipse.preferences.version=1
|
||||
showIntro=false
|
||||
KEY_CONFIGURATION_ID=org.eclipse.cdt.ui.visualstudio
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -1,28 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbremote.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbremote.core.initCommands" value="target remote | m68k-elf-sprite pe: m5282evb"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbremote.core.ipAddress" value="localhost"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbremote.core.loadImage" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbremote.core.portNumber" value="10000"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbremote.core.runCommands" value="load b main continue delete main "/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbremote.core.useRemoteTarget" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="m68k-elf-gdb"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.GDB_INIT" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="ps-(format)" val="4"/><content id="d7-(format)" val="4"/><content id="d4-(format)" val="4"/><content id="d1-(format)" val="4"/><content id="d0-(format)" val="4"/><content id="us-main-(format)" val="4"/></contentList>"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="bin/RTOSDemo.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RTOSDemo"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.1348192838"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/RTOSDemo"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
</launchConfiguration>
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<section name="org.eclipse.debug.ui.LAUNCH_CONFIGURATIONS_DIALOG_SECTION">
|
||||
<item value="952" key="DIALOG_WIDTH"/>
|
||||
<item value="89" key="DIALOG_Y_ORIGIN"/>
|
||||
<item value=", org.eclipse.cdt.debug.gdbjtag.launchConfigurationType, " key="org.eclipse.debug.ui.EXPANDED_NODES"/>
|
||||
<item value="640" key="DIALOG_HEIGHT"/>
|
||||
<item value="444" key="DIALOG_X_ORIGIN"/>
|
||||
<item value="237" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_1"/>
|
||||
<item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>
|
||||
<item value="762" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_2"/>
|
||||
</section>
|
||||
</section>
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchHistory>
|
||||
<launchGroup id="org.eclipse.ui.externaltools.launchGroup">
|
||||
<mruHistory/>
|
||||
<favorites/>
|
||||
</launchGroup>
|
||||
<launchGroup id="org.eclipse.debug.ui.launchGroup.profile">
|
||||
<mruHistory/>
|
||||
<favorites/>
|
||||
</launchGroup>
|
||||
<launchGroup id="org.eclipse.debug.ui.launchGroup.debug">
|
||||
<mruHistory>
|
||||
<launch memento="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <launchConfiguration local="true" path="RTOSDemo.launch"/> "/>
|
||||
</mruHistory>
|
||||
<favorites/>
|
||||
</launchGroup>
|
||||
<launchGroup id="org.eclipse.debug.ui.launchGroup.run">
|
||||
<mruHistory/>
|
||||
<favorites/>
|
||||
</launchGroup>
|
||||
</launchHistory>
|
||||
Binary file not shown.
|
|
@ -1,2 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<typeInfoHistroy/>
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<qualifiedTypeNameHistroy/>
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<section name="org.eclipse.jdt.internal.ui.packageview.PackageExplorerPart">
|
||||
<item value="true" key="group_libraries"/>
|
||||
<item value="false" key="linkWithEditor"/>
|
||||
<item value="2" key="layout"/>
|
||||
<item value="1" key="rootMode"/>
|
||||
<item value="<?xml version="1.0" encoding="UTF-8"?>
<packageExplorer group_libraries="1" isWindowWorkingSet="true" layout="2" linkWithEditor="0" rootMode="1" workingSetName="">
<customFilters userDefinedPatternsEnabled="false">
<xmlDefinedFilters>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.LibraryFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.LocalTypesFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.StaticsFilter" isEnabled="false"/>
<child filterId="org.eclipse.pde.ui.ExternalPluginLibrariesFilter1" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.ClosedProjectsFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.NonSharedProjectsFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.NonJavaElementFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.ContainedLibraryFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.CuAndClassFileFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.NonJavaProjectsFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.internal.ui.PackageExplorer.EmptyInnerPackageFilter" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.PackageDeclarationFilter" isEnabled="true"/>
<child filterId="org.eclipse.jdt.internal.ui.PackageExplorer.EmptyPackageFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.ImportDeclarationFilter" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.FieldsFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.internal.ui.PackageExplorer.HideInnerClassFilesFilter" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.NonPublicFilter" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer_patternFilterId_.*" isEnabled="true"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.EmptyLibraryContainerFilter" isEnabled="true"/>
<child filterId="org.eclipse.pde.ui.BinaryProjectFilter1" isEnabled="false"/>
<child filterId="org.eclipse.jdt.ui.PackageExplorer.SyntheticMembersFilter" isEnabled="true"/>
</xmlDefinedFilters>
</customFilters>
</packageExplorer>" key="memento"/>
|
||||
</section>
|
||||
<section name="JavaElementSearchActions">
|
||||
</section>
|
||||
</section>
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
</section>
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
#Cached timestamps
|
||||
#Tue Aug 05 11:56:05 BST 2008
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<section name="DialogBounds_SearchDialog">
|
||||
<item value="519" key="DIALOG_WIDTH"/>
|
||||
<item value="259" key="DIALOG_Y_ORIGIN"/>
|
||||
<item value="385" key="DIALOG_HEIGHT"/>
|
||||
<item value="445" key="DIALOG_X_ORIGIN"/>
|
||||
<item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>
|
||||
</section>
|
||||
<section name="Search">
|
||||
<list key="Search.processedPageIds">
|
||||
<item value="org.eclipse.search.internal.ui.text.TextSearchPage"/>
|
||||
<item value="org.eclipse.mylyn.tasks.ui.search.page"/>
|
||||
<item value="org.eclipse.cdt.ui.pdomSearchPage"/>
|
||||
<item value="org.eclipse.jdt.ui.JavaSearchPage"/>
|
||||
<item value="org.eclipse.pde.internal.ui.search.SearchPage"/>
|
||||
</list>
|
||||
<list key="Search.enabledPageIds">
|
||||
<item value="org.eclipse.search.internal.ui.text.TextSearchPage"/>
|
||||
<item value="org.eclipse.mylyn.tasks.ui.search.page"/>
|
||||
<item value="org.eclipse.cdt.ui.pdomSearchPage"/>
|
||||
<item value="org.eclipse.jdt.ui.JavaSearchPage"/>
|
||||
<item value="org.eclipse.pde.internal.ui.search.SearchPage"/>
|
||||
</list>
|
||||
</section>
|
||||
<section name="org.eclipse.cdt.ui.pdomSearchViewPage">
|
||||
</section>
|
||||
<section name="SearchDialog.ScopePart">
|
||||
<item value="0" key="scope"/>
|
||||
</section>
|
||||
</section>
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<section name="SaveAsDialogSettings">
|
||||
<item value="438" key="DIALOG_WIDTH"/>
|
||||
<item value="147" key="DIALOG_Y_ORIGIN"/>
|
||||
<item value="625" key="DIALOG_X_ORIGIN"/>
|
||||
<item value="553" key="DIALOG_HEIGHT"/>
|
||||
<item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>
|
||||
</section>
|
||||
<section name="NewWizardAction">
|
||||
<item value="org.eclipse.cdt.ui.wizards.NewCWizard2" key="NewWizardSelectionPage.STORE_SELECTED_ID"/>
|
||||
<list key="NewWizardSelectionPage.STORE_EXPANDED_CATEGORIES_ID">
|
||||
<item value="org.eclipse.cdt.ui.newCWizards"/>
|
||||
</list>
|
||||
</section>
|
||||
<section name="CleanDialogSettings">
|
||||
<item value="411" key="DIALOG_WIDTH"/>
|
||||
<item value="false" key="BUILD_NOW"/>
|
||||
<item value="275" key="DIALOG_Y_ORIGIN"/>
|
||||
<item value="true" key="BUILD_ALL"/>
|
||||
<item value="635" key="DIALOG_X_ORIGIN"/>
|
||||
<item value="417" key="DIALOG_HEIGHT"/>
|
||||
<item value="false" key="TOGGLE_SELECTED"/>
|
||||
</section>
|
||||
</section>
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<item value="1024" key="introLaunchBar.location"/>
|
||||
</section>
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<section name="org.eclipse.ui.texteditor.FindReplaceDialog_dialogBounds">
|
||||
<item value="237" key="DIALOG_WIDTH"/>
|
||||
<item value="212" key="DIALOG_Y_ORIGIN"/>
|
||||
<item value="1167" key="DIALOG_X_ORIGIN"/>
|
||||
<item value="356" key="DIALOG_HEIGHT"/>
|
||||
<item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>
|
||||
</section>
|
||||
<section name="org.eclipse.ui.texteditor.FindReplaceDialog">
|
||||
<item value="true" key="wrap"/>
|
||||
<item value="false" key="casesensitive"/>
|
||||
<item value="false" key="isRegEx"/>
|
||||
<item value="false" key="incremental"/>
|
||||
<item value="false" key="wholeword"/>
|
||||
<item value="xTaskCreate" key="selection"/>
|
||||
<list key="findhistory">
|
||||
<item value="xTaskCreate"/>
|
||||
<item value="prvQueueAccessLogError"/>
|
||||
<item value="criticalnest"/>
|
||||
<item value="0x200075ec"/>
|
||||
<item value="0x200075e8"/>
|
||||
<item value="ulPrevPendedValue"/>
|
||||
<item value=""nop""/>
|
||||
<item value="uxTopReadyPriority"/>
|
||||
</list>
|
||||
<list key="replacehistory">
|
||||
<item value="0x20007fdc"/>
|
||||
<item value="0x200075ec"/>
|
||||
<item value="0x01"/>
|
||||
<item value="mainERROR_PERIOD"/>
|
||||
<item value="french_cheese"/>
|
||||
<item value="taskEXIT_CRITICAL"/>
|
||||
<item value="taskENTER_CRITICAL"/>
|
||||
<item value="COMMON_DEMO_CODE_DIR"/>
|
||||
</list>
|
||||
</section>
|
||||
</section>
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<section name="FileSystemImportWizard">
|
||||
<item value="false" key="WizardFileSystemResourceImportPage1.STORE_OVERWRITE_EXISTING_RESOURCES_ID"/>
|
||||
<item value="false" key="WizardFileSystemResourceImportPage1.STORE_CREATE_CONTAINER_STRUCTURE_ID"/>
|
||||
<list key="WizardFileSystemResourceImportPage1.STORE_SOURCE_NAMES_ID">
|
||||
<item value="C:\Temp\RTOSDemo"/>
|
||||
</list>
|
||||
</section>
|
||||
<section name="WorkbenchPreferenceDialogSettings">
|
||||
<item value="157" key="DIALOG_Y_ORIGIN"/>
|
||||
<item value="258" key="DIALOG_X_ORIGIN"/>
|
||||
</section>
|
||||
<section name="ShowViewDialog">
|
||||
<item value="280" key="DIALOG_WIDTH"/>
|
||||
<item value="rtos.openrtos.viewer.views.TaskTable" key="ShowViewDialog.STORE_SELECTED_VIEW_ID"/>
|
||||
<item value="239" key="DIALOG_Y_ORIGIN"/>
|
||||
<item value="704" key="DIALOG_X_ORIGIN"/>
|
||||
<item value="415" key="DIALOG_HEIGHT"/>
|
||||
<item value="1|Tahoma|8.25|0|WINDOWS|1|-11|0|0|0|400|0|0|0|1|0|0|0|0|Tahoma" key="DIALOG_FONT_NAME"/>
|
||||
<list key="ShowViewDialog.STORE_EXPANDED_CATEGORIES_ID">
|
||||
<item value="rtos.openrtos.viewer"/>
|
||||
</list>
|
||||
</section>
|
||||
<section name="org.eclipse.ui.preferences.keysPreferencePage">
|
||||
<item value="true" key="uncategorizedFilter"/>
|
||||
<item value="true" key="internalFilter"/>
|
||||
<item value="true" key="actionSetFilter"/>
|
||||
</section>
|
||||
<section name="ImportExportAction">
|
||||
<item value="org.eclipse.ui.wizards.import.FileSystem" key="ImportExportPage.STORE_SELECTED_IMPORT_WIZARD_ID"/>
|
||||
<list key="ImportExportPage.STORE_EXPANDED_IMPORT_CATEGORIES">
|
||||
<item value="org.eclipse.ui.Basic"/>
|
||||
</list>
|
||||
</section>
|
||||
</section>
|
||||
|
|
@ -1,401 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<workbench progressCount="18" version="2.0">
|
||||
<workbenchAdvisor/>
|
||||
<window height="768" maximized="true" width="1024" x="220" y="230">
|
||||
<fastViewData fastViewLocation="1024"/>
|
||||
<perspectiveBar>
|
||||
<itemSize x="160"/>
|
||||
</perspectiveBar>
|
||||
<coolbarLayout locked="0">
|
||||
<coolItem id="group.file" itemType="typeGroupMarker"/>
|
||||
<coolItem id="org.eclipse.ui.workbench.file" itemType="typeToolBarContribution" x="130" y="22"/>
|
||||
<coolItem id="additions" itemType="typeGroupMarker"/>
|
||||
<coolItem id="org.eclipse.cdt.ui.CElementCreationActionSet" itemType="typeToolBarContribution" x="161" y="22"/>
|
||||
<coolItem id="org.eclipse.cdt.ui.buildConfigActionSet" itemType="typeToolBarContribution" x="85" y="22"/>
|
||||
<coolItem id="org.eclipse.debug.ui.launchActionSet" itemType="typeToolBarContribution" x="124" y="22"/>
|
||||
<coolItem id="org.eclipse.jdt.ui.JavaElementCreationActionSet" itemType="typeToolBarContribution" x="98" y="22"/>
|
||||
<coolItem id="org.eclipse.search.searchActionSet" itemType="typeToolBarContribution" x="98" y="22"/>
|
||||
<coolItem id="org.eclipse.ui.edit.text.actionSet.presentation" itemType="typeToolBarContribution" x="85" y="22"/>
|
||||
<coolItem id="group.nav" itemType="typeGroupMarker"/>
|
||||
<coolItem id="org.eclipse.ui.workbench.navigate" itemType="typeToolBarContribution" x="185" y="22"/>
|
||||
<coolItem id="group.editor" itemType="typeGroupMarker"/>
|
||||
<coolItem id="org.eclipse.ui.browser.editor" itemType="typePlaceholder" x="-1" y="-1"/>
|
||||
<coolItem id="org.eclipse.cdt.ui.editor.asm.AsmEditor" itemType="typePlaceholder" x="-1" y="-1"/>
|
||||
<coolItem id="org.eclipse.ui.DefaultTextEditor" itemType="typePlaceholder" x="-1" y="-1"/>
|
||||
<coolItem id="org.eclipse.cdt.ui.editor.CEditor" itemType="typePlaceholder" x="-1" y="-1"/>
|
||||
<coolItem id="org.eclipse.cdt.make.editor" itemType="typePlaceholder" x="-1" y="-1"/>
|
||||
<coolItem id="group.help" itemType="typeGroupMarker"/>
|
||||
<coolItem id="org.eclipse.ui.workbench.help" itemType="typeToolBarContribution" x="-1" y="-1"/>
|
||||
</coolbarLayout>
|
||||
<page aggregateWorkingSetId="Aggregate for window 1217933244875" focus="true" label="Workspace - C/C++">
|
||||
<editors>
|
||||
<editorArea activeWorkbook="DefaultEditorWorkbook">
|
||||
<info part="DefaultEditorWorkbook">
|
||||
<folder appearance="1" expanded="2">
|
||||
<presentation id="org.eclipse.ui.presentations.WorkbenchPresentationFactory"/>
|
||||
</folder>
|
||||
</info>
|
||||
</editorArea>
|
||||
</editors>
|
||||
<views>
|
||||
<view id="org.eclipse.debug.ui.ExpressionView" partName="Expressions">
|
||||
<viewState/>
|
||||
</view>
|
||||
<view id="org.eclipse.cdt.ui.CView" partName="C/C++ Projects">
|
||||
<viewState horizontalPosition="0" verticalPosition="0" workingSet="RTOSDemo">
|
||||
<expanded>
|
||||
<element path="C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\ColdFire_MCF5282_Eclipse\RTOSDemo"/>
|
||||
</expanded>
|
||||
<customFilters userDefinedPatternsEnabled="false">
|
||||
<xmlDefinedFilters>
|
||||
<child filterId="org.eclipse.cdt.internal.ui.CView.ExecutableFilter" isEnabled="false"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<child filterId="org.eclipse.cdt.ui.CView_patternFilterId_.*" isEnabled="true"/>
|
||||
<child filterId="org.eclipse.cdt.internal.ui.CView.ObjectFilter" isEnabled="false"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
<expanded>
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|
||||
<category IMemento.internal.id="Warnings"/>
|
||||
</expanded>
|
||||
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|
||||
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|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.resourceField"/>
|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.pathField"/>
|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.locationField"/>
|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.markerType"/>
|
||||
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|
||||
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|
||||
<view id="org.eclipse.ui.console.ConsoleView" partName="Console">
|
||||
<viewState/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.completionField"/>
|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.priorityField"/>
|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.descriptionField"/>
|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.resourceField"/>
|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.pathField"/>
|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.locationField"/>
|
||||
<visible IMemento.internal.id="org.eclipse.ui.ide.markerType"/>
|
||||
</viewState>
|
||||
</view>
|
||||
</views>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<new_wizard_action id="org.eclipse.cdt.ui.wizards.NewSourceFileCreationWizard"/>
|
||||
<new_wizard_action id="org.eclipse.cdt.ui.wizards.NewHeaderFileCreationWizard"/>
|
||||
<new_wizard_action id="org.eclipse.cdt.ui.wizards.NewFileCreationWizard"/>
|
||||
<new_wizard_action id="org.eclipse.cdt.ui.wizards.NewClassCreationWizard"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<view id="org.eclipse.ui.views.ProblemView"/>
|
||||
<fastViewBars/>
|
||||
<layout>
|
||||
<mainWindow>
|
||||
<info folder="true" part="topLeft">
|
||||
<folder activePageID="org.eclipse.cdt.ui.CView" appearance="2" expanded="2">
|
||||
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|
||||
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|
||||
<page content="org.eclipse.ui.views.ResourceNavigator" label="LabelNotFound"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<folder appearance="2" expanded="2">
|
||||
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|
||||
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|
||||
<page content="org.eclipse.ui.cheatsheets.views.CheatSheetView" label="LabelNotFound"/>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<page content="org.eclipse.debug.ui.DebugView" label="LabelNotFound"/>
|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
</layout>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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||||
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|
||||
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||||
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||||
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|
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||||
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|
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||||
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|
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||||
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|
||||
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||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
|
||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
|
||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
|
||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
|
||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<scannerConfigBuildInfo instanceId="0.1348192838">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
|
||||
<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
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<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
|
||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="makefileGenerator">
|
||||
<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
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||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
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||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileCPP">
|
||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfileC">
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||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
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||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
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||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
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||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileCPP">
|
||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.cpp" command="g++" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfileC">
|
||||
<buildOutputProvider>
|
||||
<openAction enabled="true" filePath=""/>
|
||||
<parser enabled="true"/>
|
||||
</buildOutputProvider>
|
||||
<scannerInfoProvider id="specsFile">
|
||||
<runAction arguments="-E -P -v -dD ${plugin_state_location}/specs.c" command="gcc" useDefault="true"/>
|
||||
<parser enabled="true"/>
|
||||
</scannerInfoProvider>
|
||||
</profile>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="RTOSDemo.null.38326818" name="RTOSDemo"/>
|
||||
</storageModule>
|
||||
</cproject>
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>RTOSDemo</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>cs-make</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>Demo_Source</name>
|
||||
<type>2</type>
|
||||
<locationURI>FREERTOS_ROOT/Demo/Common</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>FreeRTOS_Source</name>
|
||||
<type>2</type>
|
||||
<locationURI>FREERTOS_ROOT/Source</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
#include "MCF5282.h"
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configCPU_CLOCK_HZ ( ( unsigned long ) 64000000 )
|
||||
#define configTICK_RATE_HZ ( ( TickType_t ) 100 )
|
||||
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 190 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40000 ) )
|
||||
#define configMAX_TASK_NAME_LEN ( 12 )
|
||||
#define configUSE_TRACE_FACILITY 1
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 0
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 1
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
#define configQUEUE_REGISTRY_SIZE 10
|
||||
#define configUSE_COUNTING_SEMAPHORES 0
|
||||
|
||||
#define configMAX_PRIORITIES ( 6 )
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero
|
||||
to exclude the API function. */
|
||||
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 0
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark 1
|
||||
#define INCLUDE_eTaskGetState 1
|
||||
|
||||
#define configYIELD_INTERRUPT_VECTOR 16UL
|
||||
#define configKERNEL_INTERRUPT_PRIORITY 1
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4
|
||||
|
||||
void vApplicationSetupInterrupts( void );
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
||||
|
|
@ -1,150 +0,0 @@
|
|||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
|
||||
/* Constants used to configure the interrupts. */
|
||||
#define portPRESCALE_VALUE 64
|
||||
#define portPRESCALE_REG_SETTING ( 5 << 8 )
|
||||
#define portPIT_INTERRUPT_ENABLED ( 0x08 )
|
||||
#define configPIT0_INTERRUPT_VECTOR ( 55 )
|
||||
|
||||
/*
|
||||
* FreeRTOS.org requires two interrupts - a tick interrupt generated from a
|
||||
* timer source, and a spare interrupt vector used for context switching.
|
||||
* The configuration below uses PIT0 for the former, and vector 16 for the
|
||||
* latter. **IF YOUR APPLICATION HAS BOTH OF THESE INTERRUPTS FREE THEN YOU DO
|
||||
* NOT NEED TO CHANGE ANY OF THIS CODE** - otherwise instructions are provided
|
||||
* here for using alternative interrupt sources.
|
||||
*
|
||||
* To change the tick interrupt source:
|
||||
*
|
||||
* 1) Modify vApplicationSetupInterrupts() below to be correct for whichever
|
||||
* peripheral is to be used to generate the tick interrupt.
|
||||
*
|
||||
* 2) Change the name of the function __cs3_isr_interrupt_119() defined within
|
||||
* this file to be correct for the interrupt vector used by the timer peripheral.
|
||||
* The name of the function should contain the vector number, so by default vector
|
||||
* number 119 is being used.
|
||||
*
|
||||
* 3) Make sure the tick interrupt is cleared within the interrupt handler function.
|
||||
* Currently __cs3_isr_interrupt_119() clears the PIT0 interrupt.
|
||||
*
|
||||
* To change the spare interrupt source:
|
||||
*
|
||||
* 1) Modify vApplicationSetupInterrupts() below to be correct for whichever
|
||||
* interrupt vector is to be used. Make sure you use a spare interrupt on interrupt
|
||||
* controller 0, otherwise the register used to request context switches will also
|
||||
* require modification. By default vector 16 is used which is free on most MCF52xxx
|
||||
* devices.
|
||||
*
|
||||
* 2) Change the definition of configYIELD_INTERRUPT_VECTOR within FreeRTOSConfig.h
|
||||
* to be correct for your chosen interrupt vector.
|
||||
*
|
||||
* 3) Change the name of the function __cs3_isr_interrupt_80() within portasm.S
|
||||
* to be correct for whichever vector number is being used. By default interrupt
|
||||
* controller 0 vector number 16 is used, which corresponds to vector number 80.
|
||||
*/
|
||||
void vApplicationSetupInterrupts( void )
|
||||
{
|
||||
const unsigned short usCompareMatchValue = ( ( configCPU_CLOCK_HZ / portPRESCALE_VALUE ) / configTICK_RATE_HZ );
|
||||
|
||||
/* Configure interrupt priority and level and unmask interrupt for PIT0. */
|
||||
MCF_INTC0_ICR55 = ( 1 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );
|
||||
MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK55 );
|
||||
|
||||
/* Do the same for vector 16 (interrupt controller 0). I don't think the
|
||||
write to MCF_INTC0_IMRH is actually required here but is included for
|
||||
completeness. */
|
||||
MCF_INTC0_ICR16 = ( 0 | ( configKERNEL_INTERRUPT_PRIORITY << 3 ) );
|
||||
MCF_INTC0_IMRH &= ~( MCF_INTC_IPRL_INT16 );
|
||||
|
||||
/* Configure PIT0 to generate the RTOS tick. */
|
||||
MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;
|
||||
MCF_PIT0_PCSR = ( portPRESCALE_REG_SETTING | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );
|
||||
MCF_PIT0_PMR = usCompareMatchValue;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void __attribute__ ((interrupt)) __cs3_isr_interrupt_119( void )
|
||||
{
|
||||
unsigned long ulSavedInterruptMask;
|
||||
|
||||
/* Clear the PIT0 interrupt. */
|
||||
MCF_PIT0_PCSR |= MCF_PIT_PCSR_PIF;
|
||||
|
||||
/* Increment the RTOS tick. */
|
||||
ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
taskYIELD();
|
||||
}
|
||||
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
|
||||
}
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "IntQueueTimer.h"
|
||||
#include "IntQueue.h"
|
||||
|
||||
#define timerINTERRUPT1_FREQUENCY ( 2000UL )
|
||||
#define timerINTERRUPT2_FREQUENCY ( 2001UL )
|
||||
#define timerPRESCALE_VALUE ( 2 )
|
||||
|
||||
void vInitialiseTimerForIntQueueTest( void )
|
||||
{
|
||||
const unsigned short usCompareMatchValue1 = ( unsigned short ) ( ( configCPU_CLOCK_HZ / timerPRESCALE_VALUE ) / timerINTERRUPT1_FREQUENCY );
|
||||
const unsigned short usCompareMatchValue2 = ( unsigned short ) ( ( configCPU_CLOCK_HZ / timerPRESCALE_VALUE ) / timerINTERRUPT2_FREQUENCY );
|
||||
|
||||
/* Configure interrupt priority and level and unmask interrupt. */
|
||||
MCF_INTC0_ICR56 = ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 1 ) << 3 );
|
||||
MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK56 );
|
||||
|
||||
MCF_PIT1_PCSR |= MCF_PIT_PCSR_PIF;
|
||||
MCF_PIT1_PCSR = ( MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );
|
||||
MCF_PIT1_PMR = usCompareMatchValue1;
|
||||
|
||||
MCF_INTC0_ICR57 = ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 3 );
|
||||
MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK57 );
|
||||
|
||||
MCF_PIT2_PCSR |= MCF_PIT_PCSR_PIF;
|
||||
MCF_PIT2_PCSR = ( MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN );
|
||||
MCF_PIT2_PMR = usCompareMatchValue2;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void __attribute__ ((interrupt)) __cs3_isr_interrupt_120( void )
|
||||
{
|
||||
MCF_PIT1_PCSR |= MCF_PIT_PCSR_PIF;
|
||||
portEND_SWITCHING_ISR( xFirstTimerHandler() );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void __attribute__ ((interrupt)) __cs3_isr_interrupt_121( void )
|
||||
{
|
||||
MCF_PIT2_PCSR |= MCF_PIT_PCSR_PIF;
|
||||
portEND_SWITCHING_ISR( xSecondTimerHandler() );
|
||||
}
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
/*
|
||||
FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
|
||||
All rights reserved
|
||||
|
||||
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License (version 2) as published by the
|
||||
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
|
||||
|
||||
***************************************************************************
|
||||
>>! NOTE: The modification to the GPL is included to allow you to !<<
|
||||
>>! distribute a combined work that includes FreeRTOS without being !<<
|
||||
>>! obliged to provide the source code for proprietary components !<<
|
||||
>>! outside of the FreeRTOS kernel. !<<
|
||||
***************************************************************************
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. Full license text is available on the following
|
||||
link: http://www.freertos.org/a00114.html
|
||||
|
||||
***************************************************************************
|
||||
* *
|
||||
* FreeRTOS provides completely free yet professionally developed, *
|
||||
* robust, strictly quality controlled, supported, and cross *
|
||||
* platform software that is more than just the market leader, it *
|
||||
* is the industry's de facto standard. *
|
||||
* *
|
||||
* Help yourself get started quickly while simultaneously helping *
|
||||
* to support the FreeRTOS project by purchasing a FreeRTOS *
|
||||
* tutorial book, reference manual, or both: *
|
||||
* http://www.FreeRTOS.org/Documentation *
|
||||
* *
|
||||
***************************************************************************
|
||||
|
||||
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
|
||||
the FAQ page "My application does not run, what could be wrong?". Have you
|
||||
defined configASSERT()?
|
||||
|
||||
http://www.FreeRTOS.org/support - In return for receiving this top quality
|
||||
embedded software for free we request you assist our global community by
|
||||
participating in the support forum.
|
||||
|
||||
http://www.FreeRTOS.org/training - Investing in training allows your team to
|
||||
be as productive as possible as early as possible. Now you can receive
|
||||
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
|
||||
Ltd, and the world's leading authority on the world's leading RTOS.
|
||||
|
||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
|
||||
compatible FAT file system, and our tiny thread aware UDP/IP stack.
|
||||
|
||||
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
|
||||
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
|
||||
|
||||
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
|
||||
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
|
||||
licenses offer ticketed support, indemnification and commercial middleware.
|
||||
|
||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||
engineered and independently SIL3 certified version for use in safety and
|
||||
mission critical applications that require provable dependability.
|
||||
|
||||
1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef INT_QUEUE_TIMER_H
|
||||
#define INT_QUEUE_TIMER_H
|
||||
|
||||
void vInitialiseTimerForIntQueueTest( void );
|
||||
portBASE_TYPE xTimer0Handler( void );
|
||||
portBASE_TYPE xTimer1Handler( void );
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_H__
|
||||
#define __MCF5282_H__
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* The basic data types
|
||||
*/
|
||||
|
||||
typedef unsigned char uint8; /* 8 bits */
|
||||
typedef unsigned short int uint16; /* 16 bits */
|
||||
typedef unsigned long int uint32; /* 32 bits */
|
||||
|
||||
typedef signed char int8; /* 8 bits */
|
||||
typedef signed short int int16; /* 16 bits */
|
||||
typedef signed long int int32; /* 32 bits */
|
||||
|
||||
typedef volatile uint8 vuint8; /* 8 bits */
|
||||
typedef volatile uint16 vuint16; /* 16 bits */
|
||||
typedef volatile uint32 vuint32; /* 32 bits */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#pragma define_section system ".system" far_absolute RW
|
||||
|
||||
/***
|
||||
* MCF5282 Derivative Memory map definitions from linker command files:
|
||||
* __IPSBAR, __FLASHBAR, __FLASHBAR_SIZE, __RAMBAR, __RAMBAR_SIZE
|
||||
* linker symbols must be defined in the linker command file.
|
||||
*/
|
||||
|
||||
extern __declspec(system) uint8 __IPSBAR[];
|
||||
extern __declspec(system) uint8 __FLASHBAR[];
|
||||
extern __declspec(system) uint8 __FLASHBAR_SIZE[];
|
||||
extern __declspec(system) uint8 __RAMBAR[];
|
||||
extern __declspec(system) uint8 __RAMBAR_SIZE[];
|
||||
#endif
|
||||
|
||||
#define __IPSBAR ((uint8*)0x40000000)
|
||||
|
||||
#define IPSBAR_ADDRESS (uint32)__IPSBAR
|
||||
#define FLASHBAR_ADDRESS (uint32)__FLASHBAR
|
||||
#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE
|
||||
#define RAMBAR_ADDRESS (uint32)__RAMBAR
|
||||
#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE
|
||||
|
||||
|
||||
#include "MCF5282_SCM.h"
|
||||
#include "MCF5282_SDRAMC.h"
|
||||
#include "MCF5282_CS.h"
|
||||
#include "MCF5282_DMA.h"
|
||||
#include "MCF5282_UART.h"
|
||||
#include "MCF5282_I2C.h"
|
||||
#include "MCF5282_QSPI.h"
|
||||
#include "MCF5282_DTIM.h"
|
||||
#include "MCF5282_INTC.h"
|
||||
#include "MCF5282_GIACR.h"
|
||||
#include "MCF5282_FEC.h"
|
||||
#include "MCF5282_GPIO.h"
|
||||
#include "MCF5282_PAD.h"
|
||||
#include "MCF5282_RCM.h"
|
||||
#include "MCF5282_PMM.h"
|
||||
#include "MCF5282_CCM.h"
|
||||
#include "MCF5282_CLOCK.h"
|
||||
#include "MCF5282_EPORT.h"
|
||||
#include "MCF5282_WTM.h"
|
||||
#include "MCF5282_PIT.h"
|
||||
#include "MCF5282_QADC.h"
|
||||
#include "MCF5282_GPTA.h"
|
||||
#include "MCF5282_GPTB.h"
|
||||
#include "MCF5282_FlexCAN.h"
|
||||
#include "MCF5282_CFM.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#define MCF5XXX_CACR_CENB (0x80000000)
|
||||
#define MCF5XXX_CACR_CPDI (0x10000000)
|
||||
#define MCF5XXX_CACR_CPD (0x10000000)
|
||||
#define MCF5XXX_CACR_CFRZ (0x08000000)
|
||||
#define MCF5XXX_CACR_CINV (0x01000000)
|
||||
#define MCF5XXX_CACR_DIDI (0x00800000)
|
||||
#define MCF5XXX_CACR_DISD (0x00400000)
|
||||
#define MCF5XXX_CACR_INVI (0x00200000)
|
||||
#define MCF5XXX_CACR_INVD (0x00100000)
|
||||
#define MCF5XXX_CACR_CEIB (0x00000400)
|
||||
#define MCF5XXX_CACR_DCM_WR (0x00000000)
|
||||
#define MCF5XXX_CACR_DCM_CB (0x00000100)
|
||||
#define MCF5XXX_CACR_DCM_IP (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM (0x00000200)
|
||||
#define MCF5XXX_CACR_DCM_II (0x00000300)
|
||||
#define MCF5XXX_CACR_DBWE (0x00000100)
|
||||
#define MCF5XXX_CACR_DWP (0x00000020)
|
||||
#define MCF5XXX_CACR_EUST (0x00000010)
|
||||
#define MCF5XXX_CACR_CLNF_00 (0x00000000)
|
||||
#define MCF5XXX_CACR_CLNF_01 (0x00000002)
|
||||
#define MCF5XXX_CACR_CLNF_10 (0x00000004)
|
||||
#define MCF5XXX_CACR_CLNF_11 (0x00000006)
|
||||
|
||||
#endif /* __MCF5282_H__ */
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_CCM_H__
|
||||
#define __MCF5282_CCM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Configuration Module (CCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CCM_CCR (*(vuint16*)(&__IPSBAR[0x110004]))
|
||||
#define MCF_CCM_RCON (*(vuint16*)(&__IPSBAR[0x110008]))
|
||||
#define MCF_CCM_CIR (*(vuint16*)(&__IPSBAR[0x11000A]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CCR */
|
||||
#define MCF_CCM_CCR_BMT(x) (((x)&0x7)<<0)
|
||||
#define MCF_CCM_CCR_BMT_65536 (0)
|
||||
#define MCF_CCM_CCR_BMT_32768 (0x1)
|
||||
#define MCF_CCM_CCR_BMT_16384 (0x2)
|
||||
#define MCF_CCM_CCR_BMT_8192 (0x3)
|
||||
#define MCF_CCM_CCR_BMT_4096 (0x4)
|
||||
#define MCF_CCM_CCR_BMT_2048 (0x5)
|
||||
#define MCF_CCM_CCR_BMT_1024 (0x6)
|
||||
#define MCF_CCM_CCR_BMT_512 (0x7)
|
||||
#define MCF_CCM_CCR_BME (0x8)
|
||||
#define MCF_CCM_CCR_PSTEN (0x20)
|
||||
#define MCF_CCM_CCR_SZEN (0x40)
|
||||
#define MCF_CCM_CCR_MODE(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_CCM_CCR_LOAD (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_RCON */
|
||||
#define MCF_CCM_RCON_MODE (0x1)
|
||||
#define MCF_CCM_RCON_BOOTSEL (0x4)
|
||||
#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x3)<<0x3)
|
||||
#define MCF_CCM_RCON_RLOAD (0x20)
|
||||
#define MCF_CCM_RCON_RPLLREF (0x40)
|
||||
#define MCF_CCM_RCON_RPLLSEL (0x80)
|
||||
#define MCF_CCM_RCON_RCSC(x) (((x)&0x3)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_CCM_CIR */
|
||||
#define MCF_CCM_CIR_PRN(x) (((x)&0xFF)<<0)
|
||||
#define MCF_CCM_CIR_PIN(x) (((x)&0xFF)<<0x8)
|
||||
|
||||
|
||||
#endif /* __MCF5282_CCM_H__ */
|
||||
|
|
@ -1,72 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_CFM_H__
|
||||
#define __MCF5282_CFM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ColdFire Flash Module (CFM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CFM_CFMMCR (*(vuint16*)(&__IPSBAR[0x1D0000]))
|
||||
#define MCF_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002]))
|
||||
#define MCF_CFM_CFMSEC (*(vuint32*)(&__IPSBAR[0x1D0008]))
|
||||
#define MCF_CFM_CFMPROT (*(vuint32*)(&__IPSBAR[0x1D0010]))
|
||||
#define MCF_CFM_CFMSACC (*(vuint32*)(&__IPSBAR[0x1D0014]))
|
||||
#define MCF_CFM_CFMDACC (*(vuint32*)(&__IPSBAR[0x1D0018]))
|
||||
#define MCF_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020]))
|
||||
#define MCF_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMMCR */
|
||||
#define MCF_CFM_CFMMCR_KEYACC (0x20)
|
||||
#define MCF_CFM_CFMMCR_CCIE (0x40)
|
||||
#define MCF_CFM_CFMMCR_CBEIE (0x80)
|
||||
#define MCF_CFM_CFMMCR_AEIE (0x100)
|
||||
#define MCF_CFM_CFMMCR_PVIE (0x200)
|
||||
#define MCF_CFM_CFMMCR_LOCK (0x400)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMCLKD */
|
||||
#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)
|
||||
#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)
|
||||
#define MCF_CFM_CFMCLKD_DIVLD (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMSEC */
|
||||
#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)
|
||||
#define MCF_CFM_CFMSEC_KEYEN (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMPROT */
|
||||
#define MCF_CFM_CFMPROT_PROT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMSACC */
|
||||
#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMDACC */
|
||||
#define MCF_CFM_CFMDACC_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMUSTAT */
|
||||
#define MCF_CFM_CFMUSTAT_BLANK (0x4)
|
||||
#define MCF_CFM_CFMUSTAT_ACCERR (0x10)
|
||||
#define MCF_CFM_CFMUSTAT_PVIOL (0x20)
|
||||
#define MCF_CFM_CFMUSTAT_CCIF (0x40)
|
||||
#define MCF_CFM_CFMUSTAT_CBEIF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMCMD */
|
||||
#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)
|
||||
#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)
|
||||
#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)
|
||||
#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)
|
||||
#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)
|
||||
#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)
|
||||
|
||||
|
||||
#endif /* __MCF5282_CFM_H__ */
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_CLOCK_H__
|
||||
#define __MCF5282_CLOCK_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Clock Module (CLOCK)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000]))
|
||||
#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_SYNCR */
|
||||
#define MCF_CLOCK_SYNCR_STPMD0 (0x4)
|
||||
#define MCF_CLOCK_SYNCR_STPMD1 (0x8)
|
||||
#define MCF_CLOCK_SYNCR_FWKUP (0x20)
|
||||
#define MCF_CLOCK_SYNCR_DISCLK (0x40)
|
||||
#define MCF_CLOCK_SYNCR_LOCEN (0x80)
|
||||
#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_CLOCK_SYNCR_LOCRE (0x800)
|
||||
#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)
|
||||
#define MCF_CLOCK_SYNCR_LOLRE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_SYNSR */
|
||||
#define MCF_CLOCK_SYNSR_LOCS (0x4)
|
||||
#define MCF_CLOCK_SYNSR_LOCK (0x8)
|
||||
#define MCF_CLOCK_SYNSR_LOCKS (0x10)
|
||||
#define MCF_CLOCK_SYNSR_PLLREF (0x20)
|
||||
#define MCF_CLOCK_SYNSR_PLLSEL (0x40)
|
||||
#define MCF_CLOCK_SYNSR_PLLMODE (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF5282_CLOCK_H__ */
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_CS_H__
|
||||
#define __MCF5282_CS_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Chip Select Module (CS)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CS0_CSAR (*(vuint16*)(&__IPSBAR[0x80]))
|
||||
#define MCF_CS0_CSMR (*(vuint32*)(&__IPSBAR[0x84]))
|
||||
#define MCF_CS0_CSCR (*(vuint16*)(&__IPSBAR[0x8A]))
|
||||
|
||||
#define MCF_CS1_CSAR (*(vuint16*)(&__IPSBAR[0x8C]))
|
||||
#define MCF_CS1_CSMR (*(vuint32*)(&__IPSBAR[0x90]))
|
||||
#define MCF_CS1_CSCR (*(vuint16*)(&__IPSBAR[0x96]))
|
||||
|
||||
#define MCF_CS2_CSAR (*(vuint16*)(&__IPSBAR[0x98]))
|
||||
#define MCF_CS2_CSMR (*(vuint32*)(&__IPSBAR[0x9C]))
|
||||
#define MCF_CS2_CSCR (*(vuint16*)(&__IPSBAR[0xA2]))
|
||||
|
||||
#define MCF_CS3_CSAR (*(vuint16*)(&__IPSBAR[0xA4]))
|
||||
#define MCF_CS3_CSMR (*(vuint32*)(&__IPSBAR[0xA8]))
|
||||
#define MCF_CS3_CSCR (*(vuint16*)(&__IPSBAR[0xAE]))
|
||||
|
||||
#define MCF_CS4_CSAR (*(vuint16*)(&__IPSBAR[0xB0]))
|
||||
#define MCF_CS4_CSMR (*(vuint32*)(&__IPSBAR[0xB4]))
|
||||
#define MCF_CS4_CSCR (*(vuint16*)(&__IPSBAR[0xBA]))
|
||||
|
||||
#define MCF_CS5_CSAR (*(vuint16*)(&__IPSBAR[0xBC]))
|
||||
#define MCF_CS5_CSMR (*(vuint32*)(&__IPSBAR[0xC0]))
|
||||
#define MCF_CS5_CSCR (*(vuint16*)(&__IPSBAR[0xC6]))
|
||||
|
||||
#define MCF_CS6_CSAR (*(vuint16*)(&__IPSBAR[0xC8]))
|
||||
#define MCF_CS6_CSMR (*(vuint32*)(&__IPSBAR[0xCC]))
|
||||
#define MCF_CS6_CSCR (*(vuint16*)(&__IPSBAR[0xD2]))
|
||||
|
||||
#define MCF_CS_CSAR(x) (*(vuint16*)(&__IPSBAR[0x80 + ((x)*0xC)]))
|
||||
#define MCF_CS_CSMR(x) (*(vuint32*)(&__IPSBAR[0x84 + ((x)*0xC)]))
|
||||
#define MCF_CS_CSCR(x) (*(vuint16*)(&__IPSBAR[0x8A + ((x)*0xC)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSAR */
|
||||
#define MCF_CS_CSAR_BA(x) (vuint16)(((x)&0xFFFF0000)>>0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSMR */
|
||||
#define MCF_CS_CSMR_V (0x1)
|
||||
#define MCF_CS_CSMR_UD (0x2)
|
||||
#define MCF_CS_CSMR_UC (0x4)
|
||||
#define MCF_CS_CSMR_SD (0x8)
|
||||
#define MCF_CS_CSMR_SC (0x10)
|
||||
#define MCF_CS_CSMR_CI (0x20)
|
||||
#define MCF_CS_CSMR_AM (0x40)
|
||||
#define MCF_CS_CSMR_WP (0x100)
|
||||
#define MCF_CS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
|
||||
#define MCF_CS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define MCF_CS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define MCF_CS_CSMR_BAM_256M (0xFFF0000)
|
||||
#define MCF_CS_CSMR_BAM_128M (0x7FF0000)
|
||||
#define MCF_CS_CSMR_BAM_64M (0x3FF0000)
|
||||
#define MCF_CS_CSMR_BAM_32M (0x1FF0000)
|
||||
#define MCF_CS_CSMR_BAM_16M (0xFF0000)
|
||||
#define MCF_CS_CSMR_BAM_8M (0x7F0000)
|
||||
#define MCF_CS_CSMR_BAM_4M (0x3F0000)
|
||||
#define MCF_CS_CSMR_BAM_2M (0x1F0000)
|
||||
#define MCF_CS_CSMR_BAM_1M (0xF0000)
|
||||
#define MCF_CS_CSMR_BAM_1024K (0xF0000)
|
||||
#define MCF_CS_CSMR_BAM_512K (0x70000)
|
||||
#define MCF_CS_CSMR_BAM_256K (0x30000)
|
||||
#define MCF_CS_CSMR_BAM_128K (0x10000)
|
||||
#define MCF_CS_CSMR_BAM_64K (0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CS_CSCR */
|
||||
#define MCF_CS_CSCR_BSTW (0x8)
|
||||
#define MCF_CS_CSCR_BSTR (0x10)
|
||||
#define MCF_CS_CSCR_BEM (0x20)
|
||||
#define MCF_CS_CSCR_PS(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_CS_CSCR_PS_32 (0)
|
||||
#define MCF_CS_CSCR_PS_8 (0x40)
|
||||
#define MCF_CS_CSCR_PS_16 (0x80)
|
||||
#define MCF_CS_CSCR_AA (0x100)
|
||||
#define MCF_CS_CSCR_WS(x) (((x)&0xF)<<0xA)
|
||||
|
||||
|
||||
#endif /* __MCF5282_CS_H__ */
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_DMA_H__
|
||||
#define __MCF5282_DMA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Controller (DMA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DMA0_SAR (*(vuint32*)(&__IPSBAR[0x100]))
|
||||
#define MCF_DMA0_DAR (*(vuint32*)(&__IPSBAR[0x104]))
|
||||
#define MCF_DMA0_DCR (*(vuint32*)(&__IPSBAR[0x108]))
|
||||
#define MCF_DMA0_BCR (*(vuint32*)(&__IPSBAR[0x10C]))
|
||||
#define MCF_DMA0_DSR (*(vuint8 *)(&__IPSBAR[0x110]))
|
||||
|
||||
#define MCF_DMA1_SAR (*(vuint32*)(&__IPSBAR[0x140]))
|
||||
#define MCF_DMA1_DAR (*(vuint32*)(&__IPSBAR[0x144]))
|
||||
#define MCF_DMA1_DCR (*(vuint32*)(&__IPSBAR[0x148]))
|
||||
#define MCF_DMA1_BCR (*(vuint32*)(&__IPSBAR[0x14C]))
|
||||
#define MCF_DMA1_DSR (*(vuint8 *)(&__IPSBAR[0x150]))
|
||||
|
||||
#define MCF_DMA2_SAR (*(vuint32*)(&__IPSBAR[0x180]))
|
||||
#define MCF_DMA2_DAR (*(vuint32*)(&__IPSBAR[0x184]))
|
||||
#define MCF_DMA2_DCR (*(vuint32*)(&__IPSBAR[0x188]))
|
||||
#define MCF_DMA2_BCR (*(vuint32*)(&__IPSBAR[0x18C]))
|
||||
#define MCF_DMA2_DSR (*(vuint8 *)(&__IPSBAR[0x190]))
|
||||
|
||||
#define MCF_DMA3_SAR (*(vuint32*)(&__IPSBAR[0x1C0]))
|
||||
#define MCF_DMA3_DAR (*(vuint32*)(&__IPSBAR[0x1C4]))
|
||||
#define MCF_DMA3_DCR (*(vuint32*)(&__IPSBAR[0x1C8]))
|
||||
#define MCF_DMA3_BCR (*(vuint32*)(&__IPSBAR[0x1CC]))
|
||||
#define MCF_DMA3_DSR (*(vuint8 *)(&__IPSBAR[0x1D0]))
|
||||
|
||||
#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x100 + ((x)*0x40)]))
|
||||
#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x104 + ((x)*0x40)]))
|
||||
#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x108 + ((x)*0x40)]))
|
||||
#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x10C + ((x)*0x40)]))
|
||||
#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x110 + ((x)*0x40)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_SAR */
|
||||
#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DAR */
|
||||
#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DCR */
|
||||
#define MCF_DMA_DCR_AT (0x8000)
|
||||
#define MCF_DMA_DCR_START (0x10000)
|
||||
#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)
|
||||
#define MCF_DMA_DCR_DSIZE_LONG (0)
|
||||
#define MCF_DMA_DCR_DSIZE_BYTE (0x1)
|
||||
#define MCF_DMA_DCR_DSIZE_WORD (0x2)
|
||||
#define MCF_DMA_DCR_DSIZE_LINE (0x3)
|
||||
#define MCF_DMA_DCR_DINC (0x80000)
|
||||
#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_DCR_SSIZE_LONG (0)
|
||||
#define MCF_DMA_DCR_SSIZE_BYTE (0x1)
|
||||
#define MCF_DMA_DCR_SSIZE_WORD (0x2)
|
||||
#define MCF_DMA_DCR_SSIZE_LINE (0x3)
|
||||
#define MCF_DMA_DCR_SINC (0x400000)
|
||||
#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)
|
||||
#define MCF_DMA_DCR_AA (0x10000000)
|
||||
#define MCF_DMA_DCR_CS (0x20000000)
|
||||
#define MCF_DMA_DCR_EEXT (0x40000000)
|
||||
#define MCF_DMA_DCR_INT (0x80000000)
|
||||
#define MCF_DMA_DCR_BWC_DMA (0)
|
||||
#define MCF_DMA_DCR_BWC_512 (0x2000000)
|
||||
#define MCF_DMA_DCR_BWC_1024 (0x4000000)
|
||||
#define MCF_DMA_DCR_BWC_2048 (0x6000000)
|
||||
#define MCF_DMA_DCR_BWC_4096 (0x8000000)
|
||||
#define MCF_DMA_DCR_BWC_8192 (0xA000000)
|
||||
#define MCF_DMA_DCR_BWC_16384 (0xC000000)
|
||||
#define MCF_DMA_DCR_BWC_32768 (0xE000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_BCR */
|
||||
#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DSR */
|
||||
#define MCF_DMA_DSR_DONE (0x1)
|
||||
#define MCF_DMA_DSR_BSY (0x2)
|
||||
#define MCF_DMA_DSR_REQ (0x4)
|
||||
#define MCF_DMA_DSR_BED (0x10)
|
||||
#define MCF_DMA_DSR_BES (0x20)
|
||||
#define MCF_DMA_DSR_CE (0x40)
|
||||
|
||||
|
||||
#endif /* __MCF5282_DMA_H__ */
|
||||
|
|
@ -1,90 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_DTIM_H__
|
||||
#define __MCF5282_DTIM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Timers (DTIM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x400]))
|
||||
#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x402]))
|
||||
#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x403]))
|
||||
#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x404]))
|
||||
#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x408]))
|
||||
#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x40C]))
|
||||
|
||||
#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x440]))
|
||||
#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x442]))
|
||||
#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x443]))
|
||||
#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x444]))
|
||||
#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x448]))
|
||||
#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x44C]))
|
||||
|
||||
#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x480]))
|
||||
#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x482]))
|
||||
#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x483]))
|
||||
#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x484]))
|
||||
#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x488]))
|
||||
#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x48C]))
|
||||
|
||||
#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x4C0]))
|
||||
#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x4C2]))
|
||||
#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x4C3]))
|
||||
#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x4C4]))
|
||||
#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x4C8]))
|
||||
#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x4CC]))
|
||||
|
||||
#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x400 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x402 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x403 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x404 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x408 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x40C + ((x)*0x40)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTMR */
|
||||
#define MCF_DTIM_DTMR_RST (0x1)
|
||||
#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)
|
||||
#define MCF_DTIM_DTMR_CLK_STOP (0)
|
||||
#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)
|
||||
#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)
|
||||
#define MCF_DTIM_DTMR_CLK_DTIN (0x6)
|
||||
#define MCF_DTIM_DTMR_FRR (0x8)
|
||||
#define MCF_DTIM_DTMR_ORRI (0x10)
|
||||
#define MCF_DTIM_DTMR_OM (0x20)
|
||||
#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DTIM_DTMR_CE_NONE (0)
|
||||
#define MCF_DTIM_DTMR_CE_RISE (0x40)
|
||||
#define MCF_DTIM_DTMR_CE_FALL (0x80)
|
||||
#define MCF_DTIM_DTMR_CE_ANY (0xC0)
|
||||
#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTXMR */
|
||||
#define MCF_DTIM_DTXMR_MODE16 (0x1)
|
||||
#define MCF_DTIM_DTXMR_DMAEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTER */
|
||||
#define MCF_DTIM_DTER_CAP (0x1)
|
||||
#define MCF_DTIM_DTER_REF (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTRR */
|
||||
#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTCR */
|
||||
#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTCN */
|
||||
#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5282_DTIM_H__ */
|
||||
|
|
@ -1,115 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_EPORT_H__
|
||||
#define __MCF5282_EPORT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT_EPPAR (*(vuint16*)(&__IPSBAR[0x130000]))
|
||||
#define MCF_EPORT_EPDDR (*(vuint8 *)(&__IPSBAR[0x130002]))
|
||||
#define MCF_EPORT_EPIER (*(vuint8 *)(&__IPSBAR[0x130003]))
|
||||
#define MCF_EPORT_EPDR (*(vuint8 *)(&__IPSBAR[0x130004]))
|
||||
#define MCF_EPORT_EPPDR (*(vuint8 *)(&__IPSBAR[0x130005]))
|
||||
#define MCF_EPORT_EPFR (*(vuint8 *)(&__IPSBAR[0x130006]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
|
||||
#define MCF_EPORT_EPPAR_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_RISING (0x1)
|
||||
#define MCF_EPORT_EPPAR_FALLING (0x2)
|
||||
#define MCF_EPORT_EPPAR_BOTH (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x2)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x4)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x8)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x2)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x4)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x8)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x2)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x4)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x8)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF5282_EPORT_H__ */
|
||||
|
|
@ -1,385 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_FEC_H__
|
||||
#define __MCF5282_FEC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller(FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x1004]))
|
||||
#define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x1008]))
|
||||
#define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x1010]))
|
||||
#define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x1014]))
|
||||
#define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x1024]))
|
||||
#define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x1040]))
|
||||
#define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x1044]))
|
||||
#define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x1064]))
|
||||
#define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x1084]))
|
||||
#define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x10C4]))
|
||||
#define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x10E4]))
|
||||
#define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x10E8]))
|
||||
#define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x10EC]))
|
||||
#define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x1118]))
|
||||
#define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x111C]))
|
||||
#define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x1120]))
|
||||
#define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x1124]))
|
||||
#define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x1144]))
|
||||
#define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x114C]))
|
||||
#define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x1150]))
|
||||
#define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x1180]))
|
||||
#define MCF_FEC_ETSDR (*(vuint32*)(&__IPSBAR[0x1184]))
|
||||
#define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x1188]))
|
||||
#define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x1200]))
|
||||
#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x1204]))
|
||||
#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x1208]))
|
||||
#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x120C]))
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1210]))
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1214]))
|
||||
#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1218]))
|
||||
#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x121C]))
|
||||
#define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x1220]))
|
||||
#define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x1224]))
|
||||
#define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x1228]))
|
||||
#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x122C]))
|
||||
#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x1230]))
|
||||
#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x1234]))
|
||||
#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x1238]))
|
||||
#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x123C]))
|
||||
#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x1240]))
|
||||
#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x1244]))
|
||||
#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x1248]))
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x124C]))
|
||||
#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x1250]))
|
||||
#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x1254]))
|
||||
#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x1258]))
|
||||
#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x125C]))
|
||||
#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x1260]))
|
||||
#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x1264]))
|
||||
#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x1268]))
|
||||
#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x126C]))
|
||||
#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x1270]))
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x1274]))
|
||||
#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x1284]))
|
||||
#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x1288]))
|
||||
#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x128C]))
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1290]))
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1294]))
|
||||
#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1298]))
|
||||
#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x129C]))
|
||||
#define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x12A0]))
|
||||
#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x12A4]))
|
||||
#define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x12A8]))
|
||||
#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x12AC]))
|
||||
#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x12B0]))
|
||||
#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x12B4]))
|
||||
#define MCF_FEC_RMON_R_P512TO1023 (*(vuint32*)(&__IPSBAR[0x12B8]))
|
||||
#define MCF_FEC_RMON_R_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x12BC]))
|
||||
#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x12C0]))
|
||||
#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x12C4]))
|
||||
#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x12C8]))
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x12CC]))
|
||||
#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x12D0]))
|
||||
#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x12D4]))
|
||||
#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x12D8]))
|
||||
#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x12DC]))
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x12E0]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIR */
|
||||
#define MCF_FEC_EIR_UN (0x80000)
|
||||
#define MCF_FEC_EIR_RL (0x100000)
|
||||
#define MCF_FEC_EIR_LC (0x200000)
|
||||
#define MCF_FEC_EIR_EBERR (0x400000)
|
||||
#define MCF_FEC_EIR_MII (0x800000)
|
||||
#define MCF_FEC_EIR_RXB (0x1000000)
|
||||
#define MCF_FEC_EIR_RXF (0x2000000)
|
||||
#define MCF_FEC_EIR_TXB (0x4000000)
|
||||
#define MCF_FEC_EIR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIMR */
|
||||
#define MCF_FEC_EIMR_UN (0x80000)
|
||||
#define MCF_FEC_EIMR_RL (0x100000)
|
||||
#define MCF_FEC_EIMR_LC (0x200000)
|
||||
#define MCF_FEC_EIMR_EBERR (0x400000)
|
||||
#define MCF_FEC_EIMR_MII (0x800000)
|
||||
#define MCF_FEC_EIMR_RXB (0x1000000)
|
||||
#define MCF_FEC_EIMR_RXF (0x2000000)
|
||||
#define MCF_FEC_EIMR_TXB (0x4000000)
|
||||
#define MCF_FEC_EIMR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIMR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIMR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIMR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIMR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIMR_MASK_ALL (0)
|
||||
#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RDAR */
|
||||
#define MCF_FEC_RDAR_R_DES_ACTIVE (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TDAR */
|
||||
#define MCF_FEC_TDAR_X_DES_ACTIVE (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ECR */
|
||||
#define MCF_FEC_ECR_RESET (0x1)
|
||||
#define MCF_FEC_ECR_ETHER_EN (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MMFR */
|
||||
#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_FEC_MMFR_TA_10 (0x20000)
|
||||
#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
|
||||
#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
|
||||
#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_FEC_MMFR_OP_READ (0x20000000)
|
||||
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
|
||||
#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
|
||||
#define MCF_FEC_MMFR_ST_01 (0x40000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MSCR */
|
||||
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
|
||||
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MIBC */
|
||||
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RCR */
|
||||
#define MCF_FEC_RCR_LOOP (0x1)
|
||||
#define MCF_FEC_RCR_DRT (0x2)
|
||||
#define MCF_FEC_RCR_MII_MODE (0x4)
|
||||
#define MCF_FEC_RCR_PROM (0x8)
|
||||
#define MCF_FEC_RCR_BC_REJ (0x10)
|
||||
#define MCF_FEC_RCR_FCE (0x20)
|
||||
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TCR */
|
||||
#define MCF_FEC_TCR_GTS (0x1)
|
||||
#define MCF_FEC_TCR_HBC (0x2)
|
||||
#define MCF_FEC_TCR_FDEN (0x4)
|
||||
#define MCF_FEC_TCR_TFC_PAUSE (0x8)
|
||||
#define MCF_FEC_TCR_RFC_PAUSE (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PALR */
|
||||
#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PAUR */
|
||||
#define MCF_FEC_PAUR_TYPE(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_OPD */
|
||||
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IAUR */
|
||||
#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IALR */
|
||||
#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GAUR */
|
||||
#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GALR */
|
||||
#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TFWR */
|
||||
#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x3)<<0)
|
||||
#define MCF_FEC_TFWR_X_WMRK_64 (0)
|
||||
#define MCF_FEC_TFWR_X_WMRK_128 (0x2)
|
||||
#define MCF_FEC_TFWR_X_WMRK_192 (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRBR */
|
||||
#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRSR */
|
||||
#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ERDSR */
|
||||
#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ETSDR */
|
||||
#define MCF_FEC_ETSDR_X_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EMRBR */
|
||||
#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
|
||||
#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
|
||||
#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
|
||||
#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
|
||||
#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
|
||||
#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
|
||||
#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
|
||||
#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
|
||||
#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
|
||||
#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
|
||||
#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
|
||||
#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
|
||||
#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
|
||||
#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
|
||||
#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
|
||||
#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
|
||||
#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
|
||||
#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
|
||||
#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
|
||||
#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
|
||||
#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
|
||||
#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
|
||||
#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
|
||||
#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
|
||||
#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
|
||||
#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
|
||||
#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
|
||||
#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
|
||||
#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
|
||||
#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
|
||||
#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
|
||||
#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
|
||||
#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
|
||||
#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
|
||||
#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
|
||||
#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
|
||||
#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
|
||||
#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
|
||||
#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
|
||||
#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
|
||||
#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
|
||||
#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
|
||||
#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5282_FEC_H__ */
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_FlexCAN_H__
|
||||
#define __MCF5282_FlexCAN_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Flex Controller Area Network (FlexCAN)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FlexCAN_CANMCR (*(vuint16*)(&__IPSBAR[0x1C0000]))
|
||||
#define MCF_FlexCAN_CANCTRL0 (*(vuint8 *)(&__IPSBAR[0x1C0006]))
|
||||
#define MCF_FlexCAN_CANCTRL1 (*(vuint8 *)(&__IPSBAR[0x1C0007]))
|
||||
#define MCF_FlexCAN_PRESDIV (*(vuint8 *)(&__IPSBAR[0x1C0008]))
|
||||
#define MCF_FlexCAN_CANCTRL2 (*(vuint8 *)(&__IPSBAR[0x1C0009]))
|
||||
#define MCF_FlexCAN_TIMER (*(vuint16*)(&__IPSBAR[0x1C000A]))
|
||||
#define MCF_FlexCAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010]))
|
||||
#define MCF_FlexCAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014]))
|
||||
#define MCF_FlexCAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018]))
|
||||
#define MCF_FlexCAN_ESTAT (*(vuint16*)(&__IPSBAR[0x1C0020]))
|
||||
#define MCF_FlexCAN_IMASK (*(vuint16*)(&__IPSBAR[0x1C0022]))
|
||||
#define MCF_FlexCAN_IFLAG (*(vuint16*)(&__IPSBAR[0x1C0024]))
|
||||
#define MCF_FlexCAN_RXECTR (*(vuint8 *)(&__IPSBAR[0x1C0026]))
|
||||
#define MCF_FlexCAN_TXECTR (*(vuint8 *)(&__IPSBAR[0x1C0028]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_CANMCR */
|
||||
#define MCF_FlexCAN_CANMCR_STOPACK (0x10)
|
||||
#define MCF_FlexCAN_CANMCR_APS (0x20)
|
||||
#define MCF_FlexCAN_CANMCR_SELFWAKE (0x40)
|
||||
#define MCF_FlexCAN_CANMCR_SUPV (0x80)
|
||||
#define MCF_FlexCAN_CANMCR_FRZACK (0x100)
|
||||
#define MCF_FlexCAN_CANMCR_SOFTRST (0x200)
|
||||
#define MCF_FlexCAN_CANMCR_WAKEMSK (0x400)
|
||||
#define MCF_FlexCAN_CANMCR_NOTRDY (0x800)
|
||||
#define MCF_FlexCAN_CANMCR_HALT (0x1000)
|
||||
#define MCF_FlexCAN_CANMCR_FRZ (0x4000)
|
||||
#define MCF_FlexCAN_CANMCR_STOP (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_CANCTRL0 */
|
||||
#define MCF_FlexCAN_CANCTRL0_TXMODE(x) (((x)&0x3)<<0)
|
||||
#define MCF_FlexCAN_CANCTRL0_RXMODE (0x4)
|
||||
#define MCF_FlexCAN_CANCTRL0_ERRMSK (0x40)
|
||||
#define MCF_FlexCAN_CANCTRL0_BOFFMSK (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_CANCTRL1 */
|
||||
#define MCF_FlexCAN_CANCTRL1_PROPSEG(x) (((x)&0x7)<<0)
|
||||
#define MCF_FlexCAN_CANCTRL1_LOM (0x8)
|
||||
#define MCF_FlexCAN_CANCTRL1_LBUF (0x10)
|
||||
#define MCF_FlexCAN_CANCTRL1_TSYNC (0x20)
|
||||
#define MCF_FlexCAN_CANCTRL1_SAMP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_PRESDIV */
|
||||
#define MCF_FlexCAN_PRESDIV_PRES_DIV(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_CANCTRL2 */
|
||||
#define MCF_FlexCAN_CANCTRL2_PSEG2(x) (((x)&0x7)<<0)
|
||||
#define MCF_FlexCAN_CANCTRL2_PSEG1(x) (((x)&0x7)<<0x3)
|
||||
#define MCF_FlexCAN_CANCTRL2_RJW(x) (((x)&0x3)<<0x6)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_TIMER */
|
||||
#define MCF_FlexCAN_TIMER_TIMER(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_RXGMASK */
|
||||
#define MCF_FlexCAN_RXGMASK_MID(x) (((x)&0x7FFFFFFF)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_RX14MASK */
|
||||
#define MCF_FlexCAN_RX14MASK_MID(x) (((x)&0x7FFFFFFF)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_RX15MASK */
|
||||
#define MCF_FlexCAN_RX15MASK_MID(x) (((x)&0x7FFFFFFF)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_ESTAT */
|
||||
#define MCF_FlexCAN_ESTAT_WAKEINT (0x1)
|
||||
#define MCF_FlexCAN_ESTAT_BOFFINT (0x2)
|
||||
#define MCF_FlexCAN_ESTAT_ERRINT (0x4)
|
||||
#define MCF_FlexCAN_ESTAT_FCS(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_FlexCAN_ESTAT_FCS_ACTIVE (0)
|
||||
#define MCF_FlexCAN_ESTAT_FCS_PASSIVE (0x10)
|
||||
#define MCF_FlexCAN_ESTAT_TXRX (0x40)
|
||||
#define MCF_FlexCAN_ESTAT_IDLE (0x80)
|
||||
#define MCF_FlexCAN_ESTAT_RXWARN (0x100)
|
||||
#define MCF_FlexCAN_ESTAT_TXWARN (0x200)
|
||||
#define MCF_FlexCAN_ESTAT_STUFFERR (0x400)
|
||||
#define MCF_FlexCAN_ESTAT_FORMERR (0x800)
|
||||
#define MCF_FlexCAN_ESTAT_CRCERR (0x1000)
|
||||
#define MCF_FlexCAN_ESTAT_ACKERR (0x2000)
|
||||
#define MCF_FlexCAN_ESTAT_BITERR(x) (((x)&0x3)<<0xE)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_IMASK */
|
||||
#define MCF_FlexCAN_IMASK_BUF0M (0x1)
|
||||
#define MCF_FlexCAN_IMASK_BUF1M (0x2)
|
||||
#define MCF_FlexCAN_IMASK_BUF2M (0x4)
|
||||
#define MCF_FlexCAN_IMASK_BUF3M (0x8)
|
||||
#define MCF_FlexCAN_IMASK_BUF4M (0x10)
|
||||
#define MCF_FlexCAN_IMASK_BUF5M (0x20)
|
||||
#define MCF_FlexCAN_IMASK_BUF6M (0x40)
|
||||
#define MCF_FlexCAN_IMASK_BUF7M (0x80)
|
||||
#define MCF_FlexCAN_IMASK_BUF8M (0x100)
|
||||
#define MCF_FlexCAN_IMASK_BUF9M (0x200)
|
||||
#define MCF_FlexCAN_IMASK_BUF10M (0x400)
|
||||
#define MCF_FlexCAN_IMASK_BUF11M (0x800)
|
||||
#define MCF_FlexCAN_IMASK_BUF12M (0x1000)
|
||||
#define MCF_FlexCAN_IMASK_BUF13M (0x2000)
|
||||
#define MCF_FlexCAN_IMASK_BUF14M (0x4000)
|
||||
#define MCF_FlexCAN_IMASK_BUF15M (0x8000)
|
||||
#define MCF_FlexCAN_IMASK_BUF(x) (0x1<<(x))
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_IFLAG */
|
||||
#define MCF_FlexCAN_IFLAG_BUF0I (0x1)
|
||||
#define MCF_FlexCAN_IFLAG_BUF1I (0x2)
|
||||
#define MCF_FlexCAN_IFLAG_BUF2I (0x4)
|
||||
#define MCF_FlexCAN_IFLAG_BUF3I (0x8)
|
||||
#define MCF_FlexCAN_IFLAG_BUF4I (0x10)
|
||||
#define MCF_FlexCAN_IFLAG_BUF5I (0x20)
|
||||
#define MCF_FlexCAN_IFLAG_BUF6I (0x40)
|
||||
#define MCF_FlexCAN_IFLAG_BUF7I (0x80)
|
||||
#define MCF_FlexCAN_IFLAG_BUF8I (0x100)
|
||||
#define MCF_FlexCAN_IFLAG_BUF9I (0x200)
|
||||
#define MCF_FlexCAN_IFLAG_BUF10I (0x400)
|
||||
#define MCF_FlexCAN_IFLAG_BUF11I (0x800)
|
||||
#define MCF_FlexCAN_IFLAG_BUF12I (0x1000)
|
||||
#define MCF_FlexCAN_IFLAG_BUF13I (0x2000)
|
||||
#define MCF_FlexCAN_IFLAG_BUF14I (0x4000)
|
||||
#define MCF_FlexCAN_IFLAG_BUF15I (0x8000)
|
||||
#define MCF_FlexCAN_IFLAG_BUF(x) (0x1<<(x))
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_RXECTR */
|
||||
#define MCF_FlexCAN_RXECTR_RXECTR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_TXECTR */
|
||||
#define MCF_FlexCAN_TXECTR_TXECTR(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5282_FlexCAN_H__ */
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_GIACR_H__
|
||||
#define __MCF5282_GIACR_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global Interrupt Acknowledge Control Registers Module (GIACR)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GIACR_GSWIACK (*(vuint8 *)(&__IPSBAR[0xFE0]))
|
||||
#define MCF_GIACR_GL1IACK (*(vuint8 *)(&__IPSBAR[0xFE4]))
|
||||
#define MCF_GIACR_GL2IACK (*(vuint8 *)(&__IPSBAR[0xFE8]))
|
||||
#define MCF_GIACR_GL3IACK (*(vuint8 *)(&__IPSBAR[0xFEC]))
|
||||
#define MCF_GIACR_GL4IACK (*(vuint8 *)(&__IPSBAR[0xFF0]))
|
||||
#define MCF_GIACR_GL5IACK (*(vuint8 *)(&__IPSBAR[0xFF4]))
|
||||
#define MCF_GIACR_GL6IACK (*(vuint8 *)(&__IPSBAR[0xFF8]))
|
||||
#define MCF_GIACR_GL7IACK (*(vuint8 *)(&__IPSBAR[0xFFC]))
|
||||
#define MCF_GIACR_GLIACK(x) (*(vuint8 *)(&__IPSBAR[0xFE4 + ((x-1)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GIACR_GSWIACK */
|
||||
#define MCF_GIACR_GSWIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GIACR_GLIACK */
|
||||
#define MCF_GIACR_GLIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5282_GIACR_H__ */
|
||||
|
|
@ -1,764 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_GPIO_H__
|
||||
#define __MCF5282_GPIO_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose I/O (GPIO)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPIO_PORTA (*(vuint8 *)(&__IPSBAR[0x100000]))
|
||||
#define MCF_GPIO_DDRA (*(vuint8 *)(&__IPSBAR[0x100014]))
|
||||
#define MCF_GPIO_SETA (*(vuint8 *)(&__IPSBAR[0x100028]))
|
||||
#define MCF_GPIO_CLRA (*(vuint8 *)(&__IPSBAR[0x10003C]))
|
||||
|
||||
#define MCF_GPIO_PORTB (*(vuint8 *)(&__IPSBAR[0x100001]))
|
||||
#define MCF_GPIO_DDRB (*(vuint8 *)(&__IPSBAR[0x100015]))
|
||||
#define MCF_GPIO_SETB (*(vuint8 *)(&__IPSBAR[0x100029]))
|
||||
#define MCF_GPIO_CLRB (*(vuint8 *)(&__IPSBAR[0x10003D]))
|
||||
|
||||
#define MCF_GPIO_PORTC (*(vuint8 *)(&__IPSBAR[0x100002]))
|
||||
#define MCF_GPIO_DDRC (*(vuint8 *)(&__IPSBAR[0x100016]))
|
||||
#define MCF_GPIO_SETC (*(vuint8 *)(&__IPSBAR[0x10002A]))
|
||||
#define MCF_GPIO_CLRC (*(vuint8 *)(&__IPSBAR[0x10003E]))
|
||||
|
||||
#define MCF_GPIO_PORTD (*(vuint8 *)(&__IPSBAR[0x100003]))
|
||||
#define MCF_GPIO_DDRD (*(vuint8 *)(&__IPSBAR[0x100017]))
|
||||
#define MCF_GPIO_SETD (*(vuint8 *)(&__IPSBAR[0x10002B]))
|
||||
#define MCF_GPIO_CLRD (*(vuint8 *)(&__IPSBAR[0x10003F]))
|
||||
|
||||
#define MCF_GPIO_PORTE (*(vuint8 *)(&__IPSBAR[0x100004]))
|
||||
#define MCF_GPIO_DDRE (*(vuint8 *)(&__IPSBAR[0x100018]))
|
||||
#define MCF_GPIO_SETE (*(vuint8 *)(&__IPSBAR[0x10002C]))
|
||||
#define MCF_GPIO_CLRE (*(vuint8 *)(&__IPSBAR[0x100040]))
|
||||
|
||||
#define MCF_GPIO_PORTF (*(vuint8 *)(&__IPSBAR[0x100005]))
|
||||
#define MCF_GPIO_DDRF (*(vuint8 *)(&__IPSBAR[0x100019]))
|
||||
#define MCF_GPIO_SETF (*(vuint8 *)(&__IPSBAR[0x10002D]))
|
||||
#define MCF_GPIO_CLRF (*(vuint8 *)(&__IPSBAR[0x100041]))
|
||||
|
||||
#define MCF_GPIO_PORTG (*(vuint8 *)(&__IPSBAR[0x100006]))
|
||||
#define MCF_GPIO_DDRG (*(vuint8 *)(&__IPSBAR[0x10001A]))
|
||||
#define MCF_GPIO_SETG (*(vuint8 *)(&__IPSBAR[0x10002E]))
|
||||
#define MCF_GPIO_CLRG (*(vuint8 *)(&__IPSBAR[0x100042]))
|
||||
|
||||
#define MCF_GPIO_PORTH (*(vuint8 *)(&__IPSBAR[0x100007]))
|
||||
#define MCF_GPIO_DDRH (*(vuint8 *)(&__IPSBAR[0x10001B]))
|
||||
#define MCF_GPIO_SETH (*(vuint8 *)(&__IPSBAR[0x10002F]))
|
||||
#define MCF_GPIO_CLRH (*(vuint8 *)(&__IPSBAR[0x100043]))
|
||||
|
||||
#define MCF_GPIO_PORTJ (*(vuint8 *)(&__IPSBAR[0x100008]))
|
||||
#define MCF_GPIO_DDRJ (*(vuint8 *)(&__IPSBAR[0x10001C]))
|
||||
#define MCF_GPIO_SETJ (*(vuint8 *)(&__IPSBAR[0x100030]))
|
||||
#define MCF_GPIO_CLRJ (*(vuint8 *)(&__IPSBAR[0x100044]))
|
||||
|
||||
#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100009]))
|
||||
#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10001D]))
|
||||
#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100031]))
|
||||
#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x100045]))
|
||||
|
||||
#define MCF_GPIO_PORTEH (*(vuint8 *)(&__IPSBAR[0x10000A]))
|
||||
#define MCF_GPIO_DDREH (*(vuint8 *)(&__IPSBAR[0x10001E]))
|
||||
#define MCF_GPIO_SETEH (*(vuint8 *)(&__IPSBAR[0x100032]))
|
||||
#define MCF_GPIO_CLREH (*(vuint8 *)(&__IPSBAR[0x100046]))
|
||||
|
||||
#define MCF_GPIO_PORTEL (*(vuint8 *)(&__IPSBAR[0x10000B]))
|
||||
#define MCF_GPIO_DDREL (*(vuint8 *)(&__IPSBAR[0x10001F]))
|
||||
#define MCF_GPIO_SETEL (*(vuint8 *)(&__IPSBAR[0x100033]))
|
||||
#define MCF_GPIO_CLREL (*(vuint8 *)(&__IPSBAR[0x100047]))
|
||||
|
||||
#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000C]))
|
||||
#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100020]))
|
||||
#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x100034]))
|
||||
#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100048]))
|
||||
|
||||
#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000D]))
|
||||
#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100021]))
|
||||
#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x100035]))
|
||||
#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100049]))
|
||||
|
||||
#define MCF_GPIO_PORTSD (*(vuint8 *)(&__IPSBAR[0x10000E]))
|
||||
#define MCF_GPIO_DDRSD (*(vuint8 *)(&__IPSBAR[0x100022]))
|
||||
#define MCF_GPIO_SETSD (*(vuint8 *)(&__IPSBAR[0x100036]))
|
||||
#define MCF_GPIO_CLRSD (*(vuint8 *)(&__IPSBAR[0x10004A]))
|
||||
|
||||
#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F]))
|
||||
#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100023]))
|
||||
#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x100037]))
|
||||
#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x10004B]))
|
||||
|
||||
#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010]))
|
||||
#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100024]))
|
||||
#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100038]))
|
||||
#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x10004C]))
|
||||
|
||||
#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011]))
|
||||
#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100025]))
|
||||
#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100039]))
|
||||
#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x10004D]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTA */
|
||||
#define MCF_GPIO_PORTA_PORTA0 (0x1)
|
||||
#define MCF_GPIO_PORTA_PORTA1 (0x2)
|
||||
#define MCF_GPIO_PORTA_PORTA2 (0x4)
|
||||
#define MCF_GPIO_PORTA_PORTA3 (0x8)
|
||||
#define MCF_GPIO_PORTA_PORTA4 (0x10)
|
||||
#define MCF_GPIO_PORTA_PORTA5 (0x20)
|
||||
#define MCF_GPIO_PORTA_PORTA6 (0x40)
|
||||
#define MCF_GPIO_PORTA_PORTA7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRA */
|
||||
#define MCF_GPIO_DDRA_DDRA0 (0x1)
|
||||
#define MCF_GPIO_DDRA_DDRA1 (0x2)
|
||||
#define MCF_GPIO_DDRA_DDRA2 (0x4)
|
||||
#define MCF_GPIO_DDRA_DDRA3 (0x8)
|
||||
#define MCF_GPIO_DDRA_DDRA4 (0x10)
|
||||
#define MCF_GPIO_DDRA_DDRA5 (0x20)
|
||||
#define MCF_GPIO_DDRA_DDRA6 (0x40)
|
||||
#define MCF_GPIO_DDRA_DDRA7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETA */
|
||||
#define MCF_GPIO_SETA_SETA0 (0x1)
|
||||
#define MCF_GPIO_SETA_SETA1 (0x2)
|
||||
#define MCF_GPIO_SETA_SETA2 (0x4)
|
||||
#define MCF_GPIO_SETA_SETA3 (0x8)
|
||||
#define MCF_GPIO_SETA_SETA4 (0x10)
|
||||
#define MCF_GPIO_SETA_SETA5 (0x20)
|
||||
#define MCF_GPIO_SETA_SETA6 (0x40)
|
||||
#define MCF_GPIO_SETA_SETA7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRA */
|
||||
#define MCF_GPIO_CLRA_CLRA0 (0x1)
|
||||
#define MCF_GPIO_CLRA_CLRA1 (0x2)
|
||||
#define MCF_GPIO_CLRA_CLRA2 (0x4)
|
||||
#define MCF_GPIO_CLRA_CLRA3 (0x8)
|
||||
#define MCF_GPIO_CLRA_CLRA4 (0x10)
|
||||
#define MCF_GPIO_CLRA_CLRA5 (0x20)
|
||||
#define MCF_GPIO_CLRA_CLRA6 (0x40)
|
||||
#define MCF_GPIO_CLRA_CLRA7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTB */
|
||||
#define MCF_GPIO_PORTB_PORTB0 (0x1)
|
||||
#define MCF_GPIO_PORTB_PORTB1 (0x2)
|
||||
#define MCF_GPIO_PORTB_PORTB2 (0x4)
|
||||
#define MCF_GPIO_PORTB_PORTB3 (0x8)
|
||||
#define MCF_GPIO_PORTB_PORTB4 (0x10)
|
||||
#define MCF_GPIO_PORTB_PORTB5 (0x20)
|
||||
#define MCF_GPIO_PORTB_PORTB6 (0x40)
|
||||
#define MCF_GPIO_PORTB_PORTB7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRB */
|
||||
#define MCF_GPIO_DDRB_DDRB0 (0x1)
|
||||
#define MCF_GPIO_DDRB_DDRB1 (0x2)
|
||||
#define MCF_GPIO_DDRB_DDRB2 (0x4)
|
||||
#define MCF_GPIO_DDRB_DDRB3 (0x8)
|
||||
#define MCF_GPIO_DDRB_DDRB4 (0x10)
|
||||
#define MCF_GPIO_DDRB_DDRB5 (0x20)
|
||||
#define MCF_GPIO_DDRB_DDRB6 (0x40)
|
||||
#define MCF_GPIO_DDRB_DDRB7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETB */
|
||||
#define MCF_GPIO_SETB_SETB0 (0x1)
|
||||
#define MCF_GPIO_SETB_SETB1 (0x2)
|
||||
#define MCF_GPIO_SETB_SETB2 (0x4)
|
||||
#define MCF_GPIO_SETB_SETB3 (0x8)
|
||||
#define MCF_GPIO_SETB_SETB4 (0x10)
|
||||
#define MCF_GPIO_SETB_SETB5 (0x20)
|
||||
#define MCF_GPIO_SETB_SETB6 (0x40)
|
||||
#define MCF_GPIO_SETB_SETB7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRB */
|
||||
#define MCF_GPIO_CLRB_CLRB0 (0x1)
|
||||
#define MCF_GPIO_CLRB_CLRB1 (0x2)
|
||||
#define MCF_GPIO_CLRB_CLRB2 (0x4)
|
||||
#define MCF_GPIO_CLRB_CLRB3 (0x8)
|
||||
#define MCF_GPIO_CLRB_CLRB4 (0x10)
|
||||
#define MCF_GPIO_CLRB_CLRB5 (0x20)
|
||||
#define MCF_GPIO_CLRB_CLRB6 (0x40)
|
||||
#define MCF_GPIO_CLRB_CLRB7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTC */
|
||||
#define MCF_GPIO_PORTC_PORTC0 (0x1)
|
||||
#define MCF_GPIO_PORTC_PORTC1 (0x2)
|
||||
#define MCF_GPIO_PORTC_PORTC2 (0x4)
|
||||
#define MCF_GPIO_PORTC_PORTC3 (0x8)
|
||||
#define MCF_GPIO_PORTC_PORTC4 (0x10)
|
||||
#define MCF_GPIO_PORTC_PORTC5 (0x20)
|
||||
#define MCF_GPIO_PORTC_PORTC6 (0x40)
|
||||
#define MCF_GPIO_PORTC_PORTC7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRC */
|
||||
#define MCF_GPIO_DDRC_DDRC0 (0x1)
|
||||
#define MCF_GPIO_DDRC_DDRC1 (0x2)
|
||||
#define MCF_GPIO_DDRC_DDRC2 (0x4)
|
||||
#define MCF_GPIO_DDRC_DDRC3 (0x8)
|
||||
#define MCF_GPIO_DDRC_DDRC4 (0x10)
|
||||
#define MCF_GPIO_DDRC_DDRC5 (0x20)
|
||||
#define MCF_GPIO_DDRC_DDRC6 (0x40)
|
||||
#define MCF_GPIO_DDRC_DDRC7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETC */
|
||||
#define MCF_GPIO_SETC_SETC0 (0x1)
|
||||
#define MCF_GPIO_SETC_SETC1 (0x2)
|
||||
#define MCF_GPIO_SETC_SETC2 (0x4)
|
||||
#define MCF_GPIO_SETC_SETC3 (0x8)
|
||||
#define MCF_GPIO_SETC_SETC4 (0x10)
|
||||
#define MCF_GPIO_SETC_SETC5 (0x20)
|
||||
#define MCF_GPIO_SETC_SETC6 (0x40)
|
||||
#define MCF_GPIO_SETC_SETC7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRC */
|
||||
#define MCF_GPIO_CLRC_CLRC0 (0x1)
|
||||
#define MCF_GPIO_CLRC_CLRC1 (0x2)
|
||||
#define MCF_GPIO_CLRC_CLRC2 (0x4)
|
||||
#define MCF_GPIO_CLRC_CLRC3 (0x8)
|
||||
#define MCF_GPIO_CLRC_CLRC4 (0x10)
|
||||
#define MCF_GPIO_CLRC_CLRC5 (0x20)
|
||||
#define MCF_GPIO_CLRC_CLRC6 (0x40)
|
||||
#define MCF_GPIO_CLRC_CLRC7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTD */
|
||||
#define MCF_GPIO_PORTD_PORTD0 (0x1)
|
||||
#define MCF_GPIO_PORTD_PORTD1 (0x2)
|
||||
#define MCF_GPIO_PORTD_PORTD2 (0x4)
|
||||
#define MCF_GPIO_PORTD_PORTD3 (0x8)
|
||||
#define MCF_GPIO_PORTD_PORTD4 (0x10)
|
||||
#define MCF_GPIO_PORTD_PORTD5 (0x20)
|
||||
#define MCF_GPIO_PORTD_PORTD6 (0x40)
|
||||
#define MCF_GPIO_PORTD_PORTD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRD */
|
||||
#define MCF_GPIO_DDRD_DDRD0 (0x1)
|
||||
#define MCF_GPIO_DDRD_DDRD1 (0x2)
|
||||
#define MCF_GPIO_DDRD_DDRD2 (0x4)
|
||||
#define MCF_GPIO_DDRD_DDRD3 (0x8)
|
||||
#define MCF_GPIO_DDRD_DDRD4 (0x10)
|
||||
#define MCF_GPIO_DDRD_DDRD5 (0x20)
|
||||
#define MCF_GPIO_DDRD_DDRD6 (0x40)
|
||||
#define MCF_GPIO_DDRD_DDRD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETD */
|
||||
#define MCF_GPIO_SETD_SETD0 (0x1)
|
||||
#define MCF_GPIO_SETD_SETD1 (0x2)
|
||||
#define MCF_GPIO_SETD_SETD2 (0x4)
|
||||
#define MCF_GPIO_SETD_SETD3 (0x8)
|
||||
#define MCF_GPIO_SETD_SETD4 (0x10)
|
||||
#define MCF_GPIO_SETD_SETD5 (0x20)
|
||||
#define MCF_GPIO_SETD_SETD6 (0x40)
|
||||
#define MCF_GPIO_SETD_SETD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRD */
|
||||
#define MCF_GPIO_CLRD_CLRD0 (0x1)
|
||||
#define MCF_GPIO_CLRD_CLRD1 (0x2)
|
||||
#define MCF_GPIO_CLRD_CLRD2 (0x4)
|
||||
#define MCF_GPIO_CLRD_CLRD3 (0x8)
|
||||
#define MCF_GPIO_CLRD_CLRD4 (0x10)
|
||||
#define MCF_GPIO_CLRD_CLRD5 (0x20)
|
||||
#define MCF_GPIO_CLRD_CLRD6 (0x40)
|
||||
#define MCF_GPIO_CLRD_CLRD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTE */
|
||||
#define MCF_GPIO_PORTE_PORTE0 (0x1)
|
||||
#define MCF_GPIO_PORTE_PORTE1 (0x2)
|
||||
#define MCF_GPIO_PORTE_PORTE2 (0x4)
|
||||
#define MCF_GPIO_PORTE_PORTE3 (0x8)
|
||||
#define MCF_GPIO_PORTE_PORTE4 (0x10)
|
||||
#define MCF_GPIO_PORTE_PORTE5 (0x20)
|
||||
#define MCF_GPIO_PORTE_PORTE6 (0x40)
|
||||
#define MCF_GPIO_PORTE_PORTE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRE */
|
||||
#define MCF_GPIO_DDRE_DDRE0 (0x1)
|
||||
#define MCF_GPIO_DDRE_DDRE1 (0x2)
|
||||
#define MCF_GPIO_DDRE_DDRE2 (0x4)
|
||||
#define MCF_GPIO_DDRE_DDRE3 (0x8)
|
||||
#define MCF_GPIO_DDRE_DDRE4 (0x10)
|
||||
#define MCF_GPIO_DDRE_DDRE5 (0x20)
|
||||
#define MCF_GPIO_DDRE_DDRE6 (0x40)
|
||||
#define MCF_GPIO_DDRE_DDRE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETE */
|
||||
#define MCF_GPIO_SETE_SETE0 (0x1)
|
||||
#define MCF_GPIO_SETE_SETE1 (0x2)
|
||||
#define MCF_GPIO_SETE_SETE2 (0x4)
|
||||
#define MCF_GPIO_SETE_SETE3 (0x8)
|
||||
#define MCF_GPIO_SETE_SETE4 (0x10)
|
||||
#define MCF_GPIO_SETE_SETE5 (0x20)
|
||||
#define MCF_GPIO_SETE_SETE6 (0x40)
|
||||
#define MCF_GPIO_SETE_SETE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRE */
|
||||
#define MCF_GPIO_CLRE_CLRE0 (0x1)
|
||||
#define MCF_GPIO_CLRE_CLRE1 (0x2)
|
||||
#define MCF_GPIO_CLRE_CLRE2 (0x4)
|
||||
#define MCF_GPIO_CLRE_CLRE3 (0x8)
|
||||
#define MCF_GPIO_CLRE_CLRE4 (0x10)
|
||||
#define MCF_GPIO_CLRE_CLRE5 (0x20)
|
||||
#define MCF_GPIO_CLRE_CLRE6 (0x40)
|
||||
#define MCF_GPIO_CLRE_CLRE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTF */
|
||||
#define MCF_GPIO_PORTF_PORTF0 (0x1)
|
||||
#define MCF_GPIO_PORTF_PORTF1 (0x2)
|
||||
#define MCF_GPIO_PORTF_PORTF2 (0x4)
|
||||
#define MCF_GPIO_PORTF_PORTF3 (0x8)
|
||||
#define MCF_GPIO_PORTF_PORTF4 (0x10)
|
||||
#define MCF_GPIO_PORTF_PORTF5 (0x20)
|
||||
#define MCF_GPIO_PORTF_PORTF6 (0x40)
|
||||
#define MCF_GPIO_PORTF_PORTF7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRF */
|
||||
#define MCF_GPIO_DDRF_DDRF0 (0x1)
|
||||
#define MCF_GPIO_DDRF_DDRF1 (0x2)
|
||||
#define MCF_GPIO_DDRF_DDRF2 (0x4)
|
||||
#define MCF_GPIO_DDRF_DDRF3 (0x8)
|
||||
#define MCF_GPIO_DDRF_DDRF4 (0x10)
|
||||
#define MCF_GPIO_DDRF_DDRF5 (0x20)
|
||||
#define MCF_GPIO_DDRF_DDRF6 (0x40)
|
||||
#define MCF_GPIO_DDRF_DDRF7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETF */
|
||||
#define MCF_GPIO_SETF_SETF0 (0x1)
|
||||
#define MCF_GPIO_SETF_SETF1 (0x2)
|
||||
#define MCF_GPIO_SETF_SETF2 (0x4)
|
||||
#define MCF_GPIO_SETF_SETF3 (0x8)
|
||||
#define MCF_GPIO_SETF_SETF4 (0x10)
|
||||
#define MCF_GPIO_SETF_SETF5 (0x20)
|
||||
#define MCF_GPIO_SETF_SETF6 (0x40)
|
||||
#define MCF_GPIO_SETF_SETF7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRF */
|
||||
#define MCF_GPIO_CLRF_CLRF0 (0x1)
|
||||
#define MCF_GPIO_CLRF_CLRF1 (0x2)
|
||||
#define MCF_GPIO_CLRF_CLRF2 (0x4)
|
||||
#define MCF_GPIO_CLRF_CLRF3 (0x8)
|
||||
#define MCF_GPIO_CLRF_CLRF4 (0x10)
|
||||
#define MCF_GPIO_CLRF_CLRF5 (0x20)
|
||||
#define MCF_GPIO_CLRF_CLRF6 (0x40)
|
||||
#define MCF_GPIO_CLRF_CLRF7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTG */
|
||||
#define MCF_GPIO_PORTG_PORTG0 (0x1)
|
||||
#define MCF_GPIO_PORTG_PORTG1 (0x2)
|
||||
#define MCF_GPIO_PORTG_PORTG2 (0x4)
|
||||
#define MCF_GPIO_PORTG_PORTG3 (0x8)
|
||||
#define MCF_GPIO_PORTG_PORTG4 (0x10)
|
||||
#define MCF_GPIO_PORTG_PORTG5 (0x20)
|
||||
#define MCF_GPIO_PORTG_PORTG6 (0x40)
|
||||
#define MCF_GPIO_PORTG_PORTG7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRG */
|
||||
#define MCF_GPIO_DDRG_DDRG0 (0x1)
|
||||
#define MCF_GPIO_DDRG_DDRG1 (0x2)
|
||||
#define MCF_GPIO_DDRG_DDRG2 (0x4)
|
||||
#define MCF_GPIO_DDRG_DDRG3 (0x8)
|
||||
#define MCF_GPIO_DDRG_DDRG4 (0x10)
|
||||
#define MCF_GPIO_DDRG_DDRG5 (0x20)
|
||||
#define MCF_GPIO_DDRG_DDRG6 (0x40)
|
||||
#define MCF_GPIO_DDRG_DDRG7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETG */
|
||||
#define MCF_GPIO_SETG_SETG0 (0x1)
|
||||
#define MCF_GPIO_SETG_SETG1 (0x2)
|
||||
#define MCF_GPIO_SETG_SETG2 (0x4)
|
||||
#define MCF_GPIO_SETG_SETG3 (0x8)
|
||||
#define MCF_GPIO_SETG_SETG4 (0x10)
|
||||
#define MCF_GPIO_SETG_SETG5 (0x20)
|
||||
#define MCF_GPIO_SETG_SETG6 (0x40)
|
||||
#define MCF_GPIO_SETG_SETG7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRG */
|
||||
#define MCF_GPIO_CLRG_CLRG0 (0x1)
|
||||
#define MCF_GPIO_CLRG_CLRG1 (0x2)
|
||||
#define MCF_GPIO_CLRG_CLRG2 (0x4)
|
||||
#define MCF_GPIO_CLRG_CLRG3 (0x8)
|
||||
#define MCF_GPIO_CLRG_CLRG4 (0x10)
|
||||
#define MCF_GPIO_CLRG_CLRG5 (0x20)
|
||||
#define MCF_GPIO_CLRG_CLRG6 (0x40)
|
||||
#define MCF_GPIO_CLRG_CLRG7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTH */
|
||||
#define MCF_GPIO_PORTH_PORTH0 (0x1)
|
||||
#define MCF_GPIO_PORTH_PORTH1 (0x2)
|
||||
#define MCF_GPIO_PORTH_PORTH2 (0x4)
|
||||
#define MCF_GPIO_PORTH_PORTH3 (0x8)
|
||||
#define MCF_GPIO_PORTH_PORTH4 (0x10)
|
||||
#define MCF_GPIO_PORTH_PORTH5 (0x20)
|
||||
#define MCF_GPIO_PORTH_PORTH6 (0x40)
|
||||
#define MCF_GPIO_PORTH_PORTH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRH */
|
||||
#define MCF_GPIO_DDRH_DDRH0 (0x1)
|
||||
#define MCF_GPIO_DDRH_DDRH1 (0x2)
|
||||
#define MCF_GPIO_DDRH_DDRH2 (0x4)
|
||||
#define MCF_GPIO_DDRH_DDRH3 (0x8)
|
||||
#define MCF_GPIO_DDRH_DDRH4 (0x10)
|
||||
#define MCF_GPIO_DDRH_DDRH5 (0x20)
|
||||
#define MCF_GPIO_DDRH_DDRH6 (0x40)
|
||||
#define MCF_GPIO_DDRH_DDRH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETH */
|
||||
#define MCF_GPIO_SETH_SETH0 (0x1)
|
||||
#define MCF_GPIO_SETH_SETH1 (0x2)
|
||||
#define MCF_GPIO_SETH_SETH2 (0x4)
|
||||
#define MCF_GPIO_SETH_SETH3 (0x8)
|
||||
#define MCF_GPIO_SETH_SETH4 (0x10)
|
||||
#define MCF_GPIO_SETH_SETH5 (0x20)
|
||||
#define MCF_GPIO_SETH_SETH6 (0x40)
|
||||
#define MCF_GPIO_SETH_SETH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRH */
|
||||
#define MCF_GPIO_CLRH_CLRH0 (0x1)
|
||||
#define MCF_GPIO_CLRH_CLRH1 (0x2)
|
||||
#define MCF_GPIO_CLRH_CLRH2 (0x4)
|
||||
#define MCF_GPIO_CLRH_CLRH3 (0x8)
|
||||
#define MCF_GPIO_CLRH_CLRH4 (0x10)
|
||||
#define MCF_GPIO_CLRH_CLRH5 (0x20)
|
||||
#define MCF_GPIO_CLRH_CLRH6 (0x40)
|
||||
#define MCF_GPIO_CLRH_CLRH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTJ */
|
||||
#define MCF_GPIO_PORTJ_PORTJ0 (0x1)
|
||||
#define MCF_GPIO_PORTJ_PORTJ1 (0x2)
|
||||
#define MCF_GPIO_PORTJ_PORTJ2 (0x4)
|
||||
#define MCF_GPIO_PORTJ_PORTJ3 (0x8)
|
||||
#define MCF_GPIO_PORTJ_PORTJ4 (0x10)
|
||||
#define MCF_GPIO_PORTJ_PORTJ5 (0x20)
|
||||
#define MCF_GPIO_PORTJ_PORTJ6 (0x40)
|
||||
#define MCF_GPIO_PORTJ_PORTJ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRJ */
|
||||
#define MCF_GPIO_DDRJ_DDRJ0 (0x1)
|
||||
#define MCF_GPIO_DDRJ_DDRJ1 (0x2)
|
||||
#define MCF_GPIO_DDRJ_DDRJ2 (0x4)
|
||||
#define MCF_GPIO_DDRJ_DDRJ3 (0x8)
|
||||
#define MCF_GPIO_DDRJ_DDRJ4 (0x10)
|
||||
#define MCF_GPIO_DDRJ_DDRJ5 (0x20)
|
||||
#define MCF_GPIO_DDRJ_DDRJ6 (0x40)
|
||||
#define MCF_GPIO_DDRJ_DDRJ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETJ */
|
||||
#define MCF_GPIO_SETJ_SETJ0 (0x1)
|
||||
#define MCF_GPIO_SETJ_SETJ1 (0x2)
|
||||
#define MCF_GPIO_SETJ_SETJ2 (0x4)
|
||||
#define MCF_GPIO_SETJ_SETJ3 (0x8)
|
||||
#define MCF_GPIO_SETJ_SETJ4 (0x10)
|
||||
#define MCF_GPIO_SETJ_SETJ5 (0x20)
|
||||
#define MCF_GPIO_SETJ_SETJ6 (0x40)
|
||||
#define MCF_GPIO_SETJ_SETJ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRJ */
|
||||
#define MCF_GPIO_CLRJ_CLRJ0 (0x1)
|
||||
#define MCF_GPIO_CLRJ_CLRJ1 (0x2)
|
||||
#define MCF_GPIO_CLRJ_CLRJ2 (0x4)
|
||||
#define MCF_GPIO_CLRJ_CLRJ3 (0x8)
|
||||
#define MCF_GPIO_CLRJ_CLRJ4 (0x10)
|
||||
#define MCF_GPIO_CLRJ_CLRJ5 (0x20)
|
||||
#define MCF_GPIO_CLRJ_CLRJ6 (0x40)
|
||||
#define MCF_GPIO_CLRJ_CLRJ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTDD */
|
||||
#define MCF_GPIO_PORTDD_PORTDD0 (0x1)
|
||||
#define MCF_GPIO_PORTDD_PORTDD1 (0x2)
|
||||
#define MCF_GPIO_PORTDD_PORTDD2 (0x4)
|
||||
#define MCF_GPIO_PORTDD_PORTDD3 (0x8)
|
||||
#define MCF_GPIO_PORTDD_PORTDD4 (0x10)
|
||||
#define MCF_GPIO_PORTDD_PORTDD5 (0x20)
|
||||
#define MCF_GPIO_PORTDD_PORTDD6 (0x40)
|
||||
#define MCF_GPIO_PORTDD_PORTDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRDD */
|
||||
#define MCF_GPIO_DDRDD_DDRDD0 (0x1)
|
||||
#define MCF_GPIO_DDRDD_DDRDD1 (0x2)
|
||||
#define MCF_GPIO_DDRDD_DDRDD2 (0x4)
|
||||
#define MCF_GPIO_DDRDD_DDRDD3 (0x8)
|
||||
#define MCF_GPIO_DDRDD_DDRDD4 (0x10)
|
||||
#define MCF_GPIO_DDRDD_DDRDD5 (0x20)
|
||||
#define MCF_GPIO_DDRDD_DDRDD6 (0x40)
|
||||
#define MCF_GPIO_DDRDD_DDRDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETDD */
|
||||
#define MCF_GPIO_SETDD_SETDD0 (0x1)
|
||||
#define MCF_GPIO_SETDD_SETDD1 (0x2)
|
||||
#define MCF_GPIO_SETDD_SETDD2 (0x4)
|
||||
#define MCF_GPIO_SETDD_SETDD3 (0x8)
|
||||
#define MCF_GPIO_SETDD_SETDD4 (0x10)
|
||||
#define MCF_GPIO_SETDD_SETDD5 (0x20)
|
||||
#define MCF_GPIO_SETDD_SETDD6 (0x40)
|
||||
#define MCF_GPIO_SETDD_SETDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRDD */
|
||||
#define MCF_GPIO_CLRDD_CLRDD0 (0x1)
|
||||
#define MCF_GPIO_CLRDD_CLRDD1 (0x2)
|
||||
#define MCF_GPIO_CLRDD_CLRDD2 (0x4)
|
||||
#define MCF_GPIO_CLRDD_CLRDD3 (0x8)
|
||||
#define MCF_GPIO_CLRDD_CLRDD4 (0x10)
|
||||
#define MCF_GPIO_CLRDD_CLRDD5 (0x20)
|
||||
#define MCF_GPIO_CLRDD_CLRDD6 (0x40)
|
||||
#define MCF_GPIO_CLRDD_CLRDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTEH */
|
||||
#define MCF_GPIO_PORTEH_PORTEH0 (0x1)
|
||||
#define MCF_GPIO_PORTEH_PORTEH1 (0x2)
|
||||
#define MCF_GPIO_PORTEH_PORTEH2 (0x4)
|
||||
#define MCF_GPIO_PORTEH_PORTEH3 (0x8)
|
||||
#define MCF_GPIO_PORTEH_PORTEH4 (0x10)
|
||||
#define MCF_GPIO_PORTEH_PORTEH5 (0x20)
|
||||
#define MCF_GPIO_PORTEH_PORTEH6 (0x40)
|
||||
#define MCF_GPIO_PORTEH_PORTEH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDREH */
|
||||
#define MCF_GPIO_DDREH_DDREH0 (0x1)
|
||||
#define MCF_GPIO_DDREH_DDREH1 (0x2)
|
||||
#define MCF_GPIO_DDREH_DDREH2 (0x4)
|
||||
#define MCF_GPIO_DDREH_DDREH3 (0x8)
|
||||
#define MCF_GPIO_DDREH_DDREH4 (0x10)
|
||||
#define MCF_GPIO_DDREH_DDREH5 (0x20)
|
||||
#define MCF_GPIO_DDREH_DDREH6 (0x40)
|
||||
#define MCF_GPIO_DDREH_DDREH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETEH */
|
||||
#define MCF_GPIO_SETEH_SETEH0 (0x1)
|
||||
#define MCF_GPIO_SETEH_SETEH1 (0x2)
|
||||
#define MCF_GPIO_SETEH_SETEH2 (0x4)
|
||||
#define MCF_GPIO_SETEH_SETEH3 (0x8)
|
||||
#define MCF_GPIO_SETEH_SETEH4 (0x10)
|
||||
#define MCF_GPIO_SETEH_SETEH5 (0x20)
|
||||
#define MCF_GPIO_SETEH_SETEH6 (0x40)
|
||||
#define MCF_GPIO_SETEH_SETEH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLREH */
|
||||
#define MCF_GPIO_CLREH_CLREH0 (0x1)
|
||||
#define MCF_GPIO_CLREH_CLREH1 (0x2)
|
||||
#define MCF_GPIO_CLREH_CLREH2 (0x4)
|
||||
#define MCF_GPIO_CLREH_CLREH3 (0x8)
|
||||
#define MCF_GPIO_CLREH_CLREH4 (0x10)
|
||||
#define MCF_GPIO_CLREH_CLREH5 (0x20)
|
||||
#define MCF_GPIO_CLREH_CLREH6 (0x40)
|
||||
#define MCF_GPIO_CLREH_CLREH7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTEL */
|
||||
#define MCF_GPIO_PORTEL_PORTEL0 (0x1)
|
||||
#define MCF_GPIO_PORTEL_PORTEL1 (0x2)
|
||||
#define MCF_GPIO_PORTEL_PORTEL2 (0x4)
|
||||
#define MCF_GPIO_PORTEL_PORTEL3 (0x8)
|
||||
#define MCF_GPIO_PORTEL_PORTEL4 (0x10)
|
||||
#define MCF_GPIO_PORTEL_PORTEL5 (0x20)
|
||||
#define MCF_GPIO_PORTEL_PORTEL6 (0x40)
|
||||
#define MCF_GPIO_PORTEL_PORTEL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDREL */
|
||||
#define MCF_GPIO_DDREL_DDREL0 (0x1)
|
||||
#define MCF_GPIO_DDREL_DDREL1 (0x2)
|
||||
#define MCF_GPIO_DDREL_DDREL2 (0x4)
|
||||
#define MCF_GPIO_DDREL_DDREL3 (0x8)
|
||||
#define MCF_GPIO_DDREL_DDREL4 (0x10)
|
||||
#define MCF_GPIO_DDREL_DDREL5 (0x20)
|
||||
#define MCF_GPIO_DDREL_DDREL6 (0x40)
|
||||
#define MCF_GPIO_DDREL_DDREL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETEL */
|
||||
#define MCF_GPIO_SETEL_SETEL0 (0x1)
|
||||
#define MCF_GPIO_SETEL_SETEL1 (0x2)
|
||||
#define MCF_GPIO_SETEL_SETEL2 (0x4)
|
||||
#define MCF_GPIO_SETEL_SETEL3 (0x8)
|
||||
#define MCF_GPIO_SETEL_SETEL4 (0x10)
|
||||
#define MCF_GPIO_SETEL_SETEL5 (0x20)
|
||||
#define MCF_GPIO_SETEL_SETEL6 (0x40)
|
||||
#define MCF_GPIO_SETEL_SETEL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLREL */
|
||||
#define MCF_GPIO_CLREL_CLREL0 (0x1)
|
||||
#define MCF_GPIO_CLREL_CLREL1 (0x2)
|
||||
#define MCF_GPIO_CLREL_CLREL2 (0x4)
|
||||
#define MCF_GPIO_CLREL_CLREL3 (0x8)
|
||||
#define MCF_GPIO_CLREL_CLREL4 (0x10)
|
||||
#define MCF_GPIO_CLREL_CLREL5 (0x20)
|
||||
#define MCF_GPIO_CLREL_CLREL6 (0x40)
|
||||
#define MCF_GPIO_CLREL_CLREL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTAS */
|
||||
#define MCF_GPIO_PORTAS_PORTAS0 (0x1)
|
||||
#define MCF_GPIO_PORTAS_PORTAS1 (0x2)
|
||||
#define MCF_GPIO_PORTAS_PORTAS2 (0x4)
|
||||
#define MCF_GPIO_PORTAS_PORTAS3 (0x8)
|
||||
#define MCF_GPIO_PORTAS_PORTAS4 (0x10)
|
||||
#define MCF_GPIO_PORTAS_PORTAS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRAS */
|
||||
#define MCF_GPIO_DDRAS_DDRAS0 (0x1)
|
||||
#define MCF_GPIO_DDRAS_DDRAS1 (0x2)
|
||||
#define MCF_GPIO_DDRAS_DDRAS2 (0x4)
|
||||
#define MCF_GPIO_DDRAS_DDRAS3 (0x8)
|
||||
#define MCF_GPIO_DDRAS_DDRAS4 (0x10)
|
||||
#define MCF_GPIO_DDRAS_DDRAS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETAS */
|
||||
#define MCF_GPIO_SETAS_SETAS0 (0x1)
|
||||
#define MCF_GPIO_SETAS_SETAS1 (0x2)
|
||||
#define MCF_GPIO_SETAS_SETAS2 (0x4)
|
||||
#define MCF_GPIO_SETAS_SETAS3 (0x8)
|
||||
#define MCF_GPIO_SETAS_SETAS4 (0x10)
|
||||
#define MCF_GPIO_SETAS_SETAS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRAS */
|
||||
#define MCF_GPIO_CLRAS_CLRAS0 (0x1)
|
||||
#define MCF_GPIO_CLRAS_CLRAS1 (0x2)
|
||||
#define MCF_GPIO_CLRAS_CLRAS2 (0x4)
|
||||
#define MCF_GPIO_CLRAS_CLRAS3 (0x8)
|
||||
#define MCF_GPIO_CLRAS_CLRAS4 (0x10)
|
||||
#define MCF_GPIO_CLRAS_CLRAS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTQS */
|
||||
#define MCF_GPIO_PORTQS_PORTQS0 (0x1)
|
||||
#define MCF_GPIO_PORTQS_PORTQS1 (0x2)
|
||||
#define MCF_GPIO_PORTQS_PORTQS2 (0x4)
|
||||
#define MCF_GPIO_PORTQS_PORTQS3 (0x8)
|
||||
#define MCF_GPIO_PORTQS_PORTQS4 (0x10)
|
||||
#define MCF_GPIO_PORTQS_PORTQS5 (0x20)
|
||||
#define MCF_GPIO_PORTQS_PORTQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRQS */
|
||||
#define MCF_GPIO_DDRQS_DDRQS0 (0x1)
|
||||
#define MCF_GPIO_DDRQS_DDRQS1 (0x2)
|
||||
#define MCF_GPIO_DDRQS_DDRQS2 (0x4)
|
||||
#define MCF_GPIO_DDRQS_DDRQS3 (0x8)
|
||||
#define MCF_GPIO_DDRQS_DDRQS4 (0x10)
|
||||
#define MCF_GPIO_DDRQS_DDRQS5 (0x20)
|
||||
#define MCF_GPIO_DDRQS_DDRQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETQS */
|
||||
#define MCF_GPIO_SETQS_SETQS0 (0x1)
|
||||
#define MCF_GPIO_SETQS_SETQS1 (0x2)
|
||||
#define MCF_GPIO_SETQS_SETQS2 (0x4)
|
||||
#define MCF_GPIO_SETQS_SETQS3 (0x8)
|
||||
#define MCF_GPIO_SETQS_SETQS4 (0x10)
|
||||
#define MCF_GPIO_SETQS_SETQS5 (0x20)
|
||||
#define MCF_GPIO_SETQS_SETQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRQS */
|
||||
#define MCF_GPIO_CLRQS_CLRQS0 (0x1)
|
||||
#define MCF_GPIO_CLRQS_CLRQS1 (0x2)
|
||||
#define MCF_GPIO_CLRQS_CLRQS2 (0x4)
|
||||
#define MCF_GPIO_CLRQS_CLRQS3 (0x8)
|
||||
#define MCF_GPIO_CLRQS_CLRQS4 (0x10)
|
||||
#define MCF_GPIO_CLRQS_CLRQS5 (0x20)
|
||||
#define MCF_GPIO_CLRQS_CLRQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTSD */
|
||||
#define MCF_GPIO_PORTSD_PORTSD0 (0x1)
|
||||
#define MCF_GPIO_PORTSD_PORTSD1 (0x2)
|
||||
#define MCF_GPIO_PORTSD_PORTSD2 (0x4)
|
||||
#define MCF_GPIO_PORTSD_PORTSD3 (0x8)
|
||||
#define MCF_GPIO_PORTSD_PORTSD4 (0x10)
|
||||
#define MCF_GPIO_PORTSD_PORTSD5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRSD */
|
||||
#define MCF_GPIO_DDRSD_DDRSD0 (0x1)
|
||||
#define MCF_GPIO_DDRSD_DDRSD1 (0x2)
|
||||
#define MCF_GPIO_DDRSD_DDRSD2 (0x4)
|
||||
#define MCF_GPIO_DDRSD_DDRSD3 (0x8)
|
||||
#define MCF_GPIO_DDRSD_DDRSD4 (0x10)
|
||||
#define MCF_GPIO_DDRSD_DDRSD5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETSD */
|
||||
#define MCF_GPIO_SETSD_SETSD0 (0x1)
|
||||
#define MCF_GPIO_SETSD_SETSD1 (0x2)
|
||||
#define MCF_GPIO_SETSD_SETSD2 (0x4)
|
||||
#define MCF_GPIO_SETSD_SETSD3 (0x8)
|
||||
#define MCF_GPIO_SETSD_SETSD4 (0x10)
|
||||
#define MCF_GPIO_SETSD_SETSD5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRSD */
|
||||
#define MCF_GPIO_CLRSD_CLRSD0 (0x1)
|
||||
#define MCF_GPIO_CLRSD_CLRSD1 (0x2)
|
||||
#define MCF_GPIO_CLRSD_CLRSD2 (0x4)
|
||||
#define MCF_GPIO_CLRSD_CLRSD3 (0x8)
|
||||
#define MCF_GPIO_CLRSD_CLRSD4 (0x10)
|
||||
#define MCF_GPIO_CLRSD_CLRSD5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTTC */
|
||||
#define MCF_GPIO_PORTTC_PORTTC0 (0x1)
|
||||
#define MCF_GPIO_PORTTC_PORTTC1 (0x2)
|
||||
#define MCF_GPIO_PORTTC_PORTTC2 (0x4)
|
||||
#define MCF_GPIO_PORTTC_PORTTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRTC */
|
||||
#define MCF_GPIO_DDRTC_DDRTC0 (0x1)
|
||||
#define MCF_GPIO_DDRTC_DDRTC1 (0x2)
|
||||
#define MCF_GPIO_DDRTC_DDRTC2 (0x4)
|
||||
#define MCF_GPIO_DDRTC_DDRTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETTC */
|
||||
#define MCF_GPIO_SETTC_SETTC0 (0x1)
|
||||
#define MCF_GPIO_SETTC_SETTC1 (0x2)
|
||||
#define MCF_GPIO_SETTC_SETTC2 (0x4)
|
||||
#define MCF_GPIO_SETTC_SETTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRTC */
|
||||
#define MCF_GPIO_CLRTC_CLRTC0 (0x1)
|
||||
#define MCF_GPIO_CLRTC_CLRTC1 (0x2)
|
||||
#define MCF_GPIO_CLRTC_CLRTC2 (0x4)
|
||||
#define MCF_GPIO_CLRTC_CLRTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTTD */
|
||||
#define MCF_GPIO_PORTTD_PORTTD0 (0x1)
|
||||
#define MCF_GPIO_PORTTD_PORTTD1 (0x2)
|
||||
#define MCF_GPIO_PORTTD_PORTTD2 (0x4)
|
||||
#define MCF_GPIO_PORTTD_PORTTD3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRTD */
|
||||
#define MCF_GPIO_DDRTD_DDRTD0 (0x1)
|
||||
#define MCF_GPIO_DDRTD_DDRTD1 (0x2)
|
||||
#define MCF_GPIO_DDRTD_DDRTD2 (0x4)
|
||||
#define MCF_GPIO_DDRTD_DDRTD3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETTD */
|
||||
#define MCF_GPIO_SETTD_SETTD0 (0x1)
|
||||
#define MCF_GPIO_SETTD_SETTD1 (0x2)
|
||||
#define MCF_GPIO_SETTD_SETTD2 (0x4)
|
||||
#define MCF_GPIO_SETTD_SETTD3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRTD */
|
||||
#define MCF_GPIO_CLRTD_CLRTD0 (0x1)
|
||||
#define MCF_GPIO_CLRTD_CLRTD1 (0x2)
|
||||
#define MCF_GPIO_CLRTD_CLRTD2 (0x4)
|
||||
#define MCF_GPIO_CLRTD_CLRTD3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTUA */
|
||||
#define MCF_GPIO_PORTUA_PORTUA0 (0x1)
|
||||
#define MCF_GPIO_PORTUA_PORTUA1 (0x2)
|
||||
#define MCF_GPIO_PORTUA_PORTUA2 (0x4)
|
||||
#define MCF_GPIO_PORTUA_PORTUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRUA */
|
||||
#define MCF_GPIO_DDRUA_DDRUA0 (0x1)
|
||||
#define MCF_GPIO_DDRUA_DDRUA1 (0x2)
|
||||
#define MCF_GPIO_DDRUA_DDRUA2 (0x4)
|
||||
#define MCF_GPIO_DDRUA_DDRUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETUA */
|
||||
#define MCF_GPIO_SETUA_SETUA0 (0x1)
|
||||
#define MCF_GPIO_SETUA_SETUA1 (0x2)
|
||||
#define MCF_GPIO_SETUA_SETUA2 (0x4)
|
||||
#define MCF_GPIO_SETUA_SETUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRUA */
|
||||
#define MCF_GPIO_CLRUA_CLRUA0 (0x1)
|
||||
#define MCF_GPIO_CLRUA_CLRUA1 (0x2)
|
||||
#define MCF_GPIO_CLRUA_CLRUA2 (0x4)
|
||||
#define MCF_GPIO_CLRUA_CLRUA3 (0x8)
|
||||
|
||||
|
||||
#endif /* __MCF5282_GPIO_H__ */
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_GPTA_H__
|
||||
#define __MCF5282_GPTA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose Timer Module (GPT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPTA_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000]))
|
||||
#define MCF_GPTA_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001]))
|
||||
#define MCF_GPTA_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002]))
|
||||
#define MCF_GPTA_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003]))
|
||||
#define MCF_GPTA_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004]))
|
||||
#define MCF_GPTA_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006]))
|
||||
#define MCF_GPTA_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008]))
|
||||
#define MCF_GPTA_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009]))
|
||||
#define MCF_GPTA_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B]))
|
||||
#define MCF_GPTA_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C]))
|
||||
#define MCF_GPTA_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D]))
|
||||
#define MCF_GPTA_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E]))
|
||||
#define MCF_GPTA_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F]))
|
||||
#define MCF_GPTA_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010]))
|
||||
#define MCF_GPTA_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012]))
|
||||
#define MCF_GPTA_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014]))
|
||||
#define MCF_GPTA_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016]))
|
||||
#define MCF_GPTA_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018]))
|
||||
#define MCF_GPTA_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019]))
|
||||
#define MCF_GPTA_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A]))
|
||||
#define MCF_GPTA_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D]))
|
||||
#define MCF_GPTA_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E]))
|
||||
#define MCF_GPTA_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010 + ((x)*0x2)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTIOS */
|
||||
#define MCF_GPTA_GPTIOS_IOS0 (0x1)
|
||||
#define MCF_GPTA_GPTIOS_IOS1 (0x2)
|
||||
#define MCF_GPTA_GPTIOS_IOS2 (0x4)
|
||||
#define MCF_GPTA_GPTIOS_IOS3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCFORC */
|
||||
#define MCF_GPTA_GPTCFORC_FOC0 (0x1)
|
||||
#define MCF_GPTA_GPTCFORC_FOC1 (0x2)
|
||||
#define MCF_GPTA_GPTCFORC_FOC2 (0x4)
|
||||
#define MCF_GPTA_GPTCFORC_FOC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTOC3M */
|
||||
#define MCF_GPTA_GPTOC3M_OC3M0 (0x1)
|
||||
#define MCF_GPTA_GPTOC3M_OC3M1 (0x2)
|
||||
#define MCF_GPTA_GPTOC3M_OC3M2 (0x4)
|
||||
#define MCF_GPTA_GPTOC3M_OC3M3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTOC3D */
|
||||
#define MCF_GPTA_GPTOC3D_OC3D0 (0x1)
|
||||
#define MCF_GPTA_GPTOC3D_OC3D1 (0x2)
|
||||
#define MCF_GPTA_GPTOC3D_OC3D2 (0x4)
|
||||
#define MCF_GPTA_GPTOC3D_OC3D3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCNT */
|
||||
#define MCF_GPTA_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTSCR1 */
|
||||
#define MCF_GPTA_GPTSCR1_TFFCA (0x10)
|
||||
#define MCF_GPTA_GPTSCR1_GPTEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTTOV */
|
||||
#define MCF_GPTA_GPTTOV_TOV0 (0x1)
|
||||
#define MCF_GPTA_GPTTOV_TOV1 (0x2)
|
||||
#define MCF_GPTA_GPTTOV_TOV2 (0x4)
|
||||
#define MCF_GPTA_GPTTOV_TOV3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCTL1 */
|
||||
#define MCF_GPTA_GPTCTL1_OL0 (0x1)
|
||||
#define MCF_GPTA_GPTCTL1_OM0 (0x2)
|
||||
#define MCF_GPTA_GPTCTL1_OL1 (0x4)
|
||||
#define MCF_GPTA_GPTCTL1_OM1 (0x8)
|
||||
#define MCF_GPTA_GPTCTL1_OL2 (0x10)
|
||||
#define MCF_GPTA_GPTCTL1_OM2 (0x20)
|
||||
#define MCF_GPTA_GPTCTL1_OL3 (0x40)
|
||||
#define MCF_GPTA_GPTCTL1_OM3 (0x80)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_TOGGLE (0x1)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_CLEAR (0x2)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_SET (0x3)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_TOGGLE (0x4)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_CLEAR (0x8)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_SET (0xC)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_TOGGLE (0x10)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_CLEAR (0x20)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_SET (0x30)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_TOGGLE (0x40)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_CLEAR (0x80)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_SET (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCTL2 */
|
||||
#define MCF_GPTA_GPTCTL2_EDG0A (0x1)
|
||||
#define MCF_GPTA_GPTCTL2_EDG0B (0x2)
|
||||
#define MCF_GPTA_GPTCTL2_EDG1A (0x4)
|
||||
#define MCF_GPTA_GPTCTL2_EDG1B (0x8)
|
||||
#define MCF_GPTA_GPTCTL2_EDG2A (0x10)
|
||||
#define MCF_GPTA_GPTCTL2_EDG2B (0x20)
|
||||
#define MCF_GPTA_GPTCTL2_EDG3A (0x40)
|
||||
#define MCF_GPTA_GPTCTL2_EDG3B (0x80)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_RISING (0x1)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_FALLING (0x2)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_ANY (0x3)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_RISING (0x4)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_FALLING (0x8)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_ANY (0xC)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_RISING (0x10)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_FALLING (0x20)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_ANY (0x30)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_RISING (0x40)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_FALLING (0x80)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_ANY (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTIE */
|
||||
#define MCF_GPTA_GPTIE_CI0 (0x1)
|
||||
#define MCF_GPTA_GPTIE_CI1 (0x2)
|
||||
#define MCF_GPTA_GPTIE_CI2 (0x4)
|
||||
#define MCF_GPTA_GPTIE_CI3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTSCR2 */
|
||||
#define MCF_GPTA_GPTSCR2_PR(x) (((x)&0x7)<<0)
|
||||
#define MCF_GPTA_GPTSCR2_PR_1 (0)
|
||||
#define MCF_GPTA_GPTSCR2_PR_2 (0x1)
|
||||
#define MCF_GPTA_GPTSCR2_PR_4 (0x2)
|
||||
#define MCF_GPTA_GPTSCR2_PR_8 (0x3)
|
||||
#define MCF_GPTA_GPTSCR2_PR_16 (0x4)
|
||||
#define MCF_GPTA_GPTSCR2_PR_32 (0x5)
|
||||
#define MCF_GPTA_GPTSCR2_PR_64 (0x6)
|
||||
#define MCF_GPTA_GPTSCR2_PR_128 (0x7)
|
||||
#define MCF_GPTA_GPTSCR2_TCRE (0x8)
|
||||
#define MCF_GPTA_GPTSCR2_RDPT (0x10)
|
||||
#define MCF_GPTA_GPTSCR2_PUPT (0x20)
|
||||
#define MCF_GPTA_GPTSCR2_TOI (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTFLG1 */
|
||||
#define MCF_GPTA_GPTFLG1_CF0 (0x1)
|
||||
#define MCF_GPTA_GPTFLG1_CF1 (0x2)
|
||||
#define MCF_GPTA_GPTFLG1_CF2 (0x4)
|
||||
#define MCF_GPTA_GPTFLG1_CF3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTFLG2 */
|
||||
#define MCF_GPTA_GPTFLG2_TOF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTC */
|
||||
#define MCF_GPTA_GPTC_CCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPACTL */
|
||||
#define MCF_GPTA_GPTPACTL_PAI (0x1)
|
||||
#define MCF_GPTA_GPTPACTL_PAOVI (0x2)
|
||||
#define MCF_GPTA_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_GPTPR (0)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_PACLK (0x1)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_PACLK_256 (0x2)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_PACLK_65536 (0x3)
|
||||
#define MCF_GPTA_GPTPACTL_PEDGE (0x10)
|
||||
#define MCF_GPTA_GPTPACTL_PAMOD (0x20)
|
||||
#define MCF_GPTA_GPTPACTL_PAE (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPAFLG */
|
||||
#define MCF_GPTA_GPTPAFLG_PAIF (0x1)
|
||||
#define MCF_GPTA_GPTPAFLG_PAOVF (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPACNT */
|
||||
#define MCF_GPTA_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPORT */
|
||||
#define MCF_GPTA_GPTPORT_PORTT0 (0x1)
|
||||
#define MCF_GPTA_GPTPORT_PORTT1 (0x2)
|
||||
#define MCF_GPTA_GPTPORT_PORTT2 (0x4)
|
||||
#define MCF_GPTA_GPTPORT_PORTT3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTDDR */
|
||||
#define MCF_GPTA_GPTDDR_DDRT0 (0x1)
|
||||
#define MCF_GPTA_GPTDDR_DDRT1 (0x2)
|
||||
#define MCF_GPTA_GPTDDR_DDRT2 (0x4)
|
||||
#define MCF_GPTA_GPTDDR_DDRT3 (0x8)
|
||||
|
||||
|
||||
#endif /* __MCF5282_GPTA_H__ */
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_GPTB_H__
|
||||
#define __MCF5282_GPTB_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose Timer Module (GPT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPTB_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1B0000]))
|
||||
#define MCF_GPTB_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1B0001]))
|
||||
#define MCF_GPTB_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1B0002]))
|
||||
#define MCF_GPTB_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1B0003]))
|
||||
#define MCF_GPTB_GPTCNT (*(vuint16*)(&__IPSBAR[0x1B0004]))
|
||||
#define MCF_GPTB_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1B0006]))
|
||||
#define MCF_GPTB_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1B0008]))
|
||||
#define MCF_GPTB_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1B0009]))
|
||||
#define MCF_GPTB_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1B000B]))
|
||||
#define MCF_GPTB_GPTIE (*(vuint8 *)(&__IPSBAR[0x1B000C]))
|
||||
#define MCF_GPTB_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1B000D]))
|
||||
#define MCF_GPTB_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1B000E]))
|
||||
#define MCF_GPTB_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1B000F]))
|
||||
#define MCF_GPTB_GPTC0 (*(vuint16*)(&__IPSBAR[0x1B0010]))
|
||||
#define MCF_GPTB_GPTC1 (*(vuint16*)(&__IPSBAR[0x1B0012]))
|
||||
#define MCF_GPTB_GPTC2 (*(vuint16*)(&__IPSBAR[0x1B0014]))
|
||||
#define MCF_GPTB_GPTC3 (*(vuint16*)(&__IPSBAR[0x1B0016]))
|
||||
#define MCF_GPTB_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1B0018]))
|
||||
#define MCF_GPTB_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1B0019]))
|
||||
#define MCF_GPTB_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1B001A]))
|
||||
#define MCF_GPTB_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1B001D]))
|
||||
#define MCF_GPTB_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1B001E]))
|
||||
#define MCF_GPTB_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1B0010 + ((x)*0x2)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTIOS */
|
||||
#define MCF_GPTB_GPTIOS_IOS0 (0x1)
|
||||
#define MCF_GPTB_GPTIOS_IOS1 (0x2)
|
||||
#define MCF_GPTB_GPTIOS_IOS2 (0x4)
|
||||
#define MCF_GPTB_GPTIOS_IOS3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTCFORC */
|
||||
#define MCF_GPTB_GPTCFORC_FOC0 (0x1)
|
||||
#define MCF_GPTB_GPTCFORC_FOC1 (0x2)
|
||||
#define MCF_GPTB_GPTCFORC_FOC2 (0x4)
|
||||
#define MCF_GPTB_GPTCFORC_FOC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTOC3M */
|
||||
#define MCF_GPTB_GPTOC3M_OC3M0 (0x1)
|
||||
#define MCF_GPTB_GPTOC3M_OC3M1 (0x2)
|
||||
#define MCF_GPTB_GPTOC3M_OC3M2 (0x4)
|
||||
#define MCF_GPTB_GPTOC3M_OC3M3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTOC3D */
|
||||
#define MCF_GPTB_GPTOC3D_OC3D0 (0x1)
|
||||
#define MCF_GPTB_GPTOC3D_OC3D1 (0x2)
|
||||
#define MCF_GPTB_GPTOC3D_OC3D2 (0x4)
|
||||
#define MCF_GPTB_GPTOC3D_OC3D3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTCNT */
|
||||
#define MCF_GPTB_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTSCR1 */
|
||||
#define MCF_GPTB_GPTSCR1_TFFCA (0x10)
|
||||
#define MCF_GPTB_GPTSCR1_GPTEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTTOV */
|
||||
#define MCF_GPTB_GPTTOV_TOV0 (0x1)
|
||||
#define MCF_GPTB_GPTTOV_TOV1 (0x2)
|
||||
#define MCF_GPTB_GPTTOV_TOV2 (0x4)
|
||||
#define MCF_GPTB_GPTTOV_TOV3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTCTL1 */
|
||||
#define MCF_GPTB_GPTCTL1_OL0 (0x1)
|
||||
#define MCF_GPTB_GPTCTL1_OM0 (0x2)
|
||||
#define MCF_GPTB_GPTCTL1_OL1 (0x4)
|
||||
#define MCF_GPTB_GPTCTL1_OM1 (0x8)
|
||||
#define MCF_GPTB_GPTCTL1_OL2 (0x10)
|
||||
#define MCF_GPTB_GPTCTL1_OM2 (0x20)
|
||||
#define MCF_GPTB_GPTCTL1_OL3 (0x40)
|
||||
#define MCF_GPTB_GPTCTL1_OM3 (0x80)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT0_NOTHING (0)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT0_TOGGLE (0x1)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT0_CLEAR (0x2)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT0_SET (0x3)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT1_NOTHING (0)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT1_TOGGLE (0x4)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT1_CLEAR (0x8)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT1_SET (0xC)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT2_NOTHING (0)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT2_TOGGLE (0x10)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT2_CLEAR (0x20)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT2_SET (0x30)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT3_NOTHING (0)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT3_TOGGLE (0x40)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT3_CLEAR (0x80)
|
||||
#define MCF_GPTB_GPTCTL1_OUTPUT3_SET (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTCTL2 */
|
||||
#define MCF_GPTB_GPTCTL2_EDG0A (0x1)
|
||||
#define MCF_GPTB_GPTCTL2_EDG0B (0x2)
|
||||
#define MCF_GPTB_GPTCTL2_EDG1A (0x4)
|
||||
#define MCF_GPTB_GPTCTL2_EDG1B (0x8)
|
||||
#define MCF_GPTB_GPTCTL2_EDG2A (0x10)
|
||||
#define MCF_GPTB_GPTCTL2_EDG2B (0x20)
|
||||
#define MCF_GPTB_GPTCTL2_EDG3A (0x40)
|
||||
#define MCF_GPTB_GPTCTL2_EDG3B (0x80)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT0_DISABLED (0)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT0_RISING (0x1)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT0_FALLING (0x2)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT0_ANY (0x3)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT1_DISABLED (0)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT1_RISING (0x4)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT1_FALLING (0x8)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT1_ANY (0xC)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT2_DISABLED (0)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT2_RISING (0x10)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT2_FALLING (0x20)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT2_ANY (0x30)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT3_DISABLED (0)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT3_RISING (0x40)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT3_FALLING (0x80)
|
||||
#define MCF_GPTB_GPTCTL2_INPUT3_ANY (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTIE */
|
||||
#define MCF_GPTB_GPTIE_CI0 (0x1)
|
||||
#define MCF_GPTB_GPTIE_CI1 (0x2)
|
||||
#define MCF_GPTB_GPTIE_CI2 (0x4)
|
||||
#define MCF_GPTB_GPTIE_CI3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTSCR2 */
|
||||
#define MCF_GPTB_GPTSCR2_PR(x) (((x)&0x7)<<0)
|
||||
#define MCF_GPTB_GPTSCR2_PR_1 (0)
|
||||
#define MCF_GPTB_GPTSCR2_PR_2 (0x1)
|
||||
#define MCF_GPTB_GPTSCR2_PR_4 (0x2)
|
||||
#define MCF_GPTB_GPTSCR2_PR_8 (0x3)
|
||||
#define MCF_GPTB_GPTSCR2_PR_16 (0x4)
|
||||
#define MCF_GPTB_GPTSCR2_PR_32 (0x5)
|
||||
#define MCF_GPTB_GPTSCR2_PR_64 (0x6)
|
||||
#define MCF_GPTB_GPTSCR2_PR_128 (0x7)
|
||||
#define MCF_GPTB_GPTSCR2_TCRE (0x8)
|
||||
#define MCF_GPTB_GPTSCR2_RDPT (0x10)
|
||||
#define MCF_GPTB_GPTSCR2_PUPT (0x20)
|
||||
#define MCF_GPTB_GPTSCR2_TOI (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTFLG1 */
|
||||
#define MCF_GPTB_GPTFLG1_CF0 (0x1)
|
||||
#define MCF_GPTB_GPTFLG1_CF1 (0x2)
|
||||
#define MCF_GPTB_GPTFLG1_CF2 (0x4)
|
||||
#define MCF_GPTB_GPTFLG1_CF3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTFLG2 */
|
||||
#define MCF_GPTB_GPTFLG2_TOF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTC */
|
||||
#define MCF_GPTB_GPTC_CCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTPACTL */
|
||||
#define MCF_GPTB_GPTPACTL_PAI (0x1)
|
||||
#define MCF_GPTB_GPTPACTL_PAOVI (0x2)
|
||||
#define MCF_GPTB_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPTB_GPTPACTL_CLK_GPTPR (0)
|
||||
#define MCF_GPTB_GPTPACTL_CLK_PACLK (0x1)
|
||||
#define MCF_GPTB_GPTPACTL_CLK_PACLK_256 (0x2)
|
||||
#define MCF_GPTB_GPTPACTL_CLK_PACLK_65536 (0x3)
|
||||
#define MCF_GPTB_GPTPACTL_PEDGE (0x10)
|
||||
#define MCF_GPTB_GPTPACTL_PAMOD (0x20)
|
||||
#define MCF_GPTB_GPTPACTL_PAE (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTPAFLG */
|
||||
#define MCF_GPTB_GPTPAFLG_PAIF (0x1)
|
||||
#define MCF_GPTB_GPTPAFLG_PAOVF (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTPACNT */
|
||||
#define MCF_GPTB_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTPORT */
|
||||
#define MCF_GPTB_GPTPORT_PORTT0 (0x1)
|
||||
#define MCF_GPTB_GPTPORT_PORTT1 (0x2)
|
||||
#define MCF_GPTB_GPTPORT_PORTT2 (0x4)
|
||||
#define MCF_GPTB_GPTPORT_PORTT3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTB_GPTDDR */
|
||||
#define MCF_GPTB_GPTDDR_DDRT0 (0x1)
|
||||
#define MCF_GPTB_GPTDDR_DDRT1 (0x2)
|
||||
#define MCF_GPTB_GPTDDR_DDRT2 (0x4)
|
||||
#define MCF_GPTB_GPTDDR_DDRT3 (0x8)
|
||||
|
||||
|
||||
#endif /* __MCF5282_GPTB_H__ */
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_I2C_H__
|
||||
#define __MCF5282_I2C_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* I2C Module (I2C)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_I2C_I2ADR (*(vuint8 *)(&__IPSBAR[0x300]))
|
||||
#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x304]))
|
||||
#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x308]))
|
||||
#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x30C]))
|
||||
#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x310]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ADR */
|
||||
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2FDR */
|
||||
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2CR */
|
||||
#define MCF_I2C_I2CR_RSTA (0x4)
|
||||
#define MCF_I2C_I2CR_TXAK (0x8)
|
||||
#define MCF_I2C_I2CR_MTX (0x10)
|
||||
#define MCF_I2C_I2CR_MSTA (0x20)
|
||||
#define MCF_I2C_I2CR_IIEN (0x40)
|
||||
#define MCF_I2C_I2CR_IEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2SR */
|
||||
#define MCF_I2C_I2SR_RXAK (0x1)
|
||||
#define MCF_I2C_I2SR_IIF (0x2)
|
||||
#define MCF_I2C_I2SR_SRW (0x4)
|
||||
#define MCF_I2C_I2SR_IAL (0x10)
|
||||
#define MCF_I2C_I2SR_IBB (0x20)
|
||||
#define MCF_I2C_I2SR_IAAS (0x40)
|
||||
#define MCF_I2C_I2SR_ICF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2DR */
|
||||
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5282_I2C_H__ */
|
||||
|
|
@ -1,484 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_INTC_H__
|
||||
#define __MCF5282_INTC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller (INTC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0xC00]))
|
||||
#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0xC04]))
|
||||
#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0xC08]))
|
||||
#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0xC0C]))
|
||||
#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0xC10]))
|
||||
#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0xC14]))
|
||||
#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0xC18]))
|
||||
#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0xC19]))
|
||||
#define MCF_INTC0_ICR01 (*(vuint8 *)(&__IPSBAR[0xC41]))
|
||||
#define MCF_INTC0_ICR02 (*(vuint8 *)(&__IPSBAR[0xC42]))
|
||||
#define MCF_INTC0_ICR03 (*(vuint8 *)(&__IPSBAR[0xC43]))
|
||||
#define MCF_INTC0_ICR04 (*(vuint8 *)(&__IPSBAR[0xC44]))
|
||||
#define MCF_INTC0_ICR05 (*(vuint8 *)(&__IPSBAR[0xC45]))
|
||||
#define MCF_INTC0_ICR06 (*(vuint8 *)(&__IPSBAR[0xC46]))
|
||||
#define MCF_INTC0_ICR07 (*(vuint8 *)(&__IPSBAR[0xC47]))
|
||||
#define MCF_INTC0_ICR08 (*(vuint8 *)(&__IPSBAR[0xC48]))
|
||||
#define MCF_INTC0_ICR09 (*(vuint8 *)(&__IPSBAR[0xC49]))
|
||||
#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0xC4A]))
|
||||
#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0xC4B]))
|
||||
#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0xC4C]))
|
||||
#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0xC4D]))
|
||||
#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0xC4E]))
|
||||
#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0xC4F]))
|
||||
#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0xC50]))
|
||||
#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0xC51]))
|
||||
#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0xC52]))
|
||||
#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0xC53]))
|
||||
#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0xC54]))
|
||||
#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0xC55]))
|
||||
#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0xC56]))
|
||||
#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0xC57]))
|
||||
#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0xC58]))
|
||||
#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0xC59]))
|
||||
#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0xC5A]))
|
||||
#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0xC5B]))
|
||||
#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0xC5C]))
|
||||
#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0xC5D]))
|
||||
#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0xC5E]))
|
||||
#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0xC5F]))
|
||||
#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0xC60]))
|
||||
#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0xC61]))
|
||||
#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0xC62]))
|
||||
#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0xC63]))
|
||||
#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0xC64]))
|
||||
#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0xC65]))
|
||||
#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0xC66]))
|
||||
#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0xC67]))
|
||||
#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0xC68]))
|
||||
#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0xC69]))
|
||||
#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0xC6A]))
|
||||
#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0xC6B]))
|
||||
#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0xC6C]))
|
||||
#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0xC6D]))
|
||||
#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0xC6E]))
|
||||
#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0xC6F]))
|
||||
#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0xC70]))
|
||||
#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0xC71]))
|
||||
#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0xC72]))
|
||||
#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0xC73]))
|
||||
#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0xC74]))
|
||||
#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0xC75]))
|
||||
#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0xC76]))
|
||||
#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0xC77]))
|
||||
#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0xC78]))
|
||||
#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0xC79]))
|
||||
#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0xC7A]))
|
||||
#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0xC7B]))
|
||||
#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0xC7C]))
|
||||
#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0xC7D]))
|
||||
#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0xC7E]))
|
||||
#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0xC7F]))
|
||||
#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0xCE0]))
|
||||
#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0xCE4]))
|
||||
#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0xCE8]))
|
||||
#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0xCEC]))
|
||||
#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0xCF0]))
|
||||
#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0xCF4]))
|
||||
#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0xCF8]))
|
||||
#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0xCFC]))
|
||||
#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0xC41 + ((x-1)*0x1)]))
|
||||
#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0xCE4 + ((x-1)*0x4)]))
|
||||
|
||||
#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0xD00]))
|
||||
#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0xD04]))
|
||||
#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0xD08]))
|
||||
#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0xD0C]))
|
||||
#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0xD10]))
|
||||
#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0xD14]))
|
||||
#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0xD18]))
|
||||
#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0xD19]))
|
||||
#define MCF_INTC1_ICR01 (*(vuint8 *)(&__IPSBAR[0xD41]))
|
||||
#define MCF_INTC1_ICR02 (*(vuint8 *)(&__IPSBAR[0xD42]))
|
||||
#define MCF_INTC1_ICR03 (*(vuint8 *)(&__IPSBAR[0xD43]))
|
||||
#define MCF_INTC1_ICR04 (*(vuint8 *)(&__IPSBAR[0xD44]))
|
||||
#define MCF_INTC1_ICR05 (*(vuint8 *)(&__IPSBAR[0xD45]))
|
||||
#define MCF_INTC1_ICR06 (*(vuint8 *)(&__IPSBAR[0xD46]))
|
||||
#define MCF_INTC1_ICR07 (*(vuint8 *)(&__IPSBAR[0xD47]))
|
||||
#define MCF_INTC1_ICR08 (*(vuint8 *)(&__IPSBAR[0xD48]))
|
||||
#define MCF_INTC1_ICR09 (*(vuint8 *)(&__IPSBAR[0xD49]))
|
||||
#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0xD4A]))
|
||||
#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0xD4B]))
|
||||
#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0xD4C]))
|
||||
#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0xD4D]))
|
||||
#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0xD4E]))
|
||||
#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0xD4F]))
|
||||
#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0xD50]))
|
||||
#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0xD51]))
|
||||
#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0xD52]))
|
||||
#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0xD53]))
|
||||
#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0xD54]))
|
||||
#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0xD55]))
|
||||
#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0xD56]))
|
||||
#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0xD57]))
|
||||
#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0xD58]))
|
||||
#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0xD59]))
|
||||
#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0xD5A]))
|
||||
#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0xD5B]))
|
||||
#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0xD5C]))
|
||||
#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0xD5D]))
|
||||
#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0xD5E]))
|
||||
#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0xD5F]))
|
||||
#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0xD60]))
|
||||
#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0xD61]))
|
||||
#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0xD62]))
|
||||
#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0xD63]))
|
||||
#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0xD64]))
|
||||
#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0xD65]))
|
||||
#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0xD66]))
|
||||
#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0xD67]))
|
||||
#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0xD68]))
|
||||
#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0xD69]))
|
||||
#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0xD6A]))
|
||||
#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0xD6B]))
|
||||
#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0xD6C]))
|
||||
#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0xD6D]))
|
||||
#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0xD6E]))
|
||||
#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0xD6F]))
|
||||
#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0xD70]))
|
||||
#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0xD71]))
|
||||
#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0xD72]))
|
||||
#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0xD73]))
|
||||
#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0xD74]))
|
||||
#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0xD75]))
|
||||
#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0xD76]))
|
||||
#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0xD77]))
|
||||
#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0xD78]))
|
||||
#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0xD79]))
|
||||
#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0xD7A]))
|
||||
#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0xD7B]))
|
||||
#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0xD7C]))
|
||||
#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0xD7D]))
|
||||
#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0xD7E]))
|
||||
#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0xD7F]))
|
||||
#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0xDE0]))
|
||||
#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0xDE4]))
|
||||
#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0xDE8]))
|
||||
#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0xDEC]))
|
||||
#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0xDF0]))
|
||||
#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0xDF4]))
|
||||
#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0xDF8]))
|
||||
#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0xDFC]))
|
||||
#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0xD41 + ((x-1)*0x1)]))
|
||||
#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0xDE4 + ((x-1)*0x4)]))
|
||||
|
||||
#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0xC00 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0xC04 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0xC08 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0xC0C + ((x)*0x100)]))
|
||||
#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0xC10 + ((x)*0x100)]))
|
||||
#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0xC14 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0xC18 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0xC19 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR01(x) (*(vuint8 *)(&__IPSBAR[0xC41 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR02(x) (*(vuint8 *)(&__IPSBAR[0xC42 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR03(x) (*(vuint8 *)(&__IPSBAR[0xC43 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR04(x) (*(vuint8 *)(&__IPSBAR[0xC44 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR05(x) (*(vuint8 *)(&__IPSBAR[0xC45 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR06(x) (*(vuint8 *)(&__IPSBAR[0xC46 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR07(x) (*(vuint8 *)(&__IPSBAR[0xC47 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR08(x) (*(vuint8 *)(&__IPSBAR[0xC48 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR09(x) (*(vuint8 *)(&__IPSBAR[0xC49 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0xC4A + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0xC4B + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0xC4C + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0xC4D + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0xC4E + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0xC4F + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0xC50 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0xC51 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0xC52 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0xC53 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0xC54 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0xC55 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0xC56 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0xC57 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0xC58 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0xC59 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0xC5A + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0xC5B + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0xC5C + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0xC5D + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0xC5E + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0xC5F + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0xC60 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0xC61 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0xC62 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0xC63 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0xC64 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0xC65 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0xC66 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0xC67 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0xC68 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0xC69 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0xC6A + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0xC6B + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0xC6C + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0xC6D + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0xC6E + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0xC6F + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0xC70 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0xC71 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0xC72 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0xC73 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0xC74 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0xC75 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0xC76 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0xC77 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0xC78 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0xC79 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0xC7A + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0xC7B + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0xC7C + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0xC7D + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0xC7E + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0xC7F + ((x)*0x100)]))
|
||||
#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0xCE0 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0xCE4 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0xCE8 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0xCEC + ((x)*0x100)]))
|
||||
#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF0 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF4 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF8 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0xCFC + ((x)*0x100)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRH */
|
||||
#define MCF_INTC_IPRH_INT32 (0x1)
|
||||
#define MCF_INTC_IPRH_INT33 (0x2)
|
||||
#define MCF_INTC_IPRH_INT34 (0x4)
|
||||
#define MCF_INTC_IPRH_INT35 (0x8)
|
||||
#define MCF_INTC_IPRH_INT36 (0x10)
|
||||
#define MCF_INTC_IPRH_INT37 (0x20)
|
||||
#define MCF_INTC_IPRH_INT38 (0x40)
|
||||
#define MCF_INTC_IPRH_INT39 (0x80)
|
||||
#define MCF_INTC_IPRH_INT40 (0x100)
|
||||
#define MCF_INTC_IPRH_INT41 (0x200)
|
||||
#define MCF_INTC_IPRH_INT42 (0x400)
|
||||
#define MCF_INTC_IPRH_INT43 (0x800)
|
||||
#define MCF_INTC_IPRH_INT44 (0x1000)
|
||||
#define MCF_INTC_IPRH_INT45 (0x2000)
|
||||
#define MCF_INTC_IPRH_INT46 (0x4000)
|
||||
#define MCF_INTC_IPRH_INT47 (0x8000)
|
||||
#define MCF_INTC_IPRH_INT48 (0x10000)
|
||||
#define MCF_INTC_IPRH_INT49 (0x20000)
|
||||
#define MCF_INTC_IPRH_INT50 (0x40000)
|
||||
#define MCF_INTC_IPRH_INT51 (0x80000)
|
||||
#define MCF_INTC_IPRH_INT52 (0x100000)
|
||||
#define MCF_INTC_IPRH_INT53 (0x200000)
|
||||
#define MCF_INTC_IPRH_INT54 (0x400000)
|
||||
#define MCF_INTC_IPRH_INT55 (0x800000)
|
||||
#define MCF_INTC_IPRH_INT56 (0x1000000)
|
||||
#define MCF_INTC_IPRH_INT57 (0x2000000)
|
||||
#define MCF_INTC_IPRH_INT58 (0x4000000)
|
||||
#define MCF_INTC_IPRH_INT59 (0x8000000)
|
||||
#define MCF_INTC_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRL */
|
||||
#define MCF_INTC_IPRL_INT1 (0x2)
|
||||
#define MCF_INTC_IPRL_INT2 (0x4)
|
||||
#define MCF_INTC_IPRL_INT3 (0x8)
|
||||
#define MCF_INTC_IPRL_INT4 (0x10)
|
||||
#define MCF_INTC_IPRL_INT5 (0x20)
|
||||
#define MCF_INTC_IPRL_INT6 (0x40)
|
||||
#define MCF_INTC_IPRL_INT7 (0x80)
|
||||
#define MCF_INTC_IPRL_INT8 (0x100)
|
||||
#define MCF_INTC_IPRL_INT9 (0x200)
|
||||
#define MCF_INTC_IPRL_INT10 (0x400)
|
||||
#define MCF_INTC_IPRL_INT11 (0x800)
|
||||
#define MCF_INTC_IPRL_INT12 (0x1000)
|
||||
#define MCF_INTC_IPRL_INT13 (0x2000)
|
||||
#define MCF_INTC_IPRL_INT14 (0x4000)
|
||||
#define MCF_INTC_IPRL_INT15 (0x8000)
|
||||
#define MCF_INTC_IPRL_INT16 (0x10000)
|
||||
#define MCF_INTC_IPRL_INT17 (0x20000)
|
||||
#define MCF_INTC_IPRL_INT18 (0x40000)
|
||||
#define MCF_INTC_IPRL_INT19 (0x80000)
|
||||
#define MCF_INTC_IPRL_INT20 (0x100000)
|
||||
#define MCF_INTC_IPRL_INT21 (0x200000)
|
||||
#define MCF_INTC_IPRL_INT22 (0x400000)
|
||||
#define MCF_INTC_IPRL_INT23 (0x800000)
|
||||
#define MCF_INTC_IPRL_INT24 (0x1000000)
|
||||
#define MCF_INTC_IPRL_INT25 (0x2000000)
|
||||
#define MCF_INTC_IPRL_INT26 (0x4000000)
|
||||
#define MCF_INTC_IPRL_INT27 (0x8000000)
|
||||
#define MCF_INTC_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRH */
|
||||
#define MCF_INTC_IMRH_INT_MASK32 (0x1)
|
||||
#define MCF_INTC_IMRH_INT_MASK33 (0x2)
|
||||
#define MCF_INTC_IMRH_INT_MASK34 (0x4)
|
||||
#define MCF_INTC_IMRH_INT_MASK35 (0x8)
|
||||
#define MCF_INTC_IMRH_INT_MASK36 (0x10)
|
||||
#define MCF_INTC_IMRH_INT_MASK37 (0x20)
|
||||
#define MCF_INTC_IMRH_INT_MASK38 (0x40)
|
||||
#define MCF_INTC_IMRH_INT_MASK39 (0x80)
|
||||
#define MCF_INTC_IMRH_INT_MASK40 (0x100)
|
||||
#define MCF_INTC_IMRH_INT_MASK41 (0x200)
|
||||
#define MCF_INTC_IMRH_INT_MASK42 (0x400)
|
||||
#define MCF_INTC_IMRH_INT_MASK43 (0x800)
|
||||
#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
|
||||
#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
|
||||
#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
|
||||
#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
|
||||
#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
|
||||
#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
|
||||
#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
|
||||
#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
|
||||
#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
|
||||
#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
|
||||
#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
|
||||
#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
|
||||
#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRL */
|
||||
#define MCF_INTC_IMRL_MASKALL (0x1)
|
||||
#define MCF_INTC_IMRL_INT_MASK1 (0x2)
|
||||
#define MCF_INTC_IMRL_INT_MASK2 (0x4)
|
||||
#define MCF_INTC_IMRL_INT_MASK3 (0x8)
|
||||
#define MCF_INTC_IMRL_INT_MASK4 (0x10)
|
||||
#define MCF_INTC_IMRL_INT_MASK5 (0x20)
|
||||
#define MCF_INTC_IMRL_INT_MASK6 (0x40)
|
||||
#define MCF_INTC_IMRL_INT_MASK7 (0x80)
|
||||
#define MCF_INTC_IMRL_INT_MASK8 (0x100)
|
||||
#define MCF_INTC_IMRL_INT_MASK9 (0x200)
|
||||
#define MCF_INTC_IMRL_INT_MASK10 (0x400)
|
||||
#define MCF_INTC_IMRL_INT_MASK11 (0x800)
|
||||
#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
|
||||
#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
|
||||
#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
|
||||
#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
|
||||
#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
|
||||
#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
|
||||
#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
|
||||
#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
|
||||
#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
|
||||
#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
|
||||
#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
|
||||
#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
|
||||
#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCH */
|
||||
#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
|
||||
#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
|
||||
#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
|
||||
#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
|
||||
#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
|
||||
#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
|
||||
#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
|
||||
#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
|
||||
#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
|
||||
#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
|
||||
#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
|
||||
#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
|
||||
#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCL */
|
||||
#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
|
||||
#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
|
||||
#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
|
||||
#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
|
||||
#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
|
||||
#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
|
||||
#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
|
||||
#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
|
||||
#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
|
||||
#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
|
||||
#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
|
||||
#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IRLR */
|
||||
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IACKLPR */
|
||||
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
|
||||
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_ICR */
|
||||
#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
|
||||
#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_SWIACK */
|
||||
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_LIACK */
|
||||
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5282_INTC_H__ */
|
||||
|
|
@ -1,159 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_PAD_H__
|
||||
#define __MCF5282_PAD_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Common GPIO Registers
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PAD_PBCDPAR (*(vuint8 *)(&__IPSBAR[0x100050]))
|
||||
#define MCF_PAD_PFPAR (*(vuint8 *)(&__IPSBAR[0x100051]))
|
||||
#define MCF_PAD_PEPAR (*(vuint16*)(&__IPSBAR[0x100052]))
|
||||
#define MCF_PAD_PJPAR (*(vuint8 *)(&__IPSBAR[0x100054]))
|
||||
#define MCF_PAD_PSDPAR (*(vuint8 *)(&__IPSBAR[0x100055]))
|
||||
#define MCF_PAD_PASPAR (*(vuint16*)(&__IPSBAR[0x100056]))
|
||||
#define MCF_PAD_PEHLPAR (*(vuint8 *)(&__IPSBAR[0x100058]))
|
||||
#define MCF_PAD_PQSPAR (*(vuint8 *)(&__IPSBAR[0x100059]))
|
||||
#define MCF_PAD_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10005A]))
|
||||
#define MCF_PAD_PTDPAR (*(vuint8 *)(&__IPSBAR[0x10005B]))
|
||||
#define MCF_PAD_PUAPAR (*(vuint8 *)(&__IPSBAR[0x10005C]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PBCDPAR */
|
||||
#define MCF_PAD_PBCDPAR_PCDPA (0x40)
|
||||
#define MCF_PAD_PBCDPAR_PBPA (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PFPAR */
|
||||
#define MCF_PAD_PFPAR_PFPA5 (0x20)
|
||||
#define MCF_PAD_PFPAR_PFPA6 (0x40)
|
||||
#define MCF_PAD_PFPAR_PFPA7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PEPAR */
|
||||
#define MCF_PAD_PEPAR_PEPA0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PEPAR_PEPA0_GPIO (0)
|
||||
#define MCF_PAD_PEPAR_PEPA0_SYNCB (0x2)
|
||||
#define MCF_PAD_PEPAR_PEPA0_TIP (0x3)
|
||||
#define MCF_PAD_PEPAR_PEPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PEPAR_PEPA1_GPIO (0)
|
||||
#define MCF_PAD_PEPAR_PEPA1_SYNCA (0x8)
|
||||
#define MCF_PAD_PEPAR_PEPA1_TS (0xC)
|
||||
#define MCF_PAD_PEPAR_PEPA2 (0x10)
|
||||
#define MCF_PAD_PEPAR_PEPA3 (0x40)
|
||||
#define MCF_PAD_PEPAR_PEPA4 (0x100)
|
||||
#define MCF_PAD_PEPAR_PEPA5 (0x400)
|
||||
#define MCF_PAD_PEPAR_PEPA6 (0x1000)
|
||||
#define MCF_PAD_PEPAR_PEPA7 (0x4000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PJPAR */
|
||||
#define MCF_PAD_PJPAR_PJPA0 (0x1)
|
||||
#define MCF_PAD_PJPAR_PJPA1 (0x2)
|
||||
#define MCF_PAD_PJPAR_PJPA2 (0x4)
|
||||
#define MCF_PAD_PJPAR_PJPA3 (0x8)
|
||||
#define MCF_PAD_PJPAR_PJPA4 (0x10)
|
||||
#define MCF_PAD_PJPAR_PJPA5 (0x20)
|
||||
#define MCF_PAD_PJPAR_PJPA6 (0x40)
|
||||
#define MCF_PAD_PJPAR_PJPA7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PSDPAR */
|
||||
#define MCF_PAD_PSDPAR_PSDPA (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PASPAR */
|
||||
#define MCF_PAD_PASPAR_PASPA0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PASPAR_PASPA0_GPIO (0)
|
||||
#define MCF_PAD_PASPAR_PASPA0_UTXD2 (0x2)
|
||||
#define MCF_PAD_PASPAR_PASPA0_SCL (0x3)
|
||||
#define MCF_PAD_PASPAR_PASPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PASPAR_PASPA1_GPIO (0)
|
||||
#define MCF_PAD_PASPAR_PASPA1_URXD2 (0x8)
|
||||
#define MCF_PAD_PASPAR_PASPA1_SDA (0xC)
|
||||
#define MCF_PAD_PASPAR_PASPA2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PASPAR_PASPA2_GPIO (0)
|
||||
#define MCF_PAD_PASPAR_PASPA2_UTXD2 (0x20)
|
||||
#define MCF_PAD_PASPAR_PASPA2_CANTX (0x30)
|
||||
#define MCF_PAD_PASPAR_PASPA3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PASPAR_PASPA3_GPIO (0)
|
||||
#define MCF_PAD_PASPAR_PASPA3_URXD2 (0x80)
|
||||
#define MCF_PAD_PASPAR_PASPA3_CANRX (0xC0)
|
||||
#define MCF_PAD_PASPAR_PASPA4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_PAD_PASPAR_PASPA4_GPIO (0)
|
||||
#define MCF_PAD_PASPAR_PASPA4_UTXD2 (0x200)
|
||||
#define MCF_PAD_PASPAR_PASPA4_EMDC (0x300)
|
||||
#define MCF_PAD_PASPAR_PASPA5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_PAD_PASPAR_PASPA5_GPIO (0)
|
||||
#define MCF_PAD_PASPAR_PASPA5_URXD2 (0x800)
|
||||
#define MCF_PAD_PASPAR_PASPA5_EMDIO (0xC00)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PEHLPAR */
|
||||
#define MCF_PAD_PEHLPAR_PELPA (0x40)
|
||||
#define MCF_PAD_PEHLPAR_PEHPA (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PQSPAR */
|
||||
#define MCF_PAD_PQSPAR_PQSPA0 (0x1)
|
||||
#define MCF_PAD_PQSPAR_PQSPA1 (0x2)
|
||||
#define MCF_PAD_PQSPAR_PQSPA2 (0x4)
|
||||
#define MCF_PAD_PQSPAR_PQSPA3 (0x8)
|
||||
#define MCF_PAD_PQSPAR_PQSPA4 (0x10)
|
||||
#define MCF_PAD_PQSPAR_PQSPA5 (0x20)
|
||||
#define MCF_PAD_PQSPAR_PQSPA6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PTCPAR */
|
||||
#define MCF_PAD_PTCPAR_PTCPA0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PTCPAR_PTCPA0_GPIO (0)
|
||||
#define MCF_PAD_PTCPAR_PTCPA0_UCTS0 (0x1)
|
||||
#define MCF_PAD_PTCPAR_PTCPA0_UCTS1 (0x2)
|
||||
#define MCF_PAD_PTCPAR_PTCPA0_TOUT2 (0x3)
|
||||
#define MCF_PAD_PTCPAR_PTCPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PTCPAR_PTCPA1_GPIO (0)
|
||||
#define MCF_PAD_PTCPAR_PTCPA1_UCTS0 (0x4)
|
||||
#define MCF_PAD_PTCPAR_PTCPA1_UCTS1 (0x8)
|
||||
#define MCF_PAD_PTCPAR_PTCPA1_TIN2 (0xC)
|
||||
#define MCF_PAD_PTCPAR_PTCPA2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PTCPAR_PTCPA2_GPIO (0)
|
||||
#define MCF_PAD_PTCPAR_PTCPA2_URTS0 (0x10)
|
||||
#define MCF_PAD_PTCPAR_PTCPA2_URTS1 (0x20)
|
||||
#define MCF_PAD_PTCPAR_PTCPA2_TOUT3 (0x30)
|
||||
#define MCF_PAD_PTCPAR_PTCPA3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PTCPAR_PTCPA3_GPIO (0)
|
||||
#define MCF_PAD_PTCPAR_PTCPA3_URTS0 (0x40)
|
||||
#define MCF_PAD_PTCPAR_PTCPA3_URTS1 (0x80)
|
||||
#define MCF_PAD_PTCPAR_PTCPA3_TIN3 (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PTDPAR */
|
||||
#define MCF_PAD_PTDPAR_PTDPA0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PTDPAR_PTDPA0_GPIO (0)
|
||||
#define MCF_PAD_PTDPAR_PTDPA0_UCTS0 (0x1)
|
||||
#define MCF_PAD_PTDPAR_PTDPA0_UCTS1 (0x2)
|
||||
#define MCF_PAD_PTDPAR_PTDPA0_TOUT0 (0x3)
|
||||
#define MCF_PAD_PTDPAR_PTDPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PTDPAR_PTDPA2_GPIO (0)
|
||||
#define MCF_PAD_PTDPAR_PTDPA2_UCTS0 (0x4)
|
||||
#define MCF_PAD_PTDPAR_PTDPA2_UCTS1 (0x8)
|
||||
#define MCF_PAD_PTDPAR_PTDPA2_TIN0 (0xC)
|
||||
#define MCF_PAD_PTDPAR_PTDPA2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PTDPAR_PTDPA2_URTS0 (0x10)
|
||||
#define MCF_PAD_PTDPAR_PTDPA2_URTS1 (0x20)
|
||||
#define MCF_PAD_PTDPAR_PTDPA2_TOUT1 (0x30)
|
||||
#define MCF_PAD_PTDPAR_PTDPA3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PTDPAR_PTDPA3_GPIO (0)
|
||||
#define MCF_PAD_PTDPAR_PTDPA3_URTS0 (0x40)
|
||||
#define MCF_PAD_PTDPAR_PTDPA3_URTS1 (0x80)
|
||||
#define MCF_PAD_PTDPAR_PTDPA3_TIN1 (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PUAPAR */
|
||||
#define MCF_PAD_PUAPAR_PUAPA0 (0x1)
|
||||
#define MCF_PAD_PUAPAR_PUAPA1 (0x2)
|
||||
#define MCF_PAD_PUAPAR_PUAPA2 (0x4)
|
||||
#define MCF_PAD_PUAPAR_PUAPA3 (0x8)
|
||||
|
||||
|
||||
#endif /* __MCF5282_PAD_H__ */
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_PIT_H__
|
||||
#define __MCF5282_PIT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Programmable Interrupt Timer (PIT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000]))
|
||||
#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002]))
|
||||
#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004]))
|
||||
|
||||
#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000]))
|
||||
#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002]))
|
||||
#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004]))
|
||||
|
||||
#define MCF_PIT2_PCSR (*(vuint16*)(&__IPSBAR[0x170000]))
|
||||
#define MCF_PIT2_PMR (*(vuint16*)(&__IPSBAR[0x170002]))
|
||||
#define MCF_PIT2_PCNTR (*(vuint16*)(&__IPSBAR[0x170004]))
|
||||
|
||||
#define MCF_PIT3_PCSR (*(vuint16*)(&__IPSBAR[0x180000]))
|
||||
#define MCF_PIT3_PMR (*(vuint16*)(&__IPSBAR[0x180002]))
|
||||
#define MCF_PIT3_PCNTR (*(vuint16*)(&__IPSBAR[0x180004]))
|
||||
|
||||
#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000 + ((x)*0x10000)]))
|
||||
#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002 + ((x)*0x10000)]))
|
||||
#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004 + ((x)*0x10000)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCSR */
|
||||
#define MCF_PIT_PCSR_EN (0x1)
|
||||
#define MCF_PIT_PCSR_RLD (0x2)
|
||||
#define MCF_PIT_PCSR_PIF (0x4)
|
||||
#define MCF_PIT_PCSR_PIE (0x8)
|
||||
#define MCF_PIT_PCSR_OVW (0x10)
|
||||
#define MCF_PIT_PCSR_HALTED (0x20)
|
||||
#define MCF_PIT_PCSR_DOZE (0x40)
|
||||
#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PMR */
|
||||
#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCNTR */
|
||||
#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5282_PIT_H__ */
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_PMM_H__
|
||||
#define __MCF5282_PMM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Power Management (PMM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x12]))
|
||||
#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PMM_LPICR */
|
||||
#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_PMM_LPICR_ENBSTOP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PMM_LPCR */
|
||||
#define MCF_PMM_LPCR_LVDSE (0x2)
|
||||
#define MCF_PMM_LPCR_STPMD(x) (((x)&0x3)<<0x3)
|
||||
#define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0)
|
||||
#define MCF_PMM_LPCR_STPMD_SYS_CLKOUT_DISABLED (0x8)
|
||||
#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x10)
|
||||
#define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x18)
|
||||
#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PMM_LPCR_LPMD_RUN (0)
|
||||
#define MCF_PMM_LPCR_LPMD_DOZE (0x40)
|
||||
#define MCF_PMM_LPCR_LPMD_WAIT (0x80)
|
||||
#define MCF_PMM_LPCR_LPMD_STOP (0xC0)
|
||||
|
||||
|
||||
#endif /* __MCF5282_PMM_H__ */
|
||||
|
|
@ -1,108 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_QADC_H__
|
||||
#define __MCF5282_QADC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Queued Analog-to-Digital Converter (QADC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_QADC_QADCMCR (*(vuint16*)(&__IPSBAR[0x190000]))
|
||||
#define MCF_QADC_PORTQA (*(vuint8 *)(&__IPSBAR[0x190006]))
|
||||
#define MCF_QADC_PORTQB (*(vuint8 *)(&__IPSBAR[0x190007]))
|
||||
#define MCF_QADC_DDRQA (*(vuint8 *)(&__IPSBAR[0x190008]))
|
||||
#define MCF_QADC_DDRQB (*(vuint8 *)(&__IPSBAR[0x190009]))
|
||||
#define MCF_QADC_QACR0 (*(vuint16*)(&__IPSBAR[0x19000A]))
|
||||
#define MCF_QADC_QACR1 (*(vuint16*)(&__IPSBAR[0x19000C]))
|
||||
#define MCF_QADC_QACR2 (*(vuint16*)(&__IPSBAR[0x19000E]))
|
||||
#define MCF_QADC_QASR0 (*(vuint16*)(&__IPSBAR[0x190010]))
|
||||
#define MCF_QADC_QASR1 (*(vuint16*)(&__IPSBAR[0x190012]))
|
||||
|
||||
/* Other macros */
|
||||
#define MCF_QADC_CCW(x) (*(vuint16*)(&__IPSBAR[0x190200 + (x*2)]))
|
||||
#define MCF_QADC_CCW_CHAN(x) (((x)&0x3F)<<0)
|
||||
#define MCF_QADC_CCW_IST(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_QADC_CCW_IST_QCLK2 (0)
|
||||
#define MCF_QADC_CCW_IST_QCLK4 (0x40)
|
||||
#define MCF_QADC_CCW_IST_QCLK8 (0x80)
|
||||
#define MCF_QADC_CCW_IST_QCLK16 (0xC0)
|
||||
#define MCF_QADC_CCW_BYP (0x100)
|
||||
#define MCF_QADC_CCW_P (0x200)
|
||||
#define MCF_QADC_RJURR(x) (*(vuint16*)(&__IPSBAR[0x190280 + (x*2)]))
|
||||
#define MCF_QADC_LJSRR(x) (*(vuint16*)(&__IPSBAR[0x190300 + (x*2)]))
|
||||
#define MCF_QADC_LJURR(x) (*(vuint16*)(&__IPSBAR[0x190380 + (x*2)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_QADCMCR */
|
||||
#define MCF_QADC_QADCMCR_SUPV (0x80)
|
||||
#define MCF_QADC_QADCMCR_QDBG (0x4000)
|
||||
#define MCF_QADC_QADCMCR_QSTOP (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_PORTQA */
|
||||
#define MCF_QADC_PORTQA_PQA0 (0x1)
|
||||
#define MCF_QADC_PORTQA_PQA1 (0x2)
|
||||
#define MCF_QADC_PORTQA_PQA2 (0x8)
|
||||
#define MCF_QADC_PORTQA_PQA3 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_PORTQB */
|
||||
#define MCF_QADC_PORTQB_PQB0 (0x1)
|
||||
#define MCF_QADC_PORTQB_PQB1 (0x2)
|
||||
#define MCF_QADC_PORTQB_PQB2 (0x4)
|
||||
#define MCF_QADC_PORTQB_PQB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_DDRQA */
|
||||
#define MCF_QADC_DDRQA_DDQA0 (0x1)
|
||||
#define MCF_QADC_DDRQA_DDQA1 (0x2)
|
||||
#define MCF_QADC_DDRQA_DDQA2 (0x8)
|
||||
#define MCF_QADC_DDRQA_DDQA3 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_DDRQB */
|
||||
#define MCF_QADC_DDRQB_DDQB0 (0x1)
|
||||
#define MCF_QADC_DDRQB_DDQB1 (0x2)
|
||||
#define MCF_QADC_DDRQB_DDQB2 (0x4)
|
||||
#define MCF_QADC_DDRQB_DDQB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_QACR0 */
|
||||
#define MCF_QADC_QACR0_QPR(x) (((x)&0x7F)<<0)
|
||||
#define MCF_QADC_QACR0_TRG (0x1000)
|
||||
#define MCF_QADC_QACR0_MUX (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_QACR1 */
|
||||
#define MCF_QADC_QACR1_MQ1(x) (((x)&0x1F)<<0x8)
|
||||
#define MCF_QADC_QACR1_SSE1 (0x2000)
|
||||
#define MCF_QADC_QACR1_PIE1 (0x4000)
|
||||
#define MCF_QADC_QACR1_CIE1 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_QACR2 */
|
||||
#define MCF_QADC_QACR2_BQ2(x) (((x)&0x7F)<<0)
|
||||
#define MCF_QADC_QACR2_RESUME (0x80)
|
||||
#define MCF_QADC_QACR2_MQ2(x) (((x)&0x1F)<<0x8)
|
||||
#define MCF_QADC_QACR2_SSE2 (0x2000)
|
||||
#define MCF_QADC_QACR2_PIE2 (0x4000)
|
||||
#define MCF_QADC_QACR2_CIE2 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_QASR0 */
|
||||
#define MCF_QADC_QASR0_CWP(x) (((x)&0x3F)<<0)
|
||||
#define MCF_QADC_QASR0_QS(x) (((x)&0xF)<<0x6)
|
||||
#define MCF_QADC_QASR0_TOR2 (0x400)
|
||||
#define MCF_QADC_QASR0_TOR1 (0x800)
|
||||
#define MCF_QADC_QASR0_PF2 (0x1000)
|
||||
#define MCF_QADC_QASR0_CF2 (0x2000)
|
||||
#define MCF_QADC_QASR0_PF1 (0x4000)
|
||||
#define MCF_QADC_QASR0_CF1 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QADC_QASR1 */
|
||||
#define MCF_QADC_QASR1_CWPQ2(x) (((x)&0x3F)<<0)
|
||||
#define MCF_QADC_QASR1_CWPQ1(x) (((x)&0x3F)<<0x8)
|
||||
|
||||
|
||||
#endif /* __MCF5282_QADC_H__ */
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_QSPI_H__
|
||||
#define __MCF5282_QSPI_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Queued Serial Peripheral Interface (QSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x340]))
|
||||
#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x344]))
|
||||
#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x348]))
|
||||
#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x34C]))
|
||||
#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x350]))
|
||||
#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x354]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QMR */
|
||||
#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)
|
||||
#define MCF_QSPI_QMR_CPHA (0x100)
|
||||
#define MCF_QSPI_QMR_CPOL (0x200)
|
||||
#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)
|
||||
#define MCF_QSPI_QMR_DOHIE (0x4000)
|
||||
#define MCF_QSPI_QMR_MSTR (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDLYR */
|
||||
#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)
|
||||
#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)
|
||||
#define MCF_QSPI_QDLYR_SPE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QWR */
|
||||
#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)
|
||||
#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_QSPI_QWR_CSIV (0x1000)
|
||||
#define MCF_QSPI_QWR_WRTO (0x2000)
|
||||
#define MCF_QSPI_QWR_WREN (0x4000)
|
||||
#define MCF_QSPI_QWR_HALT (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QIR */
|
||||
#define MCF_QSPI_QIR_SPIF (0x1)
|
||||
#define MCF_QSPI_QIR_ABRT (0x4)
|
||||
#define MCF_QSPI_QIR_WCEF (0x8)
|
||||
#define MCF_QSPI_QIR_SPIFE (0x100)
|
||||
#define MCF_QSPI_QIR_ABRTE (0x400)
|
||||
#define MCF_QSPI_QIR_WCEFE (0x800)
|
||||
#define MCF_QSPI_QIR_ABRTL (0x1000)
|
||||
#define MCF_QSPI_QIR_ABRTB (0x4000)
|
||||
#define MCF_QSPI_QIR_WCEFB (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QAR */
|
||||
#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)
|
||||
#define MCF_QSPI_QAR_TRANS (0)
|
||||
#define MCF_QSPI_QAR_RECV (0x10)
|
||||
#define MCF_QSPI_QAR_CMD (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDR */
|
||||
#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_QSPI_QDR_CONT (0x8000)
|
||||
#define MCF_QSPI_QDR_BITSE (0x4000)
|
||||
#define MCF_QSPI_QDR_DT (0x2000)
|
||||
#define MCF_QSPI_QDR_DSCK (0x1000)
|
||||
#define MCF_QSPI_QDR_QSPI_CS3 (0x800)
|
||||
#define MCF_QSPI_QDR_QSPI_CS2 (0x400)
|
||||
#define MCF_QSPI_QDR_QSPI_CS1 (0x200)
|
||||
#define MCF_QSPI_QDR_QSPI_CS0 (0x100)
|
||||
|
||||
|
||||
#endif /* __MCF5282_QSPI_H__ */
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.9
|
||||
*/
|
||||
|
||||
#ifndef __MCF5282_RCM_H__
|
||||
#define __MCF5282_RCM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Reset Controller Module (RCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RCM_RCR (*(vuint8 *)(&__IPSBAR[0x110000]))
|
||||
#define MCF_RCM_RSR (*(vuint8 *)(&__IPSBAR[0x110001]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RCR */
|
||||
#define MCF_RCM_RCR_LVDE (0x1)
|
||||
#define MCF_RCM_RCR_LVDRE (0x4)
|
||||
#define MCF_RCM_RCR_LVDIE (0x8)
|
||||
#define MCF_RCM_RCR_LVDF (0x10)
|
||||
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
|
||||
#define MCF_RCM_RCR_SOFTRST (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RSR */
|
||||
#define MCF_RCM_RSR_LOL (0x1)
|
||||
#define MCF_RCM_RSR_LOC (0x2)
|
||||
#define MCF_RCM_RSR_EXT (0x4)
|
||||
#define MCF_RCM_RSR_POR (0x8)
|
||||
#define MCF_RCM_RSR_WDR (0x10)
|
||||
#define MCF_RCM_RSR_SOFT (0x20)
|
||||
#define MCF_RCM_RSR_LVD (0x40)
|
||||
|
||||
|
||||
#endif /* __MCF5282_RCM_H__ */
|
||||
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