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Fix compiler issues cause by formatting assembly code on ESP32 port (#133)
This commit is contained in:
Carl Lundin
GitHub
parent
0b0a2060c0
commit
7cd4a4f276
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@ -1,37 +1,37 @@
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/*******************************************************************************
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* Copyright (c) 2006-2015 Cadence Design Systems Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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* --------------------------------------------------------------------------------
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*
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* XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
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*
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* This header contains definitions and macros for use primarily by Xtensa
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* RTOS assembly coded source files. It includes and uses the Xtensa hardware
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* abstraction layer (HAL) to deal with config specifics. It may also be
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* included in C source files.
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*
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* !! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
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*
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* NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
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*
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Copyright (c) 2006-2015 Cadence Design Systems Inc.
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||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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--------------------------------------------------------------------------------
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XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
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This header contains definitions and macros for use primarily by Xtensa
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RTOS assembly coded source files. It includes and uses the Xtensa hardware
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abstraction layer (HAL) to deal with config specifics. It may also be
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included in C source files.
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!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
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NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
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*******************************************************************************/
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#ifndef XTENSA_CONTEXT_H
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@ -52,9 +52,9 @@
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/*
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* -------------------------------------------------------------------------------
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* Macros that help define structures for both C and assembler.
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* -------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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Macros that help define structures for both C and assembler.
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-------------------------------------------------------------------------------
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*/
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#ifdef STRUCT_BEGIN
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@ -76,36 +76,32 @@
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#define STRUCT_BEGIN typedef struct {
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#define STRUCT_FIELD(ctype,size,asname,name) ctype name;
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#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype name[n];
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#define STRUCT_END( sname ) \
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} \
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sname;
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#define STRUCT_END(sname) } sname;
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#endif //_ASMLANGUAGE || __ASSEMBLER__
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/*
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* -------------------------------------------------------------------------------
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* INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
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*
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* A stack frame of this structure is allocated for any interrupt or exception.
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* It goes on the current stack. If the RTOS has a system stack for handling
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* interrupts, every thread stack must allow space for just one interrupt stack
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* frame, then nested interrupt stack frames go on the system stack.
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*
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* The frame includes basic registers (explicit) and "extra" registers introduced
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* by user TIE or the use of the MAC16 option in the user's Xtensa config.
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* The frame size is minimized by omitting regs not applicable to user's config.
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*
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* For Windowed ABI, this stack frame includes the interruptee's base save area,
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* another base save area to manage gcc nested functions, and a little temporary
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* space to help manage the spilling of the register windows.
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* -------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
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A stack frame of this structure is allocated for any interrupt or exception.
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It goes on the current stack. If the RTOS has a system stack for handling
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interrupts, every thread stack must allow space for just one interrupt stack
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frame, then nested interrupt stack frames go on the system stack.
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The frame includes basic registers (explicit) and "extra" registers introduced
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by user TIE or the use of the MAC16 option in the user's Xtensa config.
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The frame size is minimized by omitting regs not applicable to user's config.
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For Windowed ABI, this stack frame includes the interruptee's base save area,
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another base save area to manage gcc nested functions, and a little temporary
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space to help manage the spilling of the register windows.
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-------------------------------------------------------------------------------
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*/
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STRUCT_BEGIN STRUCT_FIELD( long,
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4,
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XT_STK_EXIT,
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exit ) /* exit point for dispatch */
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STRUCT_BEGIN
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STRUCT_FIELD (long, 4, XT_STK_EXIT, exit) /* exit point for dispatch */
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STRUCT_FIELD (long, 4, XT_STK_PC, pc) /* return PC */
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STRUCT_FIELD (long, 4, XT_STK_PS, ps) /* return PS */
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STRUCT_FIELD (long, 4, XT_STK_A0, a0)
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@ -169,46 +165,43 @@ STRUCT_END( XtExcFrame )
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#define XT_STK_NEXT2 XT_STK_NEXT1
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#endif /* if XCHAL_EXTRA_SA_SIZE != 0 */
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#endif
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/*
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* -------------------------------------------------------------------------------
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* This is the frame size. Add space for 4 registers (interruptee's base save
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* area) and some space for gcc nested functions if any.
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* -------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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This is the frame size. Add space for 4 registers (interruptee's base save
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area) and some space for gcc nested functions if any.
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-------------------------------------------------------------------------------
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*/
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#define XT_STK_FRMSZ (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
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/*
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* -------------------------------------------------------------------------------
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* SOLICITED STACK FRAME FOR A THREAD
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*
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* A stack frame of this structure is allocated whenever a thread enters the
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* RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
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* It goes on the current thread's stack.
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*
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* The solicited frame only includes registers that are required to be preserved
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* by the callee according to the compiler's ABI conventions, some space to save
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* the return address for returning to the caller, and the caller's PS register.
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*
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* For Windowed ABI, this stack frame includes the caller's base save area.
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*
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* Note on XT_SOL_EXIT field:
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* It is necessary to distinguish a solicited from an interrupt stack frame.
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* This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
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* always at the same offset (0). It can be written with a code (usually 0)
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* to distinguish a solicted frame from an interrupt frame. An RTOS port may
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* opt to ignore this field if it has another way of distinguishing frames.
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* -------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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SOLICITED STACK FRAME FOR A THREAD
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A stack frame of this structure is allocated whenever a thread enters the
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RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
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It goes on the current thread's stack.
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The solicited frame only includes registers that are required to be preserved
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by the callee according to the compiler's ABI conventions, some space to save
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the return address for returning to the caller, and the caller's PS register.
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For Windowed ABI, this stack frame includes the caller's base save area.
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Note on XT_SOL_EXIT field:
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It is necessary to distinguish a solicited from an interrupt stack frame.
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This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
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always at the same offset (0). It can be written with a code (usually 0)
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to distinguish a solicted frame from an interrupt frame. An RTOS port may
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opt to ignore this field if it has another way of distinguishing frames.
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-------------------------------------------------------------------------------
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*/
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STRUCT_BEGIN
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#ifdef __XTENSA_CALL0_ABI__
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STRUCT_FIELD( long,
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4,
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XT_SOL_EXIT,
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exit )
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STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
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STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
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STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
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STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
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@ -216,7 +209,7 @@ STRUCT_BEGIN
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STRUCT_FIELD (long, 4, XT_SOL_A13, a13)
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STRUCT_FIELD (long, 4, XT_SOL_A14, a14)
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STRUCT_FIELD (long, 4, XT_SOL_A15, a15)
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#else /* ifdef __XTENSA_CALL0_ABI__ */
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#else
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STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
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STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
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STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
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@ -225,7 +218,7 @@ STRUCT_BEGIN
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STRUCT_FIELD (long, 4, XT_SOL_A1, a1)
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STRUCT_FIELD (long, 4, XT_SOL_A2, a2)
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STRUCT_FIELD (long, 4, XT_SOL_A3, a3)
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#endif /* ifdef __XTENSA_CALL0_ABI__ */
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#endif
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STRUCT_END(XtSolFrame)
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/* Size of solicited stack frame */
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@ -233,65 +226,65 @@ STRUCT_END( XtSolFrame )
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/*
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* -------------------------------------------------------------------------------
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* CO-PROCESSOR STATE SAVE AREA FOR A THREAD
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*
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* The RTOS must provide an area per thread to save the state of co-processors
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* when that thread does not have control. Co-processors are context-switched
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* lazily (on demand) only when a new thread uses a co-processor instruction,
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* otherwise a thread retains ownership of the co-processor even when it loses
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* control of the processor. An Xtensa co-processor exception is triggered when
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* any co-processor instruction is executed by a thread that is not the owner,
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* and the context switch of that co-processor is then peformed by the handler.
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* Ownership represents which thread's state is currently in the co-processor.
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*
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* Co-processors may not be used by interrupt or exception handlers. If an
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* co-processor instruction is executed by an interrupt or exception handler,
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* the co-processor exception handler will trigger a kernel panic and freeze.
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* This restriction is introduced to reduce the overhead of saving and restoring
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* co-processor state (which can be quite large) and in particular remove that
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* overhead from interrupt handlers.
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*
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* The co-processor state save area may be in any convenient per-thread location
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* such as in the thread control block or above the thread stack area. It need
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* not be in the interrupt stack frame since interrupts don't use co-processors.
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*
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* Along with the save area for each co-processor, two bitmasks with flags per
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* co-processor (laid out as in the CPENABLE reg) help manage context-switching
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* co-processors as efficiently as possible:
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*
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* XT_CPENABLE
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* The contents of a non-running thread's CPENABLE register.
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* It represents the co-processors owned (and whose state is still needed)
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* by the thread. When a thread is preempted, its CPENABLE is saved here.
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* When a thread solicits a context-swtich, its CPENABLE is cleared - the
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* compiler has saved the (caller-saved) co-proc state if it needs to.
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* When a non-running thread loses ownership of a CP, its bit is cleared.
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* When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
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* Avoids co-processor exceptions when no change of ownership is needed.
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*
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* XT_CPSTORED
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* A bitmask with the same layout as CPENABLE, a bit per co-processor.
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* Indicates whether the state of each co-processor is saved in the state
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* save area. When a thread enters the kernel, only the state of co-procs
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* still enabled in CPENABLE is saved. When the co-processor exception
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* handler assigns ownership of a co-processor to a thread, it restores
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* the saved state only if this bit is set, and clears this bit.
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*
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* XT_CP_CS_ST
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* A bitmask with the same layout as CPENABLE, a bit per co-processor.
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* Indicates whether callee-saved state is saved in the state save area.
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* Callee-saved state is saved by itself on a solicited context switch,
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* and restored when needed by the coprocessor exception handler.
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* Unsolicited switches will cause the entire coprocessor to be saved
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* when necessary.
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*
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* XT_CP_ASA
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* Pointer to the aligned save area. Allows it to be aligned more than
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* the overall save area (which might only be stack-aligned or TCB-aligned).
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* Especially relevant for Xtensa cores configured with a very large data
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* path that requires alignment greater than 16 bytes (ABI stack alignment).
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* -------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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CO-PROCESSOR STATE SAVE AREA FOR A THREAD
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The RTOS must provide an area per thread to save the state of co-processors
|
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when that thread does not have control. Co-processors are context-switched
|
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lazily (on demand) only when a new thread uses a co-processor instruction,
|
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otherwise a thread retains ownership of the co-processor even when it loses
|
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control of the processor. An Xtensa co-processor exception is triggered when
|
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any co-processor instruction is executed by a thread that is not the owner,
|
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and the context switch of that co-processor is then peformed by the handler.
|
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Ownership represents which thread's state is currently in the co-processor.
|
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Co-processors may not be used by interrupt or exception handlers. If an
|
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co-processor instruction is executed by an interrupt or exception handler,
|
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the co-processor exception handler will trigger a kernel panic and freeze.
|
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This restriction is introduced to reduce the overhead of saving and restoring
|
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co-processor state (which can be quite large) and in particular remove that
|
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overhead from interrupt handlers.
|
||||
|
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The co-processor state save area may be in any convenient per-thread location
|
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such as in the thread control block or above the thread stack area. It need
|
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not be in the interrupt stack frame since interrupts don't use co-processors.
|
||||
|
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Along with the save area for each co-processor, two bitmasks with flags per
|
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co-processor (laid out as in the CPENABLE reg) help manage context-switching
|
||||
co-processors as efficiently as possible:
|
||||
|
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XT_CPENABLE
|
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The contents of a non-running thread's CPENABLE register.
|
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It represents the co-processors owned (and whose state is still needed)
|
||||
by the thread. When a thread is preempted, its CPENABLE is saved here.
|
||||
When a thread solicits a context-swtich, its CPENABLE is cleared - the
|
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compiler has saved the (caller-saved) co-proc state if it needs to.
|
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When a non-running thread loses ownership of a CP, its bit is cleared.
|
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When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
|
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Avoids co-processor exceptions when no change of ownership is needed.
|
||||
|
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XT_CPSTORED
|
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A bitmask with the same layout as CPENABLE, a bit per co-processor.
|
||||
Indicates whether the state of each co-processor is saved in the state
|
||||
save area. When a thread enters the kernel, only the state of co-procs
|
||||
still enabled in CPENABLE is saved. When the co-processor exception
|
||||
handler assigns ownership of a co-processor to a thread, it restores
|
||||
the saved state only if this bit is set, and clears this bit.
|
||||
|
||||
XT_CP_CS_ST
|
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A bitmask with the same layout as CPENABLE, a bit per co-processor.
|
||||
Indicates whether callee-saved state is saved in the state save area.
|
||||
Callee-saved state is saved by itself on a solicited context switch,
|
||||
and restored when needed by the coprocessor exception handler.
|
||||
Unsolicited switches will cause the entire coprocessor to be saved
|
||||
when necessary.
|
||||
|
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XT_CP_ASA
|
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Pointer to the aligned save area. Allows it to be aligned more than
|
||||
the overall save area (which might only be stack-aligned or TCB-aligned).
|
||||
Especially relevant for Xtensa cores configured with a very large data
|
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path that requires alignment greater than 16 bytes (ABI stack alignment).
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
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#if XCHAL_CP_NUM > 0
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|
@ -314,16 +307,16 @@ STRUCT_END( XtSolFrame )
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#define XT_CP_ASA 8 /* (4 bytes) ptr to aligned save area */
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/* Overall size allows for dynamic alignment: */
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#define XT_CP_SIZE (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
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#else /* if XCHAL_CP_NUM > 0 */
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#else
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#define XT_CP_SIZE 0
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#endif /* if XCHAL_CP_NUM > 0 */
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#endif
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/*
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* Macro to get the current core ID. Only uses the reg given as an argument.
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* Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0)
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* and 0xABAB on the APP CPU (1). We can distinguish between the two by checking
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* bit 13: it's 1 on the APP and 0 on the PRO processor.
|
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Macro to get the current core ID. Only uses the reg given as an argument.
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Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0)
|
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and 0xABAB on the APP CPU (1). We can distinguish between the two by checking
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bit 13: it's 1 on the APP and 0 on the PRO processor.
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*/
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#ifdef __ASSEMBLER__
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.macro getcoreid reg
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|
|
@ -336,20 +329,20 @@ STRUCT_END( XtSolFrame )
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#define CORE_ID_APP 0xABAB
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|
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/*
|
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* -------------------------------------------------------------------------------
|
||||
* MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
|
||||
*
|
||||
* Convenient where the frame size requirements are the same for both ABIs.
|
||||
* ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
|
||||
* ENTRY0, RET0 are for frameless functions (no locals, no calls).
|
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*
|
||||
* where size = size of stack frame in bytes (must be >0 and aligned to 16).
|
||||
* For framed functions the frame is created and the return address saved at
|
||||
* base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
|
||||
* For frameless functions, there is no frame and return address remains in a0.
|
||||
* Note: Because CPP macros expand to a single line, macros requiring multi-line
|
||||
* expansions are implemented as assembler macros.
|
||||
* -------------------------------------------------------------------------------
|
||||
-------------------------------------------------------------------------------
|
||||
MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
|
||||
|
||||
Convenient where the frame size requirements are the same for both ABIs.
|
||||
ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
|
||||
ENTRY0, RET0 are for frameless functions (no locals, no calls).
|
||||
|
||||
where size = size of stack frame in bytes (must be >0 and aligned to 16).
|
||||
For framed functions the frame is created and the return address saved at
|
||||
base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
|
||||
For frameless functions, there is no frame and return address remains in a0.
|
||||
Note: Because CPP macros expand to a single line, macros requiring multi-line
|
||||
expansions are implemented as assembler macros.
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
|
|
@ -368,15 +361,18 @@ STRUCT_END( XtSolFrame )
|
|||
ret
|
||||
.endm
|
||||
#define RET0 ret
|
||||
#else /* ifdef __XTENSA_CALL0_ABI__ */
|
||||
#else
|
||||
/* Windowed */
|
||||
#define ENTRY(sz) entry sp, sz
|
||||
#define ENTRY0 entry sp, 0x10
|
||||
#define RET(sz) retw
|
||||
#define RET0 retw
|
||||
#endif /* ifdef __XTENSA_CALL0_ABI__ */
|
||||
#endif /* ifdef __ASSEMBLER__ */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* XTENSA_CONTEXT_H */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue