mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other. + Handle external interrupts (working with Renode emulator). + The _sp linker variable is now called __freertos_irq_stack_top.
This commit is contained in:
Richard Barry
parent
866635d2ad
commit
7cc42b2ab6
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@ -39,9 +39,8 @@
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static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
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const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 1 ] );
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#else
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#warning What should _sp be named?
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extern const uint32_t _sp[];
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const uint32_t xISRStackTop = ( uint32_t ) _sp;
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extern const uint32_t __freertos_irq_stack_top[];
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const uint32_t xISRStackTop = ( uint32_t ) __freertos_irq_stack_top;
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#endif
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/*
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@ -227,9 +226,6 @@ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLI
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/* Prepare the time to use after the next tick interrupt. */
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ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;
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/* Enable timer interrupt. */
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__asm volatile( "csrs mie, %0" :: "r"(0x80) ); /* 1<<7 for timer interrupt. */
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}
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/*-----------------------------------------------------------*/
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@ -254,6 +250,12 @@ extern void xPortStartFirstTask( void );
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#endif
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vPortSetupTimerInterrupt();
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/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
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for external interrupt. _RB_ What happens here when mtime is not present as
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with pulpino? */
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__asm volatile( "csrs mie, %0" :: "r"(0x880) );
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xPortStartFirstTask();
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/* Should not get here as after calling xPortStartFirstTask() only tasks
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@ -271,3 +273,4 @@ void vPortEndScheduler( void )
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@ -50,49 +50,7 @@
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.extern pullNextTime
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.extern ulTimerIncrementsForOneTick
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.extern xISRStackTop
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/*-----------------------------------------------------------*/
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.align 8
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xPortStartFirstTask:
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la t0, vPortTrapHandler
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csrw mtvec, t0
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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csrs mstatus, 8 /* Enable machine interrupts. */
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ret
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.extern vPortHandleInterrupt
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/*-----------------------------------------------------------*/
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@ -152,7 +110,7 @@ test_if_timer:
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lui t0, 0x80000
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addi t1,t0, 7 /* 0x80000007 == machine timer interrupt. */
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bne a0, t1, as_yet_unhandled
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bne a0, t1, test_if_external_interrupt
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lw t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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lw t1, pullNextTime /* Load the address of ullNextTime into t1. */
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@ -172,9 +130,15 @@ test_if_timer:
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jal vTaskSwitchContext
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j processed_source
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as_yet_unhandled:
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// ebreak /* External interrupt? */
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j as_yet_unhandled
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test_if_external_interrupt:
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addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
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bne a0, t1, is_exception /* Only thing left it can be. */
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jal vPortHandleInterrupt
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j processed_source
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is_exception:
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ebreak
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j is_exception
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processed_source:
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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@ -219,5 +183,48 @@ processed_source:
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addi sp, sp, CONTEXT_SIZE
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mret
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/*-----------------------------------------------------------*/
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.align 8
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xPortStartFirstTask:
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la t0, vPortTrapHandler
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csrw mtvec, t0
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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csrs mstatus, 8 /* Enable machine interrupts. */
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ret
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/*-----------------------------------------------------------*/
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@ -43,10 +43,6 @@ extern "C" {
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*-----------------------------------------------------------
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*/
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#ifdef __riscv64
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#error This is the RV32 port that supports 32-bit cores only.
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#endif
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/* Type definitions. */
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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@ -65,7 +61,12 @@ not need to be guarded with a critical section. */
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 16
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#ifdef __riscv64
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#error This is the RV32 port that has not yet been adapted for 64.
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#define portBYTE_ALIGNMENT 16
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#else
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#define portBYTE_ALIGNMENT 8
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#endif
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/*-----------------------------------------------------------*/
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@ -79,15 +80,13 @@ extern void vTaskSwitchContext( void );
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/* Critical section management. */
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#define portCRITICAL_NESTING_IN_TCB 1
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extern int vPortSetInterruptMask( void );
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extern void vPortClearInterruptMask( int );
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extern void vTaskEnterCritical( void );
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extern void vTaskExitCritical( void );
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#define portSET_INTERRUPT_MASK_FROM_ISR() 0
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
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#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" ); __asm volatile( "fence" )
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#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" ); __asm volatile( "fence" )
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#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" )
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#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" )
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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