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Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other. + Handle external interrupts (working with Renode emulator). + The _sp linker variable is now called __freertos_irq_stack_top.
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3 changed files with 71 additions and 62 deletions
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@ -43,10 +43,6 @@ extern "C" {
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*-----------------------------------------------------------
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*/
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#ifdef __riscv64
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#error This is the RV32 port that supports 32-bit cores only.
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#endif
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/* Type definitions. */
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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@ -65,7 +61,12 @@ not need to be guarded with a critical section. */
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 16
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#ifdef __riscv64
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#error This is the RV32 port that has not yet been adapted for 64.
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#define portBYTE_ALIGNMENT 16
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#else
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#define portBYTE_ALIGNMENT 8
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#endif
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/*-----------------------------------------------------------*/
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@ -79,15 +80,13 @@ extern void vTaskSwitchContext( void );
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/* Critical section management. */
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#define portCRITICAL_NESTING_IN_TCB 1
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extern int vPortSetInterruptMask( void );
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extern void vPortClearInterruptMask( int );
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extern void vTaskEnterCritical( void );
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extern void vTaskExitCritical( void );
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#define portSET_INTERRUPT_MASK_FROM_ISR() 0
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
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#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" ); __asm volatile( "fence" )
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#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" ); __asm volatile( "fence" )
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#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" )
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#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" )
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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