len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-04-20 05:21:59 -04:00
Code Issues Packages Projects Releases Wiki Activity

Continued V850 development.

Browse source
This commit is contained in:
Richard Barry 2009-01-29 16:20:25 +00:00
parent 42d07bc94b
commit 77fbf587ee
3 changed files with 19 additions and 79 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
Source/portable/IAR/V850ES_Fx3/port.c
View file

@ -184,11 +184,19 @@ static void prvSetupTimerInterrupt( void )
TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */
TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
#ifdef __IAR_V850ES_Fx3__
{
/* Set INTTM0EQ0 level 5 priority */
TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
}
#else
{
TM0CMP0 = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
}
#endif
TM0EQIC0 &= 0xF8;
TM0CTL0 = 0x00;
TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */
TM0CE = 1; /* TMM0 operation enable */

24
Source/portable/IAR/V850ES_Fx3/portasm_Fx3.s85
View file

@ -221,29 +221,6 @@ vPortStart:
; Output: NONE
;------------------------------------------------------------------------------
#if 0
RSEG CODE:CODE
vPortYield:
DI
ADD -0x0C,sp ; prepare stack to save necessary values
st.w lp,8[sp] ; save LP to stack
st.w lp,4[sp] ; save LP to stack
stsr 5,lp
st.w lp,0[sp] ; save PSW to stack
portSAVE_CONTEXT ; Save the context of the current task.
jarl vTaskSwitchContext,lp ; Call the scheduler.
portRESTORE_CONTEXT ; Restore the context of whichever task the ...
ld.w 0[sp],lp ; restore EIPSW
ldsr lp,1
ld.w 4[sp],lp ; restore PIPC
ldsr lp,0
ld.w 8[sp],lp ; restore LP
add 0x0C,sp
RETI
#else
RSEG CODE:CODE
vPortYield:
@ -266,7 +243,6 @@ vPortYield:
RETI
#endif
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------

54
Source/portable/IAR/V850ES_Jx3/portasm_Jx3.s85
View file

@ -61,22 +61,13 @@
#define CG_SECURITY8 0FFH
#define CG_SECURITY9 0FFH
; Option Byte definitions
;------------------------------------------------------------------------------
#define CG_OPTION7A 0x00
#define CG_OPTION7B 0x04
#define OPT7C 0x00
#define OPT7D 0x00
#define OPT7E 0x00
#define OPT7F 0x00
; Tick ISR Prototype
;------------------------------------------------------------------------------
PUBWEAK `??MD_INTTM0EQ0??INTVEC 608`
PUBWEAK `??MD_INTTM0EQ0??INTVEC 640`
PUBLIC MD_INTTM0EQ0
MD_INTTM0EQ0 SYMBOL "MD_INTTM0EQ0"
`??MD_INTTM0EQ0??INTVEC 608` SYMBOL "??INTVEC 608", MD_INTTM0EQ0
`??MD_INTTM0EQ0??INTVEC 640` SYMBOL "??INTVEC 640", MD_INTTM0EQ0
;------------------------------------------------------------------------------
; portSAVE_CONTEXT MACRO
@ -221,29 +212,6 @@ vPortStart:
; Output: NONE
;------------------------------------------------------------------------------
#if 0
RSEG CODE:CODE
vPortYield:
DI
ADD -0x0C,sp ; prepare stack to save necessary values
st.w lp,8[sp] ; save LP to stack
st.w lp,4[sp] ; save LP to stack
stsr 5,lp
st.w lp,0[sp] ; save PSW to stack
portSAVE_CONTEXT ; Save the context of the current task.
jarl vTaskSwitchContext,lp ; Call the scheduler.
portRESTORE_CONTEXT ; Restore the context of whichever task the ...
ld.w 0[sp],lp ; restore EIPSW
ldsr lp,1
ld.w 4[sp],lp ; restore PIPC
ldsr lp,0
ld.w 8[sp],lp ; restore LP
add 0x0C,sp
RETI
#else
RSEG CODE:CODE
vPortYield:
@ -266,7 +234,6 @@ vPortYield:
RETI
#endif
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
@ -318,8 +285,8 @@ MD_INTTM0EQ0:
;------------------------------------------------------------------------------
COMMON INTVEC:CODE:ROOT(2)
ORG 608
`??MD_INTTM0EQ0??INTVEC 608`:
ORG 640
`??MD_INTTM0EQ0??INTVEC 640`:
JR MD_INTTM0EQ0
RSEG NEAR_ID:CONST:SORT:NOROOT(2)
@ -348,17 +315,6 @@ MD_INTTM0EQ0:
DB CG_SECURITY8
DB CG_SECURITY9
;------------------------------------------------------------------------------
; set microcontroller option bytes
COMMON INTVEC:CODE:ROOT(2)
ORG 7AH
`OPTBYTES`:
DB CG_OPTION7A
DB CG_OPTION7B
DB OPT7C
DB OPT7D
DB OPT7E
DB OPT7F
END