Continued V850 development.

This commit is contained in:
Richard Barry 2009-01-29 16:20:25 +00:00
parent 42d07bc94b
commit 77fbf587ee
3 changed files with 19 additions and 79 deletions

View file

@ -37,13 +37,13 @@
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
@ -184,11 +184,19 @@ static void prvSetupTimerInterrupt( void )
TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */
TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
/* Set INTTM0EQ0 level 5 priority */
#ifdef __IAR_V850ES_Fx3__
{
/* Set INTTM0EQ0 level 5 priority */
TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
}
#else
{
TM0CMP0 = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
}
#endif
TM0EQIC0 &= 0xF8;
TM0CTL0 = 0x00;
TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */
TM0CE = 1; /* TMM0 operation enable */

View file

@ -221,29 +221,6 @@ vPortStart:
; Output: NONE
;------------------------------------------------------------------------------
#if 0
RSEG CODE:CODE
vPortYield:
DI
ADD -0x0C,sp ; prepare stack to save necessary values
st.w lp,8[sp] ; save LP to stack
st.w lp,4[sp] ; save LP to stack
stsr 5,lp
st.w lp,0[sp] ; save PSW to stack
portSAVE_CONTEXT ; Save the context of the current task.
jarl vTaskSwitchContext,lp ; Call the scheduler.
portRESTORE_CONTEXT ; Restore the context of whichever task the ...
ld.w 0[sp],lp ; restore EIPSW
ldsr lp,1
ld.w 4[sp],lp ; restore PIPC
ldsr lp,0
ld.w 8[sp],lp ; restore LP
add 0x0C,sp
RETI
#else
RSEG CODE:CODE
vPortYield:
@ -266,7 +243,6 @@ vPortYield:
RETI
#endif
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------