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Changes to core code and port layer:

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+ Add configASSERT() into ARM Cortex-M ports to check the number of priority
      bit settings.
    + Clear the 'control' register before starting ARM Cortex-M4F ports in case
      the FPU is used before the scheduler is started.  This just saves a few
      bytes on the main stack as it prevents space being left for a later save
      of FPU registers.
    + Added xSemaphoreGetMutexHolderFromISR().
    + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.
This commit is contained in:
Richard Barry 2016-08-16 11:38:58 +00:00
parent bdbf347c22
commit 75ffac21d7
32 changed files with 1196 additions and 215 deletions
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33
FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
View file

@ -381,6 +381,24 @@ BaseType_t xPortStartScheduler( void )
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
}
#ifdef __NVIC_PRIO_BITS
{
/* Check the CMSIS configuration that defines the number of
priority bits matches the number of priority bits actually queried
from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
}
#endif
#ifdef configPRIO_BITS
{
/* Check the FreeRTOS configuration that defines the number of
priority bits matches the number of priority bits actually queried
from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
}
#endif
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
@ -426,11 +444,20 @@ __asm void prvStartFirstTask( void )
{
PRESERVE8
ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
/* Use the NVIC offset register to locate the stack. */
ldr r0, =0xE000ED08
ldr r0, [r0]
ldr r0, [r0]
msr msp, r0 /* Set the msp back to the start of the stack. */
cpsie i /* Globally enable interrupts. */
/* Set the msp back to the start of the stack. */
msr msp, r0
/* Clear the bit that indicates the FPU is in use in case the FPU was used
before the scheduler was started - which would otherwise result in the
unnecessary leaving of space in the SVC stack for lazy saving of FPU
registers. */
mov r0, #0
msr control, r0
/* Globally enable interrupts. */
cpsie i
cpsie f
dsb
isb

10
FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
View file

@ -179,7 +179,7 @@ typedef struct MPU_SETTINGS
#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET
#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
/*-----------------------------------------------------------*/
@ -273,7 +273,7 @@ static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
__asm
{
/* Set BASEPRI to 0 so no interrupts are masked. This function is only
used to lower the mask in an interrupt, so memory barriers are not
used to lower the mask in an interrupt, so memory barriers are not
used. */
msr basepri, #0
}
@ -326,10 +326,10 @@ BaseType_t xReturn;
portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
{
uint32_t ulReg;
if( xRunningPrivileged != pdTRUE )
if( xRunningPrivileged != pdTRUE )
{
__asm
__asm
{
mrs ulReg, control
orr ulReg, #1