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Changes to core code and port layer:
+ Add configASSERT() into ARM Cortex-M ports to check the number of priority bit settings. + Clear the 'control' register before starting ARM Cortex-M4F ports in case the FPU is used before the scheduler is started. This just saves a few bytes on the main stack as it prevents space being left for a later save of FPU registers. + Added xSemaphoreGetMutexHolderFromISR(). + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.
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32 changed files with 1196 additions and 215 deletions
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@ -285,11 +285,17 @@ void vPortSVCHandler( void )
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static void prvPortStartFirstTask( void )
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{
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/* Start the first task. This also clears the bit that indicates the FPU is
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in use in case the FPU was used before the scheduler was started - which
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would otherwise result in the unnecessary leaving of space in the SVC stack
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for lazy saving of FPU registers. */
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__asm volatile(
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" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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" ldr r0, [r0] \n"
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" ldr r0, [r0] \n"
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" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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" mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
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" msr control, r0 \n"
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" cpsie i \n" /* Globally enable interrupts. */
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" cpsie f \n"
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" dsb \n"
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@ -342,6 +348,24 @@ BaseType_t xPortStartScheduler( void )
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ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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}
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#ifdef __NVIC_PRIO_BITS
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{
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/* Check the CMSIS configuration that defines the number of
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priority bits matches the number of priority bits actually queried
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from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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}
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#endif
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#ifdef configPRIO_BITS
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{
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/* Check the FreeRTOS configuration that defines the number of
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priority bits matches the number of priority bits actually queried
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from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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}
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#endif
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/* Shift the priority group value back to its position within the AIRCR
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register. */
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ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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