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cortex-r82: Minor code improvements

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This commit includes minor code improvements to enhance readability
and maintainability of the Cortex-R82 port files. Changes include
refactoring variable names, optimizing comments, and improving code
structure without altering functionality.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
This commit is contained in:
Ahmed Ismail 2025-10-09 14:45:09 +01:00
parent a9b9085d7b
commit 7417c8338b
3 changed files with 155 additions and 129 deletions
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96
portable/GCC/ARM_CR82/port.c
View file

@ -229,7 +229,6 @@
* assembly code so is implemented in portASM.s.
*/
extern void vPortRestoreTaskContext( void );
extern void vGIC_EnableIRQ( uint32_t ulInterruptID );
extern void vGIC_SetPriority( uint32_t ulInterruptID, uint32_t ulPriority );
extern void vGIC_PowerUpRedistributor( void );
@ -238,6 +237,7 @@ extern void vGIC_EnableCPUInterface( void );
/*-----------------------------------------------------------*/
#if ( configNUMBER_OF_CORES == 1 )
PRIVILEGED_DATA volatile uint64_t ullCriticalNesting = 0ULL;
/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
@ -250,16 +250,25 @@ extern void vGIC_EnableCPUInterface( void );
/* Counts the interrupt nesting depth. A context switch is only performed if
* if the nesting depth is 0. */
PRIVILEGED_DATA uint64_t ullPortInterruptNesting = 0;
#else /* #if ( configNUMBER_OF_CORES == 1 ) */
PRIVILEGED_DATA volatile uint64_t ullCriticalNestings[ configNUMBER_OF_CORES ] = { 0 };
/* Flags to check if the secondary cores are ready. */
PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 };
/* Flag to signal that the primary core has done all the shared initialisations. */
PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0;
/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
* then floating point context must be saved and restored for the task. */
PRIVILEGED_DATA uint64_t ullPortTaskHasFPUContext[ configNUMBER_OF_CORES ] = { pdFALSE };
/* Set to 1 to pend a context switch from an ISR. */
PRIVILEGED_DATA uint64_t ullPortYieldRequired[ configNUMBER_OF_CORES ] = { pdFALSE };
/* Counts the interrupt nesting depth. A context switch is only performed if
* if the nesting depth is 0. */
PRIVILEGED_DATA uint64_t ullPortInterruptNestings[ configNUMBER_OF_CORES ] = { 0 };
#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
@ -1229,9 +1238,9 @@ BaseType_t xPortStartScheduler( void )
while( 1 )
{
BaseType_t xAllCoresReady = pdTRUE;
for( uint32_t ulCoreID = 0; ulCoreID < ( configNUMBER_OF_CORES - 1 ); ulCoreID++ )
for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ )
{
if( ucSecondaryCoresReadyFlags[ ulCoreID ] != pdTRUE )
if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE )
{
xAllCoresReady = pdFALSE;
break;
@ -1530,16 +1539,16 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
#if ( configNUMBER_OF_CORES > 1 )
/* Which core owns the lock? Keep in privileged, shareable RAM. */
PRIVILEGED_DATA volatile uint64_t ucOwnedByCore[ portMAX_CORE_COUNT ];
PRIVILEGED_DATA volatile uint64_t ullOwnedByCore[ portMAX_CORE_COUNT ];
/* Lock count a core owns. */
PRIVILEGED_DATA volatile uint64_t ucRecursionCountByLock[ eLockCount ];
PRIVILEGED_DATA volatile uint64_t ullRecursionCountByLock[ eLockCount ];
/* Index 0 is used for ISR lock and Index 1 is used for task lock. */
PRIVILEGED_DATA uint32_t ulGateWord[ eLockCount ];
void vInterruptCore( uint32_t ulInterruptID, uint32_t ulCoreID )
void vInterruptCore( uint32_t ulInterruptID, uint8_t ucCoreID )
{
uint64_t ulRegVal = 0;
uint32_t ulCoreMask = ( 1UL << ulCoreID );
uint32_t ulCoreMask = ( 1UL << ucCoreID );
ulRegVal |= ( (ulCoreMask & 0xFFFF) | ( ( ulInterruptID & 0xF ) << 24U ) );
__asm volatile (
"str x0, [ sp, #-0x10 ]! \n"
@ -1556,6 +1565,7 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
static inline void prvSpinUnlock( uint32_t * ulLock )
{
/* Conservative unlock: preserve original barriers for broad HW/FVP. */
__asm volatile (
"dmb sy \n"
"mov w1, #0 \n"
@ -1573,22 +1583,30 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
static inline uint32_t prvSpinTrylock( uint32_t * ulLock )
{
/*
* Conservative LDXR/STXR trylock:
* - Return 1 immediately if busy, clearing exclusive state (CLREX).
* - Retry STXR only on spurious failure when observed free.
* - DMB on success to preserve expected acquire semantics.
*/
register uint32_t ulRet;
/* Try to acquire spinlock; caller is responsible for further barriers. */
__asm volatile (
"1: \n"
"ldxr w1, [%x1] \n"
"cmp w1, #1\n"
"beq 2f\n"
"cbnz w1, 2f \n" /* Busy -> return 1 */
"mov w2, #1 \n"
"stxr w1, w2, [%x1]\n"
"cmp w1, #0\n"
"bne 1b\n"
"stxr w3, w2, [%x1] \n" /* w3 = status */
"cbnz w3, 1b \n" /* Retry on STXR failure */
"dmb sy \n" /* Acquire barrier on success */
"mov %w0, #0 \n" /* Success */
"b 3f \n"
"2: \n"
"mov %w0, w1\n"
"clrex \n" /* Clear monitor when busy */
"mov %w0, #1 \n" /* Busy */
"3: \n"
: "=r" ( ulRet )
: "r" ( ulLock )
: "memory", "w1", "w2"
: "memory", "w1", "w2", "w3"
);
return ulRet;
@ -1615,12 +1633,12 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
/*-----------------------------------------------------------*/
void vPortRecursiveLock( BaseType_t xCoreID,
void vPortRecursiveLock( uint8_t ucCoreID,
ePortRTOSLock eLockNum,
BaseType_t uxAcquire )
{
/* Validate the core ID and lock number. */
configASSERT( xCoreID < portMAX_CORE_COUNT );
configASSERT( ucCoreID < portMAX_CORE_COUNT );
configASSERT( eLockNum < eLockCount );
uint32_t ulLockBit = 1u << eLockNum;
@ -1636,10 +1654,10 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 )
{
/* Check if the core owns the spinlock. */
if( prvGet64( &ucOwnedByCore[ xCoreID ] ) & ulLockBit )
if( prvGet64( &ullOwnedByCore[ ucCoreID ] ) & ulLockBit )
{
configASSERT( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) != 255u );
prvSet64( &ucRecursionCountByLock[ eLockNum ], ( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) + 1 ) );
configASSERT( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) != 255u );
prvSet64( &ullRecursionCountByLock[ eLockNum ], ( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) + 1 ) );
return;
}
@ -1650,12 +1668,20 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 )
{
/* Follow Arm's recommended way of sleeping
* sevl is used to prime the wait loop,
* the first wfe wakes immediately as sevl has set the flag
* the second wfe sleeps the core. This way the core is ensured
* to sleep.
* sevl is used to prime the wait loop.
* The first wfe wakes immediately because sevl has set the flag.
* Check the lock, if it's not available, issue a second wfe to sleep.
* This guarantees the core actually goes to sleep.
*/
__asm volatile ( "sevl; wfe; wfe" );
__asm volatile (
"sevl \n"
"1: wfe \n"
"ldr w2, [%x0] \n"
"cbnz w2, 1b \n"
:
: "r" ( &ulGateWord[ eLockNum ] )
: "memory", "w2"
);
}
}
@ -1663,26 +1689,26 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
__asm__ __volatile__ ( "dmb sy" ::: "memory" );
/* Assert the lock count is 0 when the spinlock is free and is acquired. */
configASSERT( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) == 0 );
configASSERT( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) == 0 );
/* Set lock count as 1. */
prvSet64( &ucRecursionCountByLock[ eLockNum ], 1 );
/* Set ucOwnedByCore. */
prvSet64( &ucOwnedByCore[ xCoreID ], ( prvGet64( &ucOwnedByCore[ xCoreID ] ) | ulLockBit ) );
prvSet64( &ullRecursionCountByLock[ eLockNum ], 1 );
/* Set ullOwnedByCore. */
prvSet64( &ullOwnedByCore[ ucCoreID ], ( prvGet64( &ullOwnedByCore[ ucCoreID ] ) | ulLockBit ) );
}
/* Lock release. */
else
{
/* Assert the lock is not free already. */
configASSERT( ( prvGet64( &ucOwnedByCore[ xCoreID ] ) & ulLockBit ) != 0 );
configASSERT( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) != 0 );
configASSERT( ( prvGet64( &ullOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 );
configASSERT( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) != 0 );
/* Reduce ucRecursionCountByLock by 1. */
prvSet64( &ucRecursionCountByLock[ eLockNum ], ( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) - 1 ) );
/* Reduce ullRecursionCountByLock by 1. */
prvSet64( &ullRecursionCountByLock[ eLockNum ], ( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) - 1 ) );
if( !prvGet64( &ucRecursionCountByLock[ eLockNum ] ) )
if( !prvGet64( &ullRecursionCountByLock[ eLockNum ] ) )
{
prvSet64( &ucOwnedByCore[ xCoreID ], ( prvGet64( &ucOwnedByCore[ xCoreID ] ) & ~ulLockBit ) );
prvSet64( &ullOwnedByCore[ ucCoreID ], ( prvGet64( &ullOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) );
prvSpinUnlock( &ulGateWord[ eLockNum ] );
/* Add barrier to ensure lock status is reflected before we proceed. */
__asm__ __volatile__ ( "dmb sy" ::: "memory" );

7
portable/GCC/ARM_CR82/portASM.S
View file

@ -369,8 +369,10 @@ LDP Q0, Q1, [ SP ], # 0x20
#endif /* #if ( configENABLE_MPU == 1 ) */
MSR SPSEL, # 0
/* Save the entire context. */
saveallgpregisters
/* Save the SPSR and ELR values. */
MRS X3, SPSR_EL1
MRS X2, ELR_EL1
@ -390,13 +392,14 @@ AND X1, X1, # 0xff /* Extract Aff0 (core ID). */
LSL X1, X1, # 3 /* Multiply core ID by pointer size (8 bytes). */
ADD X0, X0, X1 /* Add offset to base address. */
#endif
LDR X3, [ X0 ]
/* Save the FPU context indicator. */
adrp X0, ullPortTaskHasFPUContext
add X0, X0, :lo12:ullPortTaskHasFPUContext /* X0 = &ullPortTaskHasFPUContext */
#if configNUMBER_OF_CORES > 1
#if ( configNUMBER_OF_CORES > 1 )
ADD X0, X0, X1 /* Add to the base of the FPU array. */
#endif
LDR X2, [ X0 ]
@ -1039,12 +1042,12 @@ ISB SY
/* Restore the interrupt ID value. */
LDP X0, X1, [ SP ], # 0x10
/* End IRQ processing by writing interrupt ID value to the EOI register. */
MSR ICC_EOIR1_EL1, X0
/* Restore the critical nesting count. */
LDP X1, X5, [ SP ], # 0x10
STR X1, [ X5 ]
/* Has interrupt nesting unwound? */

29
portable/GCC/ARM_CR82/portmacro.h
View file

@ -139,15 +139,14 @@
extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
extern void vPortClearInterruptMaskFromISR( UBaseType_t uxNewMaskValue );
extern void vInterruptCore( uint32_t ulInterruptID, uint32_t ulCoreID );
extern void vInterruptCore( uint32_t ulInterruptID, uint8_t ucCoreID );
#endif /* if !defined(__ASSEMBLER__) */
/* Use SVC so this is safe from EL0. EL1 sites in the port use direct MSR. */\
/* Use SVC so this is safe from EL0. EL1 sites in the port use direct MSR. */
#define portDISABLE_INTERRUPTS() __asm volatile ( "SVC %0" : : "i" ( portSVC_DISABLE_INTERRUPTS ) : "memory" )
#define portENABLE_INTERRUPTS() __asm volatile ( "SVC %0" : : "i" ( portSVC_ENABLE_INTERRUPTS ) : "memory" )
/* In all GICs 255 can be written to the priority mask register to unmask all
* (but the lowest) interrupt priority. */
#define portUNMASK_VALUE ( 0xFFUL )
@ -200,6 +199,7 @@
* nothing to prevent it from being called accidentally. */
#define vPortTaskUsesFPU()
#endif
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
@ -216,8 +216,6 @@
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
/*-----------------------------------------------------------*/
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
@ -266,7 +264,7 @@
} ePortRTOSLock;
extern volatile uint64_t ullCriticalNestings[ configNUMBER_OF_CORES ];
extern void vPortRecursiveLock( BaseType_t xCoreID,
extern void vPortRecursiveLock( uint8_t ucCoreID,
ePortRTOSLock eLockNum,
BaseType_t uxAcquire );
extern uint8_t ucPortGetCoreID( void );
@ -281,18 +279,17 @@
#define portGET_CORE_ID_FROM_ISR() ucPortGetCoreIDFromIsr()
/* Use SGI 0 as the yield core interrupt. */
#define portYIELD_CORE( xCoreID ) vInterruptCore( portYIELD_CORE_INT_ID, ( uint32_t ) xCoreID )
#define portYIELD_CORE( xCoreID ) vInterruptCore( portYIELD_CORE_INT_ID, ( uint8_t ) xCoreID )
#define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eIsrLock, pdFALSE )
#define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eIsrLock, pdTRUE )
#define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE )
#define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE )
#define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eTaskLock, pdFALSE )
#define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eTaskLock, pdTRUE )
#define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( xCoreID ) ] )
#define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ullCriticalNestings[ ( xCoreID ) ] = ( x ) )
#define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( xCoreID ) ]++ )
#define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( xCoreID ) ]-- )
#define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE )
#define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE )
#define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ] )
#define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) )
#define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ]++ )
#define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ]-- )
#endif /* configNUMBER_OF_CORES > 1 */