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cortex-r82: Minor code improvements
This commit includes minor code improvements to enhance readability and maintainability of the Cortex-R82 port files. Changes include refactoring variable names, optimizing comments, and improving code structure without altering functionality. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
This commit is contained in:
Ahmed Ismail
parent
a9b9085d7b
commit
7417c8338b
3 changed files with 155 additions and 129 deletions
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@ -229,7 +229,6 @@
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* assembly code so is implemented in portASM.s.
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*/
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extern void vPortRestoreTaskContext( void );
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extern void vGIC_EnableIRQ( uint32_t ulInterruptID );
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extern void vGIC_SetPriority( uint32_t ulInterruptID, uint32_t ulPriority );
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extern void vGIC_PowerUpRedistributor( void );
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@ -238,28 +237,38 @@ extern void vGIC_EnableCPUInterface( void );
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/*-----------------------------------------------------------*/
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#if ( configNUMBER_OF_CORES == 1 )
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PRIVILEGED_DATA volatile uint64_t ullCriticalNesting = 0ULL;
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/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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* then floating point context must be saved and restored for the task. */
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/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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* then floating point context must be saved and restored for the task. */
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PRIVILEGED_DATA uint64_t ullPortTaskHasFPUContext = pdFALSE;
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/* Set to 1 to pend a context switch from an ISR. */
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/* Set to 1 to pend a context switch from an ISR. */
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PRIVILEGED_DATA uint64_t ullPortYieldRequired = pdFALSE;
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/* Counts the interrupt nesting depth. A context switch is only performed if
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* if the nesting depth is 0. */
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/* Counts the interrupt nesting depth. A context switch is only performed if
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* if the nesting depth is 0. */
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PRIVILEGED_DATA uint64_t ullPortInterruptNesting = 0;
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#else /* #if ( configNUMBER_OF_CORES == 1 ) */
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PRIVILEGED_DATA volatile uint64_t ullCriticalNestings[ configNUMBER_OF_CORES ] = { 0 };
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/* Flags to check if the secondary cores are ready. */
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PRIVILEGED_DATA volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 };
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/* Flag to signal that the primary core has done all the shared initialisations. */
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PRIVILEGED_DATA volatile uint8_t ucPrimaryCoreInitDoneFlag = 0;
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/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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* then floating point context must be saved and restored for the task. */
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PRIVILEGED_DATA uint64_t ullPortTaskHasFPUContext[ configNUMBER_OF_CORES ] = { pdFALSE };
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/* Set to 1 to pend a context switch from an ISR. */
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PRIVILEGED_DATA uint64_t ullPortYieldRequired[ configNUMBER_OF_CORES ] = { pdFALSE };
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/* Counts the interrupt nesting depth. A context switch is only performed if
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* if the nesting depth is 0. */
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PRIVILEGED_DATA uint64_t ullPortInterruptNestings[ configNUMBER_OF_CORES ] = { 0 };
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#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
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@ -1168,12 +1177,12 @@ BaseType_t xPortStartScheduler( void )
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volatile uint8_t ucMaxPriorityValue;
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/* Determine how many priority bits are implemented in the GIC.
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*
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* Save the interrupt priority value that is about to be clobbered. */
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*
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* Save the interrupt priority value that is about to be clobbered. */
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ucOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to
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* all possible bits. */
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* all possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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@ -1186,12 +1195,12 @@ BaseType_t xPortStartScheduler( void )
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}
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/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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* value. */
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* value. */
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configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
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/* Restore the clobbered interrupt priority register to its original
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* value. */
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* value. */
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*pucFirstUserPriorityRegister = ucOriginalPriority;
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}
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#endif /* configASSERT_DEFINED */
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@ -1229,9 +1238,9 @@ BaseType_t xPortStartScheduler( void )
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while( 1 )
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{
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BaseType_t xAllCoresReady = pdTRUE;
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for( uint32_t ulCoreID = 0; ulCoreID < ( configNUMBER_OF_CORES - 1 ); ulCoreID++ )
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for( uint8_t ucCoreID = 0; ucCoreID < ( configNUMBER_OF_CORES - 1 ); ucCoreID++ )
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{
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if( ucSecondaryCoresReadyFlags[ ulCoreID ] != pdTRUE )
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if( ucSecondaryCoresReadyFlags[ ucCoreID ] != pdTRUE )
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{
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xAllCoresReady = pdFALSE;
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break;
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@ -1530,16 +1539,16 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
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#if ( configNUMBER_OF_CORES > 1 )
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/* Which core owns the lock? Keep in privileged, shareable RAM. */
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PRIVILEGED_DATA volatile uint64_t ucOwnedByCore[ portMAX_CORE_COUNT ];
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PRIVILEGED_DATA volatile uint64_t ullOwnedByCore[ portMAX_CORE_COUNT ];
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/* Lock count a core owns. */
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PRIVILEGED_DATA volatile uint64_t ucRecursionCountByLock[ eLockCount ];
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PRIVILEGED_DATA volatile uint64_t ullRecursionCountByLock[ eLockCount ];
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/* Index 0 is used for ISR lock and Index 1 is used for task lock. */
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PRIVILEGED_DATA uint32_t ulGateWord[ eLockCount ];
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void vInterruptCore( uint32_t ulInterruptID, uint32_t ulCoreID )
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void vInterruptCore( uint32_t ulInterruptID, uint8_t ucCoreID )
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{
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uint64_t ulRegVal = 0;
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uint32_t ulCoreMask = ( 1UL << ulCoreID );
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uint32_t ulCoreMask = ( 1UL << ucCoreID );
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ulRegVal |= ( (ulCoreMask & 0xFFFF) | ( ( ulInterruptID & 0xF ) << 24U ) );
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__asm volatile (
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"str x0, [ sp, #-0x10 ]! \n"
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@ -1556,13 +1565,14 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
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static inline void prvSpinUnlock( uint32_t * ulLock )
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{
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/* Conservative unlock: preserve original barriers for broad HW/FVP. */
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__asm volatile (
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"dmb sy\n"
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"mov w1, #0\n"
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"str w1, [%x0]\n"
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"sev\n"
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"dsb sy\n"
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"isb sy\n"
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"dmb sy \n"
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"mov w1, #0 \n"
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"str w1, [%x0] \n"
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"sev \n"
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"dsb sy \n"
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"isb sy \n"
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:
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: "r" ( ulLock )
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: "memory", "w1"
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@ -1573,22 +1583,30 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
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static inline uint32_t prvSpinTrylock( uint32_t * ulLock )
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{
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/*
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* Conservative LDXR/STXR trylock:
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* - Return 1 immediately if busy, clearing exclusive state (CLREX).
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* - Retry STXR only on spurious failure when observed free.
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* - DMB on success to preserve expected acquire semantics.
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*/
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register uint32_t ulRet;
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/* Try to acquire spinlock; caller is responsible for further barriers. */
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__asm volatile (
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"1:\n"
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"ldxr w1, [%x1]\n"
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"cmp w1, #1\n"
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"beq 2f\n"
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"mov w2, #1\n"
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"stxr w1, w2, [%x1]\n"
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"cmp w1, #0\n"
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"bne 1b\n"
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"2:\n"
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"mov %w0, w1\n"
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"1: \n"
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"ldxr w1, [%x1] \n"
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"cbnz w1, 2f \n" /* Busy -> return 1 */
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"mov w2, #1 \n"
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"stxr w3, w2, [%x1] \n" /* w3 = status */
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"cbnz w3, 1b \n" /* Retry on STXR failure */
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"dmb sy \n" /* Acquire barrier on success */
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"mov %w0, #0 \n" /* Success */
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"b 3f \n"
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"2: \n"
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"clrex \n" /* Clear monitor when busy */
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"mov %w0, #1 \n" /* Busy */
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"3: \n"
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: "=r" ( ulRet )
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: "r" ( ulLock )
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: "memory", "w1", "w2"
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: "memory", "w1", "w2", "w3"
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);
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return ulRet;
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@ -1615,12 +1633,12 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
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/*-----------------------------------------------------------*/
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void vPortRecursiveLock( BaseType_t xCoreID,
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void vPortRecursiveLock( uint8_t ucCoreID,
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ePortRTOSLock eLockNum,
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BaseType_t uxAcquire )
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{
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/* Validate the core ID and lock number. */
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configASSERT( xCoreID < portMAX_CORE_COUNT );
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configASSERT( ucCoreID < portMAX_CORE_COUNT );
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configASSERT( eLockNum < eLockCount );
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uint32_t ulLockBit = 1u << eLockNum;
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@ -1636,10 +1654,10 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
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if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 )
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{
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/* Check if the core owns the spinlock. */
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if( prvGet64( &ucOwnedByCore[ xCoreID ] ) & ulLockBit )
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if( prvGet64( &ullOwnedByCore[ ucCoreID ] ) & ulLockBit )
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{
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configASSERT( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) != 255u );
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prvSet64( &ucRecursionCountByLock[ eLockNum ], ( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) + 1 ) );
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configASSERT( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) != 255u );
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prvSet64( &ullRecursionCountByLock[ eLockNum ], ( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) + 1 ) );
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return;
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}
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@ -1649,13 +1667,21 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
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while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 )
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{
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/* Follow Arm's recommended way of sleeping
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* sevl is used to prime the wait loop,
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* the first wfe wakes immediately as sevl has set the flag
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* the second wfe sleeps the core. This way the core is ensured
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* to sleep.
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*/
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__asm volatile ( "sevl; wfe; wfe" );
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/* Follow Arm's recommended way of sleeping
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* sevl is used to prime the wait loop.
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* The first wfe wakes immediately because sevl has set the flag.
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* Check the lock, if it's not available, issue a second wfe to sleep.
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* This guarantees the core actually goes to sleep.
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*/
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__asm volatile (
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"sevl \n"
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"1: wfe \n"
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"ldr w2, [%x0] \n"
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"cbnz w2, 1b \n"
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:
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: "r" ( &ulGateWord[ eLockNum ] )
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: "memory", "w2"
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);
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}
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}
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@ -1663,26 +1689,26 @@ UBaseType_t uxPortSetInterruptMaskFromISR( void )
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__asm__ __volatile__ ( "dmb sy" ::: "memory" );
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/* Assert the lock count is 0 when the spinlock is free and is acquired. */
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configASSERT( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) == 0 );
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configASSERT( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) == 0 );
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/* Set lock count as 1. */
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prvSet64( &ucRecursionCountByLock[ eLockNum ], 1 );
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/* Set ucOwnedByCore. */
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prvSet64( &ucOwnedByCore[ xCoreID ], ( prvGet64( &ucOwnedByCore[ xCoreID ] ) | ulLockBit ) );
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prvSet64( &ullRecursionCountByLock[ eLockNum ], 1 );
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/* Set ullOwnedByCore. */
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prvSet64( &ullOwnedByCore[ ucCoreID ], ( prvGet64( &ullOwnedByCore[ ucCoreID ] ) | ulLockBit ) );
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}
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/* Lock release. */
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else
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{
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/* Assert the lock is not free already. */
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configASSERT( ( prvGet64( &ucOwnedByCore[ xCoreID ] ) & ulLockBit ) != 0 );
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configASSERT( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) != 0 );
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configASSERT( ( prvGet64( &ullOwnedByCore[ ucCoreID ] ) & ulLockBit ) != 0 );
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configASSERT( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) != 0 );
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/* Reduce ucRecursionCountByLock by 1. */
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prvSet64( &ucRecursionCountByLock[ eLockNum ], ( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) - 1 ) );
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/* Reduce ullRecursionCountByLock by 1. */
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prvSet64( &ullRecursionCountByLock[ eLockNum ], ( prvGet64( &ullRecursionCountByLock[ eLockNum ] ) - 1 ) );
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if( !prvGet64( &ucRecursionCountByLock[ eLockNum ] ) )
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if( !prvGet64( &ullRecursionCountByLock[ eLockNum ] ) )
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{
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prvSet64( &ucOwnedByCore[ xCoreID ], ( prvGet64( &ucOwnedByCore[ xCoreID ] ) & ~ulLockBit ) );
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prvSet64( &ullOwnedByCore[ ucCoreID ], ( prvGet64( &ullOwnedByCore[ ucCoreID ] ) & ~ulLockBit ) );
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prvSpinUnlock( &ulGateWord[ eLockNum ] );
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/* Add barrier to ensure lock status is reflected before we proceed. */
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__asm__ __volatile__ ( "dmb sy" ::: "memory" );
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@ -52,13 +52,13 @@
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/* Variables and functions. */
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#if ( configNUMBER_OF_CORES == 1 )
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.extern pxCurrentTCB
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.extern ullCriticalNesting
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.extern ullPortInterruptNesting
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.extern pxCurrentTCB
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.extern ullCriticalNesting
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.extern ullPortInterruptNesting
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#else /* #if ( configNUMBER_OF_CORES == 1 ) */
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.extern pxCurrentTCBs
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.extern ullCriticalNestings
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.extern ullPortInterruptNestings
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.extern pxCurrentTCBs
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.extern ullCriticalNestings
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.extern ullPortInterruptNestings
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#endif
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.extern vTaskSwitchContext
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.extern vApplicationIRQHandler
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@ -308,16 +308,16 @@ LDP Q0, Q1, [ SP ], # 0x20
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/* Store user allocated task stack and use ullContext as the SP */
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#if ( configNUMBER_OF_CORES == 1 )
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adrp X0, pxCurrentTCB
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add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */
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adrp X0, pxCurrentTCB
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add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */
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#else
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adrp X0, pxCurrentTCBs
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add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */
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adrp X0, pxCurrentTCBs
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add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */
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#endif
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LDR X1, [ X0 ]
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ADD X1, X1, #8 /* X1 = X1 + 8, X1 now points to ullTaskUnprivilegedSP in TCB. */
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@ -339,16 +339,16 @@ LDP Q0, Q1, [ SP ], # 0x20
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#endif
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CBNZ X0, 3f /* If task is privileged, skip saving MPU context. */
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#if ( configNUMBER_OF_CORES == 1 )
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adrp X0, pxCurrentTCB
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add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */
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adrp X0, pxCurrentTCB
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add X0, X0, :lo12:pxCurrentTCB /* X0 = &pxCurrentTCB */
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#else
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adrp X0, pxCurrentTCBs
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add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */
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adrp X0, pxCurrentTCBs
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add X0, X0, :lo12:pxCurrentTCBs /* X0 = &pxCurrentTCBs */
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/* Get the core ID to index the TCB correctly. */
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MRS X2, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
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AND X2, X2, # 0xff /* Extract Aff0 which contains the core ID */
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LSL X2, X2, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
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ADD X0, X0, X2 /* Add the offset for the current core's TCB pointer */
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#endif
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LDR X0, [ X0 ]
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@ -369,8 +369,10 @@ LDP Q0, Q1, [ SP ], # 0x20
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#endif /* #if ( configENABLE_MPU == 1 ) */
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MSR SPSEL, # 0
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/* Save the entire context. */
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saveallgpregisters
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/* Save the SPSR and ELR values. */
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MRS X3, SPSR_EL1
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MRS X2, ELR_EL1
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@ -379,24 +381,25 @@ STP X2, X3, [ SP, # - 0x10 ] !
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/* Save the critical section nesting depth. */
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#if ( configNUMBER_OF_CORES == 1 )
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adrp X0, ullCriticalNesting
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add X0, X0, :lo12:ullCriticalNesting /* X0 = &ullCriticalNesting */
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adrp X0, ullCriticalNesting
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add X0, X0, :lo12:ullCriticalNesting /* X0 = &ullCriticalNesting */
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#else
|
||||
adrp X0, ullCriticalNestings
|
||||
add X0, X0, :lo12:ullCriticalNestings /* X0 = &ullCriticalNestings */
|
||||
/* Calculate per-core index using MPIDR_EL1 for SMP support. */
|
||||
MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register. */
|
||||
AND X1, X1, # 0xff /* Extract Aff0 (core ID). */
|
||||
LSL X1, X1, # 3 /* Multiply core ID by pointer size (8 bytes). */
|
||||
ADD X0, X0, X1 /* Add offset to base address. */
|
||||
adrp X0, ullCriticalNestings
|
||||
add X0, X0, :lo12:ullCriticalNestings /* X0 = &ullCriticalNestings */
|
||||
/* Calculate per-core index using MPIDR_EL1 for SMP support. */
|
||||
MRS X1, MPIDR_EL1 /* Read the Multiprocessor Affinity Register. */
|
||||
AND X1, X1, # 0xff /* Extract Aff0 (core ID). */
|
||||
LSL X1, X1, # 3 /* Multiply core ID by pointer size (8 bytes). */
|
||||
ADD X0, X0, X1 /* Add offset to base address. */
|
||||
#endif
|
||||
|
||||
LDR X3, [ X0 ]
|
||||
|
||||
/* Save the FPU context indicator. */
|
||||
adrp X0, ullPortTaskHasFPUContext
|
||||
add X0, X0, :lo12:ullPortTaskHasFPUContext /* X0 = &ullPortTaskHasFPUContext */
|
||||
|
||||
#if configNUMBER_OF_CORES > 1
|
||||
#if ( configNUMBER_OF_CORES > 1 )
|
||||
ADD X0, X0, X1 /* Add to the base of the FPU array. */
|
||||
#endif
|
||||
LDR X2, [ X0 ]
|
||||
|
|
@ -547,16 +550,16 @@ MSR SPSEL, # 1
|
|||
STP X8, X9, [ SP, # - 0x10 ] !
|
||||
STR X10, [ SP, # - 0x10 ] !
|
||||
#if ( configNUMBER_OF_CORES == 1 )
|
||||
adrp X8, pxCurrentTCB
|
||||
add X8, X8, :lo12:pxCurrentTCB /* X8 = &pxCurrentTCB */
|
||||
adrp X8, pxCurrentTCB
|
||||
add X8, X8, :lo12:pxCurrentTCB /* X8 = &pxCurrentTCB */
|
||||
#else
|
||||
adrp X8, pxCurrentTCBs
|
||||
add X8, X8, :lo12:pxCurrentTCBs /* X8 = &pxCurrentTCBs */
|
||||
/* Get the core ID to index the TCB correctly. */
|
||||
MRS X10, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
|
||||
AND X10, X10, # 0xff /* Extract Aff0 which contains the core ID */
|
||||
LSL X10, X10, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
|
||||
ADD X8, X8, X10 /* Add the offset for the current core's TCB pointer */
|
||||
adrp X8, pxCurrentTCBs
|
||||
add X8, X8, :lo12:pxCurrentTCBs /* X8 = &pxCurrentTCBs */
|
||||
/* Get the core ID to index the TCB correctly. */
|
||||
MRS X10, MPIDR_EL1 /* Read the Multiprocessor Affinity Register */
|
||||
AND X10, X10, # 0xff /* Extract Aff0 which contains the core ID */
|
||||
LSL X10, X10, # 3 /* Scale the core ID to the size of a pointer (64-bit system) */
|
||||
ADD X8, X8, X10 /* Add the offset for the current core's TCB pointer */
|
||||
#endif
|
||||
LDR X9, [ X8 ]
|
||||
MRS X8, SP_EL0
|
||||
|
|
@ -926,8 +929,8 @@ LDP X0, X1, [SP], #0x10
|
|||
portSAVE_CONTEXT
|
||||
savefuncontextgpregs
|
||||
#if ( configNUMBER_OF_CORES > 1 )
|
||||
MRS x0, mpidr_el1
|
||||
AND x0, x0, 255
|
||||
MRS x0, mpidr_el1
|
||||
AND x0, x0, 255
|
||||
#endif
|
||||
BL vTaskSwitchContext
|
||||
restorefuncontextgpregs
|
||||
|
|
@ -1039,12 +1042,12 @@ ISB SY
|
|||
/* Restore the interrupt ID value. */
|
||||
LDP X0, X1, [ SP ], # 0x10
|
||||
|
||||
|
||||
/* End IRQ processing by writing interrupt ID value to the EOI register. */
|
||||
MSR ICC_EOIR1_EL1, X0
|
||||
|
||||
/* Restore the critical nesting count. */
|
||||
LDP X1, X5, [ SP ], # 0x10
|
||||
|
||||
STR X1, [ X5 ]
|
||||
|
||||
/* Has interrupt nesting unwound? */
|
||||
|
|
@ -1095,8 +1098,8 @@ restoreallgpregisters
|
|||
/* Save the context of the current task and select a new task to run. */
|
||||
portSAVE_CONTEXT
|
||||
#if configNUMBER_OF_CORES > 1
|
||||
MRS x0, mpidr_el1
|
||||
AND x0, x0, 255
|
||||
MRS x0, mpidr_el1
|
||||
AND x0, x0, 255
|
||||
#endif
|
||||
savefuncontextgpregs
|
||||
BL vTaskSwitchContext
|
||||
|
|
@ -1116,7 +1119,7 @@ ISB SY
|
|||
restorefloatregisters
|
||||
restoreallgpregisters
|
||||
|
||||
ERET
|
||||
ERET
|
||||
|
||||
/******************************************************************************
|
||||
* If the application provides an implementation of vApplicationIRQHandler(),
|
||||
|
|
|
|||
|
|
@ -139,22 +139,21 @@
|
|||
extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
|
||||
extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t uxNewMaskValue );
|
||||
extern void vInterruptCore( uint32_t ulInterruptID, uint32_t ulCoreID );
|
||||
extern void vInterruptCore( uint32_t ulInterruptID, uint8_t ucCoreID );
|
||||
#endif /* if !defined(__ASSEMBLER__) */
|
||||
|
||||
/* Use SVC so this is safe from EL0. EL1 sites in the port use direct MSR. */\
|
||||
/* Use SVC so this is safe from EL0. EL1 sites in the port use direct MSR. */
|
||||
#define portDISABLE_INTERRUPTS() __asm volatile ( "SVC %0" : : "i" ( portSVC_DISABLE_INTERRUPTS ) : "memory" )
|
||||
|
||||
#define portENABLE_INTERRUPTS() __asm volatile ( "SVC %0" : : "i" ( portSVC_ENABLE_INTERRUPTS ) : "memory" )
|
||||
|
||||
|
||||
/* In all GICs 255 can be written to the priority mask register to unmask all
|
||||
* (but the lowest) interrupt priority. */
|
||||
#define portUNMASK_VALUE ( 0xFFUL )
|
||||
|
||||
#if !defined(__ASSEMBLER__)
|
||||
/* These macros do not globally disable/enable interrupts. They do mask off
|
||||
* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
|
||||
* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
|
||||
#if ( configNUMBER_OF_CORES == 1 )
|
||||
extern void vPortEnterCritical( void );
|
||||
extern void vPortExitCritical( void );
|
||||
|
|
@ -180,7 +179,7 @@
|
|||
|
||||
#if !defined(__ASSEMBLER__)
|
||||
/* Prototype of the FreeRTOS tick handler. This must be installed as the
|
||||
* handler for whichever peripheral is used to generate the RTOS tick. */
|
||||
* handler for whichever peripheral is used to generate the RTOS tick. */
|
||||
void FreeRTOS_Tick_Handler( void );
|
||||
#endif /* if !defined(__ASSEMBLER__) */
|
||||
|
||||
|
|
@ -200,7 +199,8 @@
|
|||
* nothing to prevent it from being called accidentally. */
|
||||
#define vPortTaskUsesFPU()
|
||||
#endif
|
||||
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
|
||||
|
||||
#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
|
||||
|
||||
#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
|
||||
#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
|
||||
|
|
@ -212,12 +212,10 @@
|
|||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
|
|
@ -227,7 +225,7 @@
|
|||
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
|
||||
#endif /* configASSERT */
|
||||
|
||||
#define portNOP() __asm volatile ( "NOP" )
|
||||
#define portNOP() __asm volatile ( "NOP" )
|
||||
#define portINLINE __inline
|
||||
|
||||
/* The number of bits to shift for an interrupt priority is dependent on the
|
||||
|
|
@ -266,7 +264,7 @@
|
|||
} ePortRTOSLock;
|
||||
|
||||
extern volatile uint64_t ullCriticalNestings[ configNUMBER_OF_CORES ];
|
||||
extern void vPortRecursiveLock( BaseType_t xCoreID,
|
||||
extern void vPortRecursiveLock( uint8_t ucCoreID,
|
||||
ePortRTOSLock eLockNum,
|
||||
BaseType_t uxAcquire );
|
||||
extern uint8_t ucPortGetCoreID( void );
|
||||
|
|
@ -280,19 +278,18 @@
|
|||
#define portGET_CORE_ID() ucPortGetCoreID()
|
||||
#define portGET_CORE_ID_FROM_ISR() ucPortGetCoreIDFromIsr()
|
||||
|
||||
/* Use SGI 0 as the yield core interrupt. */
|
||||
#define portYIELD_CORE( xCoreID ) vInterruptCore( portYIELD_CORE_INT_ID, ( uint32_t ) xCoreID )
|
||||
/* Use SGI 0 as the yield core interrupt. */
|
||||
#define portYIELD_CORE( xCoreID ) vInterruptCore( portYIELD_CORE_INT_ID, ( uint8_t ) xCoreID )
|
||||
|
||||
#define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eIsrLock, pdFALSE )
|
||||
#define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eIsrLock, pdTRUE )
|
||||
#define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE )
|
||||
#define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE )
|
||||
|
||||
#define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eTaskLock, pdFALSE )
|
||||
#define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eTaskLock, pdTRUE )
|
||||
|
||||
#define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( xCoreID ) ] )
|
||||
#define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ullCriticalNestings[ ( xCoreID ) ] = ( x ) )
|
||||
#define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( xCoreID ) ]++ )
|
||||
#define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( xCoreID ) ]-- )
|
||||
#define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE )
|
||||
#define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE )
|
||||
#define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ] )
|
||||
#define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) )
|
||||
#define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ]++ )
|
||||
#define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ]-- )
|
||||
|
||||
#endif /* configNUMBER_OF_CORES > 1 */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue