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Starting point for IAR RISC-V project created some time ago - checking in now so it can be completed - currently work in progress.

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Richard Barry 2019-08-04 15:24:15 +00:00
parent 5352cb4f45
commit 72af51cd86
16 changed files with 5179 additions and 0 deletions
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13
FreeRTOS/Demo/RISC-V_RV32_SiFive_IAR/settings/RTOSDemo.Debug.driver.xcl Normal file
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"--core=RV32IMAC"
"-p"
"C:\devtools\IAR Systems\Embedded Workbench 8.3\riscv\config\debugger\SiFive\e31arty35t.ddf"
"-d"
"sim"