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Starting point for IAR RISC-V project created some time ago - checking in now so it can be completed - currently work in progress.
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Richard Barry
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16 changed files with 5179 additions and 0 deletions
172
FreeRTOS/Demo/RISC-V_RV32_SiFive_IAR/SiFive_code/riscv_plic0.c
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172
FreeRTOS/Demo/RISC-V_RV32_SiFive_IAR/SiFive_code/riscv_plic0.c
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/* Copyright 2018 SiFive, Inc */
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/* SPDX-License-Identifier: Apache-2.0 */
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#include <metal/machine/platform.h>
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#ifdef METAL_RISCV_PLIC0
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#include <metal/io.h>
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#include <metal/shutdown.h>
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#include <metal/drivers/riscv_plic0.h>
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#include <metal/machine.h>
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unsigned int __metal_plic0_claim_interrupt (struct __metal_driver_riscv_plic0 *plic)
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{
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unsigned long control_base = __metal_driver_sifive_plic0_control_base((struct metal_interrupt *)plic);
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return __METAL_ACCESS_ONCE((__metal_io_u32 *)(control_base +
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METAL_RISCV_PLIC0_CLAIM));
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}
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void __metal_plic0_complete_interrupt(struct __metal_driver_riscv_plic0 *plic,
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unsigned int id)
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{
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unsigned long control_base = __metal_driver_sifive_plic0_control_base((struct metal_interrupt *)plic);
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__METAL_ACCESS_ONCE((__metal_io_u32 *)(control_base +
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METAL_RISCV_PLIC0_CLAIM)) = id;
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}
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void __metal_plic0_set_threshold(struct __metal_driver_riscv_plic0 *plic,
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unsigned int threshold)
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{
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unsigned long control_base = __metal_driver_sifive_plic0_control_base((struct metal_interrupt *)plic);
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__METAL_ACCESS_ONCE((__metal_io_u32 *)(control_base +
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METAL_RISCV_PLIC0_THRESHOLD)) = threshold;
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}
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void __metal_plic0_set_priority(struct __metal_driver_riscv_plic0 *plic,
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int id, unsigned int priority)
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{
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unsigned long control_base = __metal_driver_sifive_plic0_control_base((struct metal_interrupt *)plic);
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int max_priority = __metal_driver_sifive_plic0_max_priority((struct metal_interrupt *)plic);
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if ( (max_priority) && (priority < max_priority) ) {
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__METAL_ACCESS_ONCE((__metal_io_u32 *)(control_base +
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METAL_RISCV_PLIC0_PRIORITY_BASE +
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(id << METAL_PLIC_SOURCE_PRIORITY_SHIFT))) = priority;
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}
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}
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void __metal_plic0_enable(struct __metal_driver_riscv_plic0 *plic, int id, int enable)
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{
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unsigned int current;
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unsigned long hartid = __metal_myhart_id();
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unsigned long control_base = __metal_driver_sifive_plic0_control_base((struct metal_interrupt *)plic);
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current = __METAL_ACCESS_ONCE((__metal_io_u32 *)(control_base +
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METAL_RISCV_PLIC0_ENABLE_BASE +
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(id >> METAL_PLIC_SOURCE_SHIFT) * 4));
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__METAL_ACCESS_ONCE((__metal_io_u32 *)(control_base +
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METAL_RISCV_PLIC0_ENABLE_BASE +
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((id >> METAL_PLIC_SOURCE_SHIFT) * 4))) =
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enable ? (current | (1 << (id & METAL_PLIC_SOURCE_MASK)))
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: (current & ~(1 << (id & METAL_PLIC_SOURCE_MASK)));
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}
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void __metal_plic0_default_handler (int id, void *priv) {
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metal_shutdown(300);
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}
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void __metal_plic0_handler (int id, void *priv)
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{
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struct __metal_driver_riscv_plic0 *plic = priv;
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unsigned int idx = __metal_plic0_claim_interrupt(plic);
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int num_interrupts = __metal_driver_sifive_plic0_num_interrupts((struct metal_interrupt *)plic);
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if ( (idx < num_interrupts) && (plic->metal_exint_table[idx]) ) {
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plic->metal_exint_table[idx](idx,
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plic->metal_exdata_table[idx].exint_data);
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}
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__metal_plic0_complete_interrupt(plic, idx);
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}
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void __metal_driver_riscv_plic0_init (struct metal_interrupt *controller)
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{
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struct __metal_driver_riscv_plic0 *plic = (void *)(controller);
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if ( !plic->init_done ) {
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int num_interrupts, line;
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struct metal_interrupt *intc;
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for(int parent = 0; parent < __METAL_PLIC_NUM_PARENTS; parent++) {
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num_interrupts = __metal_driver_sifive_plic0_num_interrupts(controller);
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intc = __metal_driver_sifive_plic0_interrupt_parents(controller, parent);
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line = __metal_driver_sifive_plic0_interrupt_lines(controller, parent);
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/* Initialize ist parent controller, aka cpu_intc. */
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intc->vtable->interrupt_init(intc);
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for (int i = 0; i < num_interrupts; i++) {
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__metal_plic0_enable(plic, i, METAL_DISABLE);
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__metal_plic0_set_priority(plic, i, 0);
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plic->metal_exint_table[i] = NULL;
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plic->metal_exdata_table[i].sub_int = NULL;
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plic->metal_exdata_table[i].exint_data = NULL;
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}
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__metal_plic0_set_threshold(plic, 0);
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/* Register plic (ext) interrupt with with parent controller */
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intc->vtable->interrupt_register(intc, line, NULL, plic);
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/* Register plic handler for dispatching its device interrupts */
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intc->vtable->interrupt_register(intc, line, __metal_plic0_handler, plic);
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/* Enable plic (ext) interrupt with with parent controller */
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intc->vtable->interrupt_enable(intc, line);
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}
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plic->init_done = 1;
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}
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}
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int __metal_driver_riscv_plic0_register (struct metal_interrupt *controller,
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int id, metal_interrupt_handler_t isr,
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void *priv)
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{
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struct __metal_driver_riscv_plic0 *plic = (void *)(controller);
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if (id >= __metal_driver_sifive_plic0_num_interrupts(controller)) {
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return -1;
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}
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if (isr) {
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__metal_plic0_set_priority(plic ,id, 2);
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plic->metal_exint_table[id] = isr;
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plic->metal_exdata_table[id].exint_data = priv;
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} else {
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__metal_plic0_set_priority(plic, id, 1);
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plic->metal_exint_table[id] = __metal_plic0_default_handler;
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plic->metal_exdata_table[id].sub_int = priv;
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}
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return 0;
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}
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int __metal_driver_riscv_plic0_enable (struct metal_interrupt *controller, int id)
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{
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struct __metal_driver_riscv_plic0 *plic = (void *)(controller);
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if (id >= __metal_driver_sifive_plic0_num_interrupts(controller)) {
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return -1;
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}
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__metal_plic0_enable(plic, id, METAL_ENABLE);
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return 0;
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}
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int __metal_driver_riscv_plic0_disable (struct metal_interrupt *controller, int id)
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{
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struct __metal_driver_riscv_plic0 *plic = (void *)(controller);
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if (id >= __metal_driver_sifive_plic0_num_interrupts(controller)) {
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return -1;
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}
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__metal_plic0_enable(plic, id, METAL_DISABLE);
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return 0;
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}
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__METAL_DEFINE_VTABLE(__metal_driver_vtable_riscv_plic0) = {
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.plic_vtable.interrupt_init = __metal_driver_riscv_plic0_init,
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.plic_vtable.interrupt_register = __metal_driver_riscv_plic0_register,
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.plic_vtable.interrupt_enable = __metal_driver_riscv_plic0_enable,
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.plic_vtable.interrupt_disable = __metal_driver_riscv_plic0_disable,
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};
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#endif /* METAL_RISCV_PLIC0 */
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151
FreeRTOS/Demo/RISC-V_RV32_SiFive_IAR/SiFive_code/sifive_uart0.c
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151
FreeRTOS/Demo/RISC-V_RV32_SiFive_IAR/SiFive_code/sifive_uart0.c
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/* Copyright 2018 SiFive, Inc */
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/* SPDX-License-Identifier: Apache-2.0 */
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#include <metal/machine/platform.h>
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#ifdef METAL_SIFIVE_UART0
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#include <metal/drivers/sifive_uart0.h>
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#include <metal/machine.h>
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/* TXDATA Fields */
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#define UART_TXEN (1 << 0)
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#define UART_TXFULL (1 << 31)
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/* RXDATA Fields */
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#define UART_RXEN (1 << 0)
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#define UART_RXEMPTY (1 << 31)
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/* TXCTRL Fields */
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#define UART_NSTOP (1 << 1)
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#define UART_TXCNT(count) ((0x7 & count) << 16)
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/* IP Fields */
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#define UART_TXWM (1 << 0)
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#define UART_REG(offset) (((unsigned long)control_base + offset))
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#define UART_REGB(offset) (__METAL_ACCESS_ONCE((__metal_io_u8 *)UART_REG(offset)))
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#define UART_REGW(offset) (__METAL_ACCESS_ONCE((__metal_io_u32 *)UART_REG(offset)))
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struct metal_interrupt *
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__metal_driver_sifive_uart0_interrupt_controller(struct metal_uart *uart)
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{
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return __metal_driver_sifive_uart0_interrupt_parent(uart);
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}
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int __metal_driver_sifive_uart0_get_interrupt_id(struct metal_uart *uart)
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{
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return (__metal_driver_sifive_uart0_interrupt_line(uart) + METAL_INTERRUPT_ID_GL0);
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}
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int __metal_driver_sifive_uart0_putc(struct metal_uart *uart, unsigned char c)
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{
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long control_base = __metal_driver_sifive_uart0_control_base(uart);
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while ((UART_REGW(METAL_SIFIVE_UART0_TXDATA) & UART_TXFULL) != 0) { }
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UART_REGW(METAL_SIFIVE_UART0_TXDATA) = c;
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return 0;
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}
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int __metal_driver_sifive_uart0_getc(struct metal_uart *uart, unsigned char *c)
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{
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uint32_t ch = UART_RXEMPTY;
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long control_base = __metal_driver_sifive_uart0_control_base(uart);
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while (ch & UART_RXEMPTY) {
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ch = UART_REGW(METAL_SIFIVE_UART0_RXDATA);
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}
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*c = ch & 0xff;
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return 0;
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}
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int __metal_driver_sifive_uart0_get_baud_rate(struct metal_uart *guart)
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{
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struct __metal_driver_sifive_uart0 *uart = (void *)guart;
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return uart->baud_rate;
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}
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int __metal_driver_sifive_uart0_set_baud_rate(struct metal_uart *guart, int baud_rate)
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{
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struct __metal_driver_sifive_uart0 *uart = (void *)guart;
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long control_base = __metal_driver_sifive_uart0_control_base(guart);
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struct metal_clock *clock = __metal_driver_sifive_uart0_clock(guart);
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uart->baud_rate = baud_rate;
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if (clock != NULL) {
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long clock_rate = clock->vtable->get_rate_hz(clock);
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UART_REGW(METAL_SIFIVE_UART0_DIV) = clock_rate / baud_rate - 1;
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UART_REGW(METAL_SIFIVE_UART0_TXCTRL) |= UART_TXEN;
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UART_REGW(METAL_SIFIVE_UART0_RXCTRL) |= UART_RXEN;
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}
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return 0;
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}
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static void pre_rate_change_callback(void *priv)
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{
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struct __metal_driver_sifive_uart0 *uart = priv;
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long control_base = __metal_driver_sifive_uart0_control_base((struct metal_uart *)priv);
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struct metal_clock *clock = __metal_driver_sifive_uart0_clock((struct metal_uart *)priv);
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/* Detect when the TXDATA is empty by setting the transmit watermark count
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* to one and waiting until an interrupt is pending */
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UART_REGW(METAL_SIFIVE_UART0_TXCTRL) &= ~(UART_TXCNT(0x7));
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UART_REGW(METAL_SIFIVE_UART0_TXCTRL) |= UART_TXCNT(1);
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while((UART_REGW(METAL_SIFIVE_UART0_IP) & UART_TXWM) == 0) ;
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/* When the TXDATA clears, the UART is still shifting out the last byte.
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* Calculate the time we must drain to finish transmitting and then wait
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* that long. */
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long bits_per_symbol = (UART_REGW(METAL_SIFIVE_UART0_TXCTRL) & (1 << 1)) ? 9 : 10;
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long clk_freq = clock->vtable->get_rate_hz(clock);
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long cycles_to_wait = bits_per_symbol * clk_freq / uart->baud_rate;
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for(volatile long x = 0; x < cycles_to_wait; x++)
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asm("nop");
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}
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static void post_rate_change_callback(void *priv)
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{
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struct __metal_driver_sifive_uart0 *uart = priv;
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metal_uart_set_baud_rate(&uart->uart, uart->baud_rate);
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}
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void __metal_driver_sifive_uart0_init(struct metal_uart *guart, int baud_rate)
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{
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struct __metal_driver_sifive_uart0 *uart = (void *)(guart);
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struct metal_clock *clock = __metal_driver_sifive_uart0_clock(guart);
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struct __metal_driver_sifive_gpio0 *pinmux = __metal_driver_sifive_uart0_pinmux(guart);
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if(clock != NULL) {
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metal_clock_register_pre_rate_change_callback(clock, &pre_rate_change_callback, guart);
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metal_clock_register_post_rate_change_callback(clock, &post_rate_change_callback, guart);
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}
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metal_uart_set_baud_rate(&(uart->uart), baud_rate);
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if (pinmux != NULL) {
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long pinmux_output_selector = __metal_driver_sifive_uart0_pinmux_output_selector(guart);
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long pinmux_source_selector = __metal_driver_sifive_uart0_pinmux_source_selector(guart);
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pinmux->gpio.vtable->enable_io(
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(struct metal_gpio *) pinmux,
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pinmux_output_selector,
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pinmux_source_selector
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);
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}
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}
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__METAL_DEFINE_VTABLE(__metal_driver_vtable_sifive_uart0) = {
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.uart.init = __metal_driver_sifive_uart0_init,
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.uart.putc = __metal_driver_sifive_uart0_putc,
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.uart.getc = __metal_driver_sifive_uart0_getc,
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.uart.get_baud_rate = __metal_driver_sifive_uart0_get_baud_rate,
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.uart.set_baud_rate = __metal_driver_sifive_uart0_set_baud_rate,
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.uart.controller_interrupt = __metal_driver_sifive_uart0_interrupt_controller,
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.uart.get_interrupt_id = __metal_driver_sifive_uart0_get_interrupt_id,
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};
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#endif /* METAL_SIFIVE_UART0 */
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