mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Implementing exception handling in the new MicroBlaze port - still a work in progress.
This commit is contained in:
Richard Barry
parent
8b0ccf1444
commit
71b359154b
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@ -96,6 +96,7 @@
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#define configUSE_COUNTING_SEMAPHORES 1
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#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 )
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#define configINTERRUPT_STACK_SIZE configMINIMAL_STACK_SIZE
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#define configINSTALL_EXCEPTION_HANDLERS 1
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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@ -1005,6 +1005,19 @@ portTickType xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
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*/
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unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
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/**
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* task. h
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* <PRE>signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery );</PRE>
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*
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* @return The text (human readable) name of the task referenced by the handle
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* xTaskToQueury. A task can query its own name by either passing in its own
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* handle, or by setting xTaskToQuery to NULL.
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*
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* \page uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
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* \ingroup TaskUtils
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*/
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signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery );
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/**
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* task. h
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* <PRE>void vTaskList( char *pcWriteBuffer );</PRE>
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@ -66,7 +66,6 @@
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/* Hardware includes. */
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#include <xintc_i.h>
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#include <xil_exception.h>
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#include <microblaze_exceptions_i.h>
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#include <microblaze_exceptions_g.h>
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/* Tasks are started with a critical section nesting of 0 - however prior
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@ -85,8 +84,6 @@ to reach zero, so it is initialised to a high value. */
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*/
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static portBASE_TYPE prvInitialiseInterruptController( void );
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static void prvExceptionHandler( void *pvExceptionID );
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/*
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* Call an application provided callback to set up the periodic interrupt used
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* for the RTOS tick. Using an application callback allows the application
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@ -344,20 +341,6 @@ extern void vApplicationClearTimerInterrupt( void );
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}
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/*-----------------------------------------------------------*/
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static void prvExceptionHandler( void *pvExceptionID )
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{
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volatile unsigned long ulExceptionID;
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ulExceptionID = ( unsigned long ) pvExceptionID;
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for( ;; )
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{
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portNOP();
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}
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( void ) ulExceptionID;
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}
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/*-----------------------------------------------------------*/
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static portBASE_TYPE prvInitialiseInterruptController( void )
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{
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portBASE_TYPE xStatus;
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@ -372,45 +355,13 @@ portBASE_TYPE xStatus;
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/* Service all pending interrupts each time the handler is entered. */
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XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
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/* Install exception handlers. */
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#if MICROBLAZE_EXCEPTIONS_ENABLED == 1
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#if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1
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microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, prvExceptionHandler, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
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#endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS*/
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#if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, prvExceptionHandler, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
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#endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, prvExceptionHandler, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
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#endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, prvExceptionHandler, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
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#endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, prvExceptionHandler, ( void * ) XEXC_ID_IPLB_EXCEPTION );
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#endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, prvExceptionHandler, ( void * ) XEXC_ID_DPLB_EXCEPTION );
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#endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, prvExceptionHandler, ( void * ) XEXC_ID_DIV_BY_ZERO );
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#endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_FPU, prvExceptionHandler, ( void * ) XEXC_ID_FPU );
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#endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_FSL, prvExceptionHandler, ( void * ) XEXC_ID_FSL );
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#endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION*/
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/* Install exception handlers if the MicroBlaze is configured to handle
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exceptions, and the application defined constant
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configINSTALL_EXCEPTION_HANDLERS is set to 1. */
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#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
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{
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vPortExceptionsInstallHandlers();
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}
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#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
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/* Start the interrupt controller. Interrupts are enabled when the
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@ -424,12 +375,17 @@ portBASE_TYPE xStatus;
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configASSERT( ( xStatus == ( portBASE_TYPE ) XST_SUCCESS ) )
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/*_RB_ Exception test code.
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/*_RB_ Exception test code. */
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#if 0
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This does not cause the bralid address to be in the r17 register.
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__asm volatile (
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"bralid r15, 1234 \n"
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"or r0, r0, r0 \n"
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);
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*/
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#endif
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#if 0
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xStatus /= 0;
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#endif
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return xStatus;
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}
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@ -0,0 +1,245 @@
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/*
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FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* FreeRTOS tutorial books are available in pdf and paperback. *
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* Complete, revised, and edited pdf reference manuals are also *
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* available. *
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* *
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* Purchasing FreeRTOS documentation will not only help you, by *
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* ensuring you get running as quickly as possible and with an *
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* in-depth knowledge of how to use FreeRTOS, it will also help *
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* the FreeRTOS project to continue with its mission of providing *
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* professional grade, cross platform, de facto standard solutions *
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* for microcontrollers - completely free of charge! *
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* *
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* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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* *
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* Thank you for using FreeRTOS, and thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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>>>NOTE<<< The modification to the GPL is included to allow you to
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distribute a combined work that includes FreeRTOS without being obliged to
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provide the source code for proprietary components outside of the FreeRTOS
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kernel. FreeRTOS is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Hardware includes. */
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#include <microblaze_exceptions_i.h>
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#include <microblaze_exceptions_g.h>
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#define portexR3_STACK_OFFSET 4
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#define portexR4_STACK_OFFSET 5
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#define portexR5_STACK_OFFSET 6
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#define portexR6_STACK_OFFSET 7
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#define portexR7_STACK_OFFSET 8
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#define portexR8_STACK_OFFSET 9
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#define portexR9_STACK_OFFSET 10
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#define portexR10_STACK_OFFSET 11
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#define portexR11_STACK_OFFSET 12
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#define portexR12_STACK_OFFSET 13
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#define portexR15_STACK_OFFSET 16
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#define portexR18_STACK_OFFSET 18
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#define portexR19_STACK_OFFSET -1
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#define portexESR_DS_MASK 0x00001000UL
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/* Exclude the entire file if the MicroBlaze is not configured to handle
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exceptions, or the application defined configuration item
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configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
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#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
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/* These are global volatiles to allow their inspection by a debugger. */
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unsigned long *pulStackPointerOnFunctionEntry = NULL;
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static xPortRegisterDump xRegisterDump;
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void vPortExceptionHandler( void *pvExceptionID );
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extern void vPortExceptionHandlerEntry( void *pvExceptionID );
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/*-----------------------------------------------------------*/
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void vPortExceptionHandler( void *pvExceptionID )
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{
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extern void *pxCurrentTCB;
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xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
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xRegisterDump.pcCurrentTaskName = pcTaskGetTaskName( NULL );
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configASSERT( pulStackPointerOnFunctionEntry );
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/* Obtain the values of registers that were stacked prior to this function
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being called, and may have changed since they were stacked. */
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xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
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xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
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xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
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xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
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xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
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xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
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xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
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xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
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xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
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xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
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xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
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/* Obtain the value of all other registers. */
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//xRegisterDump.ulR1 =
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xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
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xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
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xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
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xRegisterDump.ulR15_return_address_from_subroutine = mfgpr( R15 );
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xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
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xRegisterDump.ulR17_return_address_from_some_exceptions = mfgpr( R17 );
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xRegisterDump.ulR18 = mfgpr( R18 );
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xRegisterDump.ulR20 = mfgpr( R20 );
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xRegisterDump.ulR21 = mfgpr( R21 );
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xRegisterDump.ulR22 = mfgpr( R22 );
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xRegisterDump.ulR23 = mfgpr( R23 );
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xRegisterDump.ulR24 = mfgpr( R24 );
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xRegisterDump.ulR25 = mfgpr( R25 );
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xRegisterDump.ulR26 = mfgpr( R26 );
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xRegisterDump.ulR27 = mfgpr( R27 );
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xRegisterDump.ulR28 = mfgpr( R28 );
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xRegisterDump.ulR29 = mfgpr( R29 );
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xRegisterDump.ulR30 = mfgpr( R30 );
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xRegisterDump.ulR31 = mfgpr( R31 );
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xRegisterDump.ulESR = mfesr();
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if( ( xRegisterDump.ulESR * portexESR_DS_MASK ) != 0UL )
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{
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xRegisterDump.ulPC = mfbtr();
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}
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else
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{
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xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_some_exceptions - 4;
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}
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// xRegisterDump.ulSP =;
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// PC changes
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// MSR changes
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// BTR changes
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switch( ( unsigned long ) pvExceptionID )
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{
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case XEXC_ID_FSL :
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xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_FSL";
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break;
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case XEXC_ID_UNALIGNED_ACCESS :
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xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_UNALIGNED_ACCESS";
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break;
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case XEXC_ID_ILLEGAL_OPCODE :
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xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_ILLEGAL_OPCODE";
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break;
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case XEXC_ID_M_AXI_I_EXCEPTION :
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xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
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break;
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case XEXC_ID_M_AXI_D_EXCEPTION :
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xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
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break;
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case XEXC_ID_DIV_BY_ZERO :
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xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_DIV_BY_ZERO";
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break;
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case XEXC_ID_FPU :
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/*_RB_ More decoding required here and in other exceptions. */
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xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_FPU";
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break;
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case XEXC_ID_STACK_VIOLATION :
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xRegisterDump.pcExceptionCause = ( signed char * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
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break;
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}
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/* Must not attempt to leave this function! */
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for( ;; )
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{
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portNOP();
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}
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}
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/*-----------------------------------------------------------*/
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void vPortExceptionsInstallHandlers( void )
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{
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#if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1
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microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
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#endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS*/
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#if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
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#endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
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#endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
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#endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
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#endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
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#endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
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#endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
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#endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION*/
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#if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1
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microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
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#endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION*/
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}
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/*-----------------------------------------------------------*/
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/* Exclude the entire file if the MicroBlaze is not configured to handle
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exceptions, or the application defined configuration item
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configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
|
||||
#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
|
||||
|
||||
|
||||
|
||||
|
|
@ -58,6 +58,7 @@
|
|||
*/
|
||||
|
||||
#include "FreeRTOSConfig.h"
|
||||
#include "microblaze_exceptions_g.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/* The context is oversized to allow functions called from the ISR to write
|
||||
|
|
@ -109,10 +110,13 @@ back into the caller stack. */
|
|||
.extern uxCriticalNesting
|
||||
.extern pulISRStack
|
||||
.extern ulTaskSwitchRequested
|
||||
.extern vPortExceptionHandler
|
||||
.extern pulStackPointerOnFunctionEntry
|
||||
|
||||
.global _interrupt_handler
|
||||
.global VPortYieldASM
|
||||
.global vPortStartFirstTask
|
||||
.global vPortExceptionHandlerEntry
|
||||
|
||||
|
||||
.macro portSAVE_CONTEXT
|
||||
|
|
@ -335,6 +339,20 @@ vPortStartFirstTask:
|
|||
|
||||
|
||||
|
||||
#if MICROBLAZE_EXCEPTIONS_ENABLED == 1
|
||||
|
||||
.text
|
||||
.align 2
|
||||
vPortExceptionHandlerEntry:
|
||||
|
||||
/* Take a copy of the stack pointer before vPortExecptionHandler is called,
|
||||
storing its value prior to the function stack frame being created. */
|
||||
lwi r18, r0, pulStackPointerOnFunctionEntry
|
||||
swi r1, r0, pulStackPointerOnFunctionEntry
|
||||
bralid r15, vPortExceptionHandler
|
||||
or r0, r0, r0
|
||||
|
||||
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -146,6 +146,48 @@ extern volatile unsigned long ulTaskSwitchRequested;
|
|||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
|
||||
typedef struct PORT_REGISTER_DUMP
|
||||
{
|
||||
unsigned long ulSP;
|
||||
unsigned long ulR2_small_data_area;
|
||||
unsigned long ulR3;
|
||||
unsigned long ulR4;
|
||||
unsigned long ulR5;
|
||||
unsigned long ulR6;
|
||||
unsigned long ulR7;
|
||||
unsigned long ulR8;
|
||||
unsigned long ulR9;
|
||||
unsigned long ulR10;
|
||||
unsigned long ulR11;
|
||||
unsigned long ulR12;
|
||||
unsigned long ulR13_read_write_small_data_area;
|
||||
unsigned long ulR14_return_address_from_interrupt;
|
||||
unsigned long ulR15_return_address_from_subroutine;
|
||||
unsigned long ulR16_return_address_from_trap;
|
||||
unsigned long ulR17_return_address_from_some_exceptions;
|
||||
unsigned long ulR18;
|
||||
unsigned long ulR19;
|
||||
unsigned long ulR20;
|
||||
unsigned long ulR21;
|
||||
unsigned long ulR22;
|
||||
unsigned long ulR23;
|
||||
unsigned long ulR24;
|
||||
unsigned long ulR25;
|
||||
unsigned long ulR26;
|
||||
unsigned long ulR27;
|
||||
unsigned long ulR28;
|
||||
unsigned long ulR29;
|
||||
unsigned long ulR30;
|
||||
unsigned long ulR31;
|
||||
unsigned long ulPC;
|
||||
unsigned long ulESR;
|
||||
signed char *pcExceptionCause;
|
||||
signed char *pcCurrentTaskName;
|
||||
void * xCurrentTaskHandle;
|
||||
} xPortRegisterDump;
|
||||
|
||||
void vPortExceptionsInstallHandlers( void );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1281,6 +1281,17 @@ unsigned portBASE_TYPE uxTaskGetNumberOfTasks( void )
|
|||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
signed char *pcTaskGetTaskName( xTaskHandle xTaskToQuery )
|
||||
{
|
||||
tskTCB *pxTCB;
|
||||
|
||||
/* If null is passed in here then we are suspending ourselves. */
|
||||
pxTCB = prvGetTCBFromHandle( xTaskToQuery );
|
||||
configASSERT( pxTCB );
|
||||
return &( pxTCB->pcTaskName[ 0 ] );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||
|
||||
void vTaskList( signed char *pcWriteBuffer )
|
||||
|
|
|
|||
Loading…
Reference in a new issue