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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Alfred Gedeon
alfred gedeon
parent
a5dbc2b1de
commit
718178c68a
406 changed files with 108795 additions and 106323 deletions
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@ -25,8 +25,8 @@
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the PPC405 port.
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*----------------------------------------------------------*/
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* Implementation of functions defined in portable.h for the PPC405 port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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@ -41,19 +41,19 @@
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/*-----------------------------------------------------------*/
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/* Definitions to set the initial MSR of each task. */
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#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
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#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
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#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
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#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
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#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
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#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
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#if configUSE_FPU == 1
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#define portAPU_PRESENT ( 1UL << 25UL )
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#define portFCM_FPU_PRESENT ( 1UL << 13UL )
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#define portAPU_PRESENT ( 1UL << 25UL )
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#define portFCM_FPU_PRESENT ( 1UL << 13UL )
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#else
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#define portAPU_PRESENT ( 0UL )
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#define portFCM_FPU_PRESENT ( 0UL )
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#define portAPU_PRESENT ( 0UL )
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#define portFCM_FPU_PRESENT ( 0UL )
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#endif
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#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
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#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
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extern const unsigned _SDA_BASE_;
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@ -89,171 +89,177 @@ static XIntc xInterruptController;
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/*-----------------------------------------------------------*/
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/*
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/*
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* Initialise the stack of a task to look exactly as if the task had been
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* interrupted.
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*
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*
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* See the header file portable.h.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/* Place a known value at the bottom of the stack for debugging. */
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*pxTopOfStack = 0xDEADBEEF;
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pxTopOfStack--;
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/* Place a known value at the bottom of the stack for debugging. */
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*pxTopOfStack = 0xDEADBEEF;
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pxTopOfStack--;
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/* EABI stack frame. */
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pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
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/* EABI stack frame. */
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pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
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/* Parameters in R13. */
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*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
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pxTopOfStack -= 10;
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/* Parameters in R13. */
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*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
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pxTopOfStack -= 10;
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/* Parameters in R3. */
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*pxTopOfStack = ( StackType_t ) pvParameters;
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pxTopOfStack--;
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/* Parameters in R3. */
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*pxTopOfStack = ( StackType_t ) pvParameters;
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pxTopOfStack--;
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/* Parameters in R2. */
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*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
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pxTopOfStack--;
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/* Parameters in R2. */
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*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
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pxTopOfStack--;
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/* R1 is the stack pointer so is omitted. */
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/* R1 is the stack pointer so is omitted. */
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*pxTopOfStack = 0x10000001UL;; /* R0. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* USPRG0. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* CR. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* XER. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* CTR. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_MSR;/* SRR1. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL;/* Backchain. */
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*pxTopOfStack = 0x10000001UL; /* R0. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* USPRG0. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* CR. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* XER. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* CTR. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_MSR; /* SRR1. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* Next LR. */
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pxTopOfStack--;
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*pxTopOfStack = 0x00000000UL; /* Backchain. */
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return pxTopOfStack;
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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prvSetupTimerInterrupt();
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XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
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vPortStartFirstTask();
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prvSetupTimerInterrupt();
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XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
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vPortStartFirstTask();
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/* Should not get here as the tasks are now running! */
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return pdFALSE;
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/* Should not get here as the tasks are now running! */
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return pdFALSE;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented. */
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for( ;; );
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/* Not implemented. */
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for( ; ; )
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{
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}
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}
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/*-----------------------------------------------------------*/
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/*
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* Hardware initialisation to generate the RTOS tick.
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* Hardware initialisation to generate the RTOS tick.
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*/
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static void prvSetupTimerInterrupt( void )
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{
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const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
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const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
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XTime_PITClearInterrupt();
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XTime_FITClearInterrupt();
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XTime_WDTClearInterrupt();
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XTime_WDTDisableInterrupt();
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XTime_FITDisableInterrupt();
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XTime_PITClearInterrupt();
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XTime_FITClearInterrupt();
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XTime_WDTClearInterrupt();
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XTime_WDTDisableInterrupt();
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XTime_FITDisableInterrupt();
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XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
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XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
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XTime_PITEnableAutoReload();
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XTime_PITSetInterval( ulInterval );
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XTime_PITEnableInterrupt();
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XTime_PITEnableAutoReload();
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XTime_PITSetInterval( ulInterval );
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XTime_PITEnableInterrupt();
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}
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/*-----------------------------------------------------------*/
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void vPortISRHandler( void *pvNullDoNotUse )
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void vPortISRHandler( void * pvNullDoNotUse )
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{
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uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
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BaseType_t xInterruptNumber;
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XIntc_Config *pxInterruptController;
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XIntc_VectorTableEntry *pxTable;
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uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
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BaseType_t xInterruptNumber;
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XIntc_Config * pxInterruptController;
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XIntc_VectorTableEntry * pxTable;
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/* Just to remove compiler warning. */
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( void ) pvNullDoNotUse;
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/* Just to remove compiler warning. */
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( void ) pvNullDoNotUse;
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/* Get the configuration by using the device ID - in this case it is
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assumed that only one interrupt controller is being used. */
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pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
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/* Which interrupts are pending? */
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ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
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for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
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{
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if( ulInterruptStatus & 0x01UL )
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{
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/* Clear the pending interrupt. */
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XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
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/* Get the configuration by using the device ID - in this case it is
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* assumed that only one interrupt controller is being used. */
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pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
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/* Call the registered handler. */
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pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
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pxTable->Handler( pxTable->CallBackRef );
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}
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/* Check the next interrupt. */
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ulInterruptMask <<= 0x01UL;
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ulInterruptStatus >>= 0x01UL;
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/* Which interrupts are pending? */
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ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
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/* Have we serviced all interrupts? */
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if( ulInterruptStatus == 0UL )
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{
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break;
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}
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}
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for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
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{
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if( ulInterruptStatus & 0x01UL )
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{
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/* Clear the pending interrupt. */
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XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
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/* Call the registered handler. */
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pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
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pxTable->Handler( pxTable->CallBackRef );
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}
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/* Check the next interrupt. */
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ulInterruptMask <<= 0x01UL;
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ulInterruptStatus >>= 0x01UL;
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/* Have we serviced all interrupts? */
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if( ulInterruptStatus == 0UL )
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{
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break;
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}
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}
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}
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/*-----------------------------------------------------------*/
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void vPortSetupInterruptController( void )
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{
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extern void vPortISRWrapper( void );
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extern void vPortISRWrapper( void );
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/* Perform all library calls necessary to initialise the exception table
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and interrupt controller. This assumes only one interrupt controller is in
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use. */
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XExc_mDisableExceptions( XEXC_NON_CRITICAL );
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XExc_Init();
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/* Perform all library calls necessary to initialise the exception table
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* and interrupt controller. This assumes only one interrupt controller is in
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* use. */
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XExc_mDisableExceptions( XEXC_NON_CRITICAL );
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XExc_Init();
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/* The library functions save the context - we then jump to a wrapper to
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save the stack into the TCB. The wrapper then calls the handler defined
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above. */
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XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
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XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
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XIntc_Start( &xInterruptController, XIN_REAL_MODE );
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/* The library functions save the context - we then jump to a wrapper to
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* save the stack into the TCB. The wrapper then calls the handler defined
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* above. */
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XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
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XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
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XIntc_Start( &xInterruptController, XIN_REAL_MODE );
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
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BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
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XInterruptHandler pxHandler,
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void * pvCallBackRef )
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{
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BaseType_t xReturn = pdFAIL;
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BaseType_t xReturn = pdFAIL;
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/* This function is defined here so the scope of xInterruptController can
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remain within this file. */
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/* This function is defined here so the scope of xInterruptController can
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* remain within this file. */
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if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
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{
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XIntc_Enable( &xInterruptController, ucInterruptID );
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xReturn = pdPASS;
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}
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if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
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{
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XIntc_Enable( &xInterruptController, ucInterruptID );
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xReturn = pdPASS;
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}
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return xReturn;
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return xReturn;
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}
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