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Alfred Gedeon
alfred gedeon
parent
a5dbc2b1de
commit
718178c68a
406 changed files with 108795 additions and 106323 deletions
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@ -25,8 +25,8 @@
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the MicroBlaze port.
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*----------------------------------------------------------*/
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* Implementation of functions defined in portable.h for the MicroBlaze port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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@ -42,20 +42,20 @@
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#include <microblaze_exceptions_g.h>
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/* Tasks are started with a critical section nesting of 0 - however, prior to
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the scheduler being commenced interrupts should not be enabled, so the critical
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nesting variable is initialised to a non-zero value. */
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#define portINITIAL_NESTING_VALUE ( 0xff )
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* the scheduler being commenced interrupts should not be enabled, so the critical
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* nesting variable is initialised to a non-zero value. */
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#define portINITIAL_NESTING_VALUE ( 0xff )
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/* The bit within the MSR register that enabled/disables interrupts and
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exceptions respectively. */
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#define portMSR_IE ( 0x02U )
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#define portMSR_EE ( 0x100U )
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/* The bit within the MSR register that enabled/disables interrupts and
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* exceptions respectively. */
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#define portMSR_IE ( 0x02U )
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#define portMSR_EE ( 0x100U )
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/* If the floating point unit is included in the MicroBlaze build, then the
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FSR register is saved as part of the task context. portINITIAL_FSR is the value
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given to the FSR register when the initial context is set up for a task being
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created. */
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#define portINITIAL_FSR ( 0U )
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* FSR register is saved as part of the task context. portINITIAL_FSR is the value
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* given to the FSR register when the initial context is set up for a task being
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* created. */
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#define portINITIAL_FSR ( 0U )
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/*-----------------------------------------------------------*/
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/*
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@ -71,28 +71,28 @@ static int32_t prvEnsureInterruptControllerIsInitialised( void );
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/*-----------------------------------------------------------*/
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/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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maintains its own count, so this variable is saved as part of the task
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context. */
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volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
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* maintains its own count, so this variable is saved as part of the task
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* context. */
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volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
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/* This port uses a separate stack for interrupts. This prevents the stack of
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every task needing to be large enough to hold an entire interrupt stack on top
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of the task stack. */
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uint32_t *pulISRStack;
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* every task needing to be large enough to hold an entire interrupt stack on top
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* of the task stack. */
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uint32_t * pulISRStack;
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/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
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get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
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handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
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will call vTaskSwitchContext() to ensure the task that runs immediately after
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the interrupt exists is the highest priority task that is able to run. This is
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an unusual mechanism, but is used for this port because a single interrupt can
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cause the servicing of multiple peripherals - and it is inefficient to call
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vTaskSwitchContext() multiple times as each peripheral is serviced. */
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* get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
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* handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
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* will call vTaskSwitchContext() to ensure the task that runs immediately after
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* the interrupt exists is the highest priority task that is able to run. This is
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* an unusual mechanism, but is used for this port because a single interrupt can
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* cause the servicing of multiple peripherals - and it is inefficient to call
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* vTaskSwitchContext() multiple times as each peripheral is serviced. */
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volatile uint32_t ulTaskSwitchRequested = 0UL;
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/* The instance of the interrupt controller used by this port. This is required
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by the Xilinx library API functions. */
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static XIntc xInterruptControllerInstance;
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* by the Xilinx library API functions. */
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static XIntc xInterruptControllerInstance;
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/*-----------------------------------------------------------*/
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@ -102,172 +102,174 @@ static XIntc xInterruptControllerInstance;
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*
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* See the portable.h header file.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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extern void *_SDA2_BASE_, *_SDA_BASE_;
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const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
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const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
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extern void * _SDA2_BASE_, * _SDA_BASE_;
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const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
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const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
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/* Place a few bytes of known values on the bottom of the stack.
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This is essential for the Microblaze port and these lines must
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not be omitted. */
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*pxTopOfStack = ( StackType_t ) 0x00000000;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00000000;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00000000;
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pxTopOfStack--;
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/* Place a few bytes of known values on the bottom of the stack.
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* This is essential for the Microblaze port and these lines must
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* not be omitted. */
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*pxTopOfStack = ( StackType_t ) 0x00000000;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00000000;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00000000;
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pxTopOfStack--;
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#if( XPAR_MICROBLAZE_USE_FPU != 0 )
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/* The FSR value placed in the initial task context is just 0. */
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*pxTopOfStack = portINITIAL_FSR;
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pxTopOfStack--;
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#endif
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#if ( XPAR_MICROBLAZE_USE_FPU != 0 )
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/* The FSR value placed in the initial task context is just 0. */
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*pxTopOfStack = portINITIAL_FSR;
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pxTopOfStack--;
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#endif
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/* The MSR value placed in the initial task context should have interrupts
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disabled. Each task will enable interrupts automatically when it enters
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the running state for the first time. */
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*pxTopOfStack = mfmsr() & ~portMSR_IE;
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#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
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{
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/* Ensure exceptions are enabled for the task. */
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*pxTopOfStack |= portMSR_EE;
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}
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#endif
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/* The MSR value placed in the initial task context should have interrupts
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* disabled. Each task will enable interrupts automatically when it enters
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* the running state for the first time. */
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*pxTopOfStack = mfmsr() & ~portMSR_IE;
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pxTopOfStack--;
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#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
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{
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/* Ensure exceptions are enabled for the task. */
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*pxTopOfStack |= portMSR_EE;
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}
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#endif
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/* First stack an initial value for the critical section nesting. This
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is initialised to zero. */
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*pxTopOfStack = ( StackType_t ) 0x00;
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pxTopOfStack--;
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/* R0 is always zero. */
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/* R1 is the SP. */
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/* First stack an initial value for the critical section nesting. This
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* is initialised to zero. */
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*pxTopOfStack = ( StackType_t ) 0x00;
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/* Place an initial value for all the general purpose registers. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
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/* R0 is always zero. */
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/* R1 is the SP. */
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#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
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pxTopOfStack--;
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#else
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pxTopOfStack-= 8;
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#endif
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/* Place an initial value for all the general purpose registers. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R5 contains the function call parameters. */
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*pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
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#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
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pxTopOfStack--;
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#else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
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pxTopOfStack -= 8;
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#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
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#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
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pxTopOfStack--;
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#else
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pxTopOfStack -= 4;
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#endif
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*pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
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*pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
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#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
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pxTopOfStack--;
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#else
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pxTopOfStack -= 4;
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#endif
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#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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#else
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pxTopOfStack -= 13;
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#endif
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*pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
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/* Return a pointer to the top of the stack that has been generated so this
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can be stored in the task control block for the task. */
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return pxTopOfStack;
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#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
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pxTopOfStack--;
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#else /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
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pxTopOfStack -= 13;
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#endif /* ifdef portPRE_LOAD_STACK_FOR_DEBUGGING */
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/* Return a pointer to the top of the stack that has been generated so this
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* can be stored in the task control block for the task. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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extern void ( vPortStartFirstTask )( void );
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extern uint32_t _stack[];
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extern void( vPortStartFirstTask )( void );
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extern uint32_t _stack[];
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/* Setup the hardware to generate the tick. Interrupts are disabled when
|
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this function is called.
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/* Setup the hardware to generate the tick. Interrupts are disabled when
|
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* this function is called.
|
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*
|
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* This port uses an application defined callback function to install the tick
|
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* interrupt handler because the kernel will run on lots of different
|
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* MicroBlaze and FPGA configurations - not all of which will have the same
|
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* timer peripherals defined or available. An example definition of
|
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* vApplicationSetupTimerInterrupt() is provided in the official demo
|
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* application that accompanies this port. */
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vApplicationSetupTimerInterrupt();
|
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|
||||
This port uses an application defined callback function to install the tick
|
||||
interrupt handler because the kernel will run on lots of different
|
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MicroBlaze and FPGA configurations - not all of which will have the same
|
||||
timer peripherals defined or available. An example definition of
|
||||
vApplicationSetupTimerInterrupt() is provided in the official demo
|
||||
application that accompanies this port. */
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vApplicationSetupTimerInterrupt();
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/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
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pulISRStack = ( uint32_t * ) _stack;
|
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|
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/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
|
||||
pulISRStack = ( uint32_t * ) _stack;
|
||||
/* Ensure there is enough space for the functions called from the interrupt
|
||||
* service routines to write back into the stack frame of the caller. */
|
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pulISRStack -= 2;
|
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|
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/* Ensure there is enough space for the functions called from the interrupt
|
||||
service routines to write back into the stack frame of the caller. */
|
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pulISRStack -= 2;
|
||||
/* Restore the context of the first task that is going to run. From here
|
||||
* on, the created tasks will be executing. */
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Restore the context of the first task that is going to run. From here
|
||||
on, the created tasks will be executing. */
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should not get here as the tasks are now running! */
|
||||
return pdFALSE;
|
||||
/* Should not get here as the tasks are now running! */
|
||||
return pdFALSE;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler( void )
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
Artificially force an assert. */
|
||||
configASSERT( uxCriticalNesting == 1000UL );
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
* Artificially force an assert. */
|
||||
configASSERT( uxCriticalNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -276,104 +278,107 @@ void vPortEndScheduler( void )
|
|||
*/
|
||||
void vPortYield( void )
|
||||
{
|
||||
extern void VPortYieldASM( void );
|
||||
extern void VPortYieldASM( void );
|
||||
|
||||
/* Perform the context switch in a critical section to assure it is
|
||||
not interrupted by the tick ISR. It is not a problem to do this as
|
||||
each task maintains its own interrupt status. */
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
/* Jump directly to the yield function to ensure there is no
|
||||
compiler generated prologue code. */
|
||||
asm volatile ( "bralid r14, VPortYieldASM \n\t" \
|
||||
"or r0, r0, r0 \n\t" );
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
/* Perform the context switch in a critical section to assure it is
|
||||
* not interrupted by the tick ISR. It is not a problem to do this as
|
||||
* each task maintains its own interrupt status. */
|
||||
portENTER_CRITICAL();
|
||||
{
|
||||
/* Jump directly to the yield function to ensure there is no
|
||||
* compiler generated prologue code. */
|
||||
asm volatile ( "bralid r14, VPortYieldASM \n\t"\
|
||||
"or r0, r0, r0 \n\t");
|
||||
}
|
||||
portEXIT_CRITICAL();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEnableInterrupt( uint8_t ucInterruptID )
|
||||
{
|
||||
int32_t lReturn;
|
||||
int32_t lReturn;
|
||||
|
||||
/* An API function is provided to enable an interrupt in the interrupt
|
||||
controller because the interrupt controller instance variable is private
|
||||
to this file. */
|
||||
lReturn = prvEnsureInterruptControllerIsInitialised();
|
||||
if( lReturn == pdPASS )
|
||||
{
|
||||
XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
|
||||
}
|
||||
/* An API function is provided to enable an interrupt in the interrupt
|
||||
* controller because the interrupt controller instance variable is private
|
||||
* to this file. */
|
||||
lReturn = prvEnsureInterruptControllerIsInitialised();
|
||||
|
||||
configASSERT( lReturn );
|
||||
if( lReturn == pdPASS )
|
||||
{
|
||||
XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
|
||||
}
|
||||
|
||||
configASSERT( lReturn );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortDisableInterrupt( uint8_t ucInterruptID )
|
||||
{
|
||||
int32_t lReturn;
|
||||
int32_t lReturn;
|
||||
|
||||
/* An API function is provided to disable an interrupt in the interrupt
|
||||
controller because the interrupt controller instance variable is private
|
||||
to this file. */
|
||||
lReturn = prvEnsureInterruptControllerIsInitialised();
|
||||
/* An API function is provided to disable an interrupt in the interrupt
|
||||
* controller because the interrupt controller instance variable is private
|
||||
* to this file. */
|
||||
lReturn = prvEnsureInterruptControllerIsInitialised();
|
||||
|
||||
if( lReturn == pdPASS )
|
||||
{
|
||||
XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
|
||||
}
|
||||
if( lReturn == pdPASS )
|
||||
{
|
||||
XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
|
||||
}
|
||||
|
||||
configASSERT( lReturn );
|
||||
configASSERT( lReturn );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
|
||||
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
|
||||
XInterruptHandler pxHandler,
|
||||
void * pvCallBackRef )
|
||||
{
|
||||
int32_t lReturn;
|
||||
int32_t lReturn;
|
||||
|
||||
/* An API function is provided to install an interrupt handler because the
|
||||
interrupt controller instance variable is private to this file. */
|
||||
/* An API function is provided to install an interrupt handler because the
|
||||
* interrupt controller instance variable is private to this file. */
|
||||
|
||||
lReturn = prvEnsureInterruptControllerIsInitialised();
|
||||
lReturn = prvEnsureInterruptControllerIsInitialised();
|
||||
|
||||
if( lReturn == pdPASS )
|
||||
{
|
||||
lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
|
||||
}
|
||||
if( lReturn == pdPASS )
|
||||
{
|
||||
lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
|
||||
}
|
||||
|
||||
if( lReturn == XST_SUCCESS )
|
||||
{
|
||||
lReturn = pdPASS;
|
||||
}
|
||||
if( lReturn == XST_SUCCESS )
|
||||
{
|
||||
lReturn = pdPASS;
|
||||
}
|
||||
|
||||
configASSERT( lReturn == pdPASS );
|
||||
configASSERT( lReturn == pdPASS );
|
||||
|
||||
return lReturn;
|
||||
return lReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static int32_t prvEnsureInterruptControllerIsInitialised( void )
|
||||
{
|
||||
static int32_t lInterruptControllerInitialised = pdFALSE;
|
||||
int32_t lReturn;
|
||||
static int32_t lInterruptControllerInitialised = pdFALSE;
|
||||
int32_t lReturn;
|
||||
|
||||
/* Ensure the interrupt controller instance variable is initialised before
|
||||
it is used, and that the initialisation only happens once. */
|
||||
if( lInterruptControllerInitialised != pdTRUE )
|
||||
{
|
||||
lReturn = prvInitialiseInterruptController();
|
||||
/* Ensure the interrupt controller instance variable is initialised before
|
||||
* it is used, and that the initialisation only happens once. */
|
||||
if( lInterruptControllerInitialised != pdTRUE )
|
||||
{
|
||||
lReturn = prvInitialiseInterruptController();
|
||||
|
||||
if( lReturn == pdPASS )
|
||||
{
|
||||
lInterruptControllerInitialised = pdTRUE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
lReturn = pdPASS;
|
||||
}
|
||||
if( lReturn == pdPASS )
|
||||
{
|
||||
lInterruptControllerInitialised = pdTRUE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
lReturn = pdPASS;
|
||||
}
|
||||
|
||||
return lReturn;
|
||||
return lReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -381,71 +386,69 @@ int32_t lReturn;
|
|||
* Handler for the timer interrupt. This is the handler that the application
|
||||
* defined callback function vApplicationSetupTimerInterrupt() should install.
|
||||
*/
|
||||
void vPortTickISR( void *pvUnused )
|
||||
void vPortTickISR( void * pvUnused )
|
||||
{
|
||||
extern void vApplicationClearTimerInterrupt( void );
|
||||
extern void vApplicationClearTimerInterrupt( void );
|
||||
|
||||
/* Ensure the unused parameter does not generate a compiler warning. */
|
||||
( void ) pvUnused;
|
||||
/* Ensure the unused parameter does not generate a compiler warning. */
|
||||
( void ) pvUnused;
|
||||
|
||||
/* This port uses an application defined callback function to clear the tick
|
||||
interrupt because the kernel will run on lots of different MicroBlaze and
|
||||
FPGA configurations - not all of which will have the same timer peripherals
|
||||
defined or available. An example definition of
|
||||
vApplicationClearTimerInterrupt() is provided in the official demo
|
||||
application that accompanies this port. */
|
||||
vApplicationClearTimerInterrupt();
|
||||
/* This port uses an application defined callback function to clear the tick
|
||||
* interrupt because the kernel will run on lots of different MicroBlaze and
|
||||
* FPGA configurations - not all of which will have the same timer peripherals
|
||||
* defined or available. An example definition of
|
||||
* vApplicationClearTimerInterrupt() is provided in the official demo
|
||||
* application that accompanies this port. */
|
||||
vApplicationClearTimerInterrupt();
|
||||
|
||||
/* Increment the RTOS tick - this might cause a task to unblock. */
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Force vTaskSwitchContext() to be called as the interrupt exits. */
|
||||
ulTaskSwitchRequested = 1;
|
||||
}
|
||||
/* Increment the RTOS tick - this might cause a task to unblock. */
|
||||
if( xTaskIncrementTick() != pdFALSE )
|
||||
{
|
||||
/* Force vTaskSwitchContext() to be called as the interrupt exits. */
|
||||
ulTaskSwitchRequested = 1;
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static int32_t prvInitialiseInterruptController( void )
|
||||
{
|
||||
int32_t lStatus;
|
||||
int32_t lStatus;
|
||||
|
||||
lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
|
||||
lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
|
||||
|
||||
if( lStatus == XST_SUCCESS )
|
||||
{
|
||||
/* Initialise the exception table. */
|
||||
Xil_ExceptionInit();
|
||||
if( lStatus == XST_SUCCESS )
|
||||
{
|
||||
/* Initialise the exception table. */
|
||||
Xil_ExceptionInit();
|
||||
|
||||
/* Service all pending interrupts each time the handler is entered. */
|
||||
XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
|
||||
/* Service all pending interrupts each time the handler is entered. */
|
||||
XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
|
||||
|
||||
/* Install exception handlers if the MicroBlaze is configured to handle
|
||||
exceptions, and the application defined constant
|
||||
configINSTALL_EXCEPTION_HANDLERS is set to 1. */
|
||||
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
|
||||
{
|
||||
vPortExceptionsInstallHandlers();
|
||||
}
|
||||
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
|
||||
/* Install exception handlers if the MicroBlaze is configured to handle
|
||||
* exceptions, and the application defined constant
|
||||
* configINSTALL_EXCEPTION_HANDLERS is set to 1. */
|
||||
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
|
||||
{
|
||||
vPortExceptionsInstallHandlers();
|
||||
}
|
||||
#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
|
||||
|
||||
/* Start the interrupt controller. Interrupts are enabled when the
|
||||
scheduler starts. */
|
||||
lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
|
||||
/* Start the interrupt controller. Interrupts are enabled when the
|
||||
* scheduler starts. */
|
||||
lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
|
||||
|
||||
if( lStatus == XST_SUCCESS )
|
||||
{
|
||||
lStatus = pdPASS;
|
||||
}
|
||||
else
|
||||
{
|
||||
lStatus = pdFAIL;
|
||||
}
|
||||
}
|
||||
if( lStatus == XST_SUCCESS )
|
||||
{
|
||||
lStatus = pdPASS;
|
||||
}
|
||||
else
|
||||
{
|
||||
lStatus = pdFAIL;
|
||||
}
|
||||
}
|
||||
|
||||
configASSERT( lStatus == pdPASS );
|
||||
configASSERT( lStatus == pdPASS );
|
||||
|
||||
return lStatus;
|
||||
return lStatus;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -33,249 +33,244 @@
|
|||
#include <microblaze_exceptions_g.h>
|
||||
|
||||
/* The Xilinx library defined exception entry point stacks a number of
|
||||
registers. These definitions are offsets from the stack pointer to the various
|
||||
stacked register values. */
|
||||
#define portexR3_STACK_OFFSET 4
|
||||
#define portexR4_STACK_OFFSET 5
|
||||
#define portexR5_STACK_OFFSET 6
|
||||
#define portexR6_STACK_OFFSET 7
|
||||
#define portexR7_STACK_OFFSET 8
|
||||
#define portexR8_STACK_OFFSET 9
|
||||
#define portexR9_STACK_OFFSET 10
|
||||
#define portexR10_STACK_OFFSET 11
|
||||
#define portexR11_STACK_OFFSET 12
|
||||
#define portexR12_STACK_OFFSET 13
|
||||
#define portexR15_STACK_OFFSET 16
|
||||
#define portexR18_STACK_OFFSET 19
|
||||
#define portexMSR_STACK_OFFSET 20
|
||||
#define portexR19_STACK_OFFSET -1
|
||||
* registers. These definitions are offsets from the stack pointer to the various
|
||||
* stacked register values. */
|
||||
#define portexR3_STACK_OFFSET 4
|
||||
#define portexR4_STACK_OFFSET 5
|
||||
#define portexR5_STACK_OFFSET 6
|
||||
#define portexR6_STACK_OFFSET 7
|
||||
#define portexR7_STACK_OFFSET 8
|
||||
#define portexR8_STACK_OFFSET 9
|
||||
#define portexR9_STACK_OFFSET 10
|
||||
#define portexR10_STACK_OFFSET 11
|
||||
#define portexR11_STACK_OFFSET 12
|
||||
#define portexR12_STACK_OFFSET 13
|
||||
#define portexR15_STACK_OFFSET 16
|
||||
#define portexR18_STACK_OFFSET 19
|
||||
#define portexMSR_STACK_OFFSET 20
|
||||
#define portexR19_STACK_OFFSET -1
|
||||
|
||||
/* This is defined to equal the size, in bytes, of the stack frame generated by
|
||||
the Xilinx standard library exception entry point. It is required to determine
|
||||
the stack pointer value prior to the exception being entered. */
|
||||
#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
|
||||
* the Xilinx standard library exception entry point. It is required to determine
|
||||
* the stack pointer value prior to the exception being entered. */
|
||||
#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
|
||||
|
||||
/* The number of bytes a MicroBlaze instruction consumes. */
|
||||
#define portexINSTRUCTION_SIZE 4
|
||||
#define portexINSTRUCTION_SIZE 4
|
||||
|
||||
/* Exclude this entire file if the MicroBlaze is not configured to handle
|
||||
exceptions, or the application defined configuration constant
|
||||
configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
|
||||
* exceptions, or the application defined configuration constant
|
||||
* configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
|
||||
#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
|
||||
|
||||
/* This variable is set in the exception entry code, before
|
||||
vPortExceptionHandler is called. */
|
||||
uint32_t *pulStackPointerOnFunctionEntry = NULL;
|
||||
* vPortExceptionHandler is called. */
|
||||
uint32_t * pulStackPointerOnFunctionEntry = NULL;
|
||||
|
||||
/* This is the structure that is filled with the MicroBlaze context as it
|
||||
existed immediately prior to the exception occurrence. A pointer to this
|
||||
structure is passed into the vApplicationExceptionRegisterDump() callback
|
||||
function, if one is defined. */
|
||||
static xPortRegisterDump xRegisterDump;
|
||||
* existed immediately prior to the exception occurrence. A pointer to this
|
||||
* structure is passed into the vApplicationExceptionRegisterDump() callback
|
||||
* function, if one is defined. */
|
||||
static xPortRegisterDump xRegisterDump;
|
||||
|
||||
/* This is the FreeRTOS exception handler that is installed for all exception
|
||||
types. It is called from vPortExceptionHanlderEntry() - which is itself defined
|
||||
in portasm.S. */
|
||||
void vPortExceptionHandler( void *pvExceptionID );
|
||||
extern void vPortExceptionHandlerEntry( void *pvExceptionID );
|
||||
* types. It is called from vPortExceptionHanlderEntry() - which is itself defined
|
||||
* in portasm.S. */
|
||||
void vPortExceptionHandler( void * pvExceptionID );
|
||||
extern void vPortExceptionHandlerEntry( void * pvExceptionID );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* vApplicationExceptionRegisterDump() is a callback function that the
|
||||
application can optionally define to receive a populated xPortRegisterDump
|
||||
structure. If the application chooses not to define a version of
|
||||
vApplicationExceptionRegisterDump() then this weekly defined default
|
||||
implementation will be called instead. */
|
||||
extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
|
||||
void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
|
||||
{
|
||||
( void ) xRegisterDump;
|
||||
* application can optionally define to receive a populated xPortRegisterDump
|
||||
* structure. If the application chooses not to define a version of
|
||||
* vApplicationExceptionRegisterDump() then this weekly defined default
|
||||
* implementation will be called instead. */
|
||||
extern void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump ) __attribute__( ( weak ) );
|
||||
void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump )
|
||||
{
|
||||
( void ) xRegisterDump;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
portNOP();
|
||||
}
|
||||
}
|
||||
for( ; ; )
|
||||
{
|
||||
portNOP();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortExceptionHandler( void *pvExceptionID )
|
||||
{
|
||||
extern void *pxCurrentTCB;
|
||||
void vPortExceptionHandler( void * pvExceptionID )
|
||||
{
|
||||
extern void * pxCurrentTCB;
|
||||
|
||||
/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
|
||||
was immediately before the exception occurrence. */
|
||||
/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
|
||||
* was immediately before the exception occurrence. */
|
||||
|
||||
/* First fill in the name and handle of the task that was in the Running
|
||||
state when the exception occurred. */
|
||||
xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
|
||||
xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
|
||||
/* First fill in the name and handle of the task that was in the Running
|
||||
* state when the exception occurred. */
|
||||
xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
|
||||
xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
|
||||
|
||||
configASSERT( pulStackPointerOnFunctionEntry );
|
||||
configASSERT( pulStackPointerOnFunctionEntry );
|
||||
|
||||
/* Obtain the values of registers that were stacked prior to this function
|
||||
being called, and may have changed since they were stacked. */
|
||||
xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
|
||||
xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
|
||||
xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
|
||||
xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
|
||||
xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
|
||||
xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
|
||||
xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
|
||||
xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
|
||||
xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
|
||||
xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
|
||||
xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
|
||||
xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
|
||||
xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
|
||||
xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
|
||||
/* Obtain the values of registers that were stacked prior to this function
|
||||
* being called, and may have changed since they were stacked. */
|
||||
xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
|
||||
xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
|
||||
xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
|
||||
xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
|
||||
xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
|
||||
xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
|
||||
xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
|
||||
xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
|
||||
xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
|
||||
xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
|
||||
xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
|
||||
xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
|
||||
xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
|
||||
xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
|
||||
|
||||
/* Obtain the value of all other registers. */
|
||||
xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
|
||||
xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
|
||||
xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
|
||||
xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
|
||||
xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
|
||||
xRegisterDump.ulR20 = mfgpr( R20 );
|
||||
xRegisterDump.ulR21 = mfgpr( R21 );
|
||||
xRegisterDump.ulR22 = mfgpr( R22 );
|
||||
xRegisterDump.ulR23 = mfgpr( R23 );
|
||||
xRegisterDump.ulR24 = mfgpr( R24 );
|
||||
xRegisterDump.ulR25 = mfgpr( R25 );
|
||||
xRegisterDump.ulR26 = mfgpr( R26 );
|
||||
xRegisterDump.ulR27 = mfgpr( R27 );
|
||||
xRegisterDump.ulR28 = mfgpr( R28 );
|
||||
xRegisterDump.ulR29 = mfgpr( R29 );
|
||||
xRegisterDump.ulR30 = mfgpr( R30 );
|
||||
xRegisterDump.ulR31 = mfgpr( R31 );
|
||||
xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
|
||||
xRegisterDump.ulEAR = mfear();
|
||||
xRegisterDump.ulESR = mfesr();
|
||||
xRegisterDump.ulEDR = mfedr();
|
||||
/* Obtain the value of all other registers. */
|
||||
xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
|
||||
xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
|
||||
xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
|
||||
xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
|
||||
xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
|
||||
xRegisterDump.ulR20 = mfgpr( R20 );
|
||||
xRegisterDump.ulR21 = mfgpr( R21 );
|
||||
xRegisterDump.ulR22 = mfgpr( R22 );
|
||||
xRegisterDump.ulR23 = mfgpr( R23 );
|
||||
xRegisterDump.ulR24 = mfgpr( R24 );
|
||||
xRegisterDump.ulR25 = mfgpr( R25 );
|
||||
xRegisterDump.ulR26 = mfgpr( R26 );
|
||||
xRegisterDump.ulR27 = mfgpr( R27 );
|
||||
xRegisterDump.ulR28 = mfgpr( R28 );
|
||||
xRegisterDump.ulR29 = mfgpr( R29 );
|
||||
xRegisterDump.ulR30 = mfgpr( R30 );
|
||||
xRegisterDump.ulR31 = mfgpr( R31 );
|
||||
xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
|
||||
xRegisterDump.ulEAR = mfear();
|
||||
xRegisterDump.ulESR = mfesr();
|
||||
xRegisterDump.ulEDR = mfedr();
|
||||
|
||||
/* Move the saved program counter back to the instruction that was executed
|
||||
when the exception occurred. This is only valid for certain types of
|
||||
exception. */
|
||||
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
|
||||
/* Move the saved program counter back to the instruction that was executed
|
||||
* when the exception occurred. This is only valid for certain types of
|
||||
* exception. */
|
||||
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
|
||||
|
||||
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
|
||||
{
|
||||
xRegisterDump.ulFSR = mffsr();
|
||||
}
|
||||
#else
|
||||
{
|
||||
xRegisterDump.ulFSR = 0UL;
|
||||
}
|
||||
#endif
|
||||
#if ( XPAR_MICROBLAZE_USE_FPU != 0 )
|
||||
{
|
||||
xRegisterDump.ulFSR = mffsr();
|
||||
}
|
||||
#else
|
||||
{
|
||||
xRegisterDump.ulFSR = 0UL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Also fill in a string that describes what type of exception this is.
|
||||
The string uses the same ID names as defined in the MicroBlaze standard
|
||||
library exception header files. */
|
||||
switch( ( uint32_t ) pvExceptionID )
|
||||
{
|
||||
case XEXC_ID_FSL :
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
|
||||
break;
|
||||
/* Also fill in a string that describes what type of exception this is.
|
||||
* The string uses the same ID names as defined in the MicroBlaze standard
|
||||
* library exception header files. */
|
||||
switch( ( uint32_t ) pvExceptionID )
|
||||
{
|
||||
case XEXC_ID_FSL:
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
|
||||
break;
|
||||
|
||||
case XEXC_ID_UNALIGNED_ACCESS :
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
|
||||
break;
|
||||
case XEXC_ID_UNALIGNED_ACCESS:
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
|
||||
break;
|
||||
|
||||
case XEXC_ID_ILLEGAL_OPCODE :
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
|
||||
break;
|
||||
case XEXC_ID_ILLEGAL_OPCODE:
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
|
||||
break;
|
||||
|
||||
case XEXC_ID_M_AXI_I_EXCEPTION :
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
|
||||
break;
|
||||
case XEXC_ID_M_AXI_I_EXCEPTION:
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
|
||||
break;
|
||||
|
||||
case XEXC_ID_M_AXI_D_EXCEPTION :
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
|
||||
break;
|
||||
case XEXC_ID_M_AXI_D_EXCEPTION:
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
|
||||
break;
|
||||
|
||||
case XEXC_ID_DIV_BY_ZERO :
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
|
||||
break;
|
||||
case XEXC_ID_DIV_BY_ZERO:
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
|
||||
break;
|
||||
|
||||
case XEXC_ID_STACK_VIOLATION :
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
|
||||
break;
|
||||
case XEXC_ID_STACK_VIOLATION:
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
|
||||
break;
|
||||
|
||||
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
|
||||
#if ( XPAR_MICROBLAZE_USE_FPU != 0 )
|
||||
case XEXC_ID_FPU:
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
|
||||
break;
|
||||
#endif /* XPAR_MICROBLAZE_USE_FPU */
|
||||
}
|
||||
|
||||
case XEXC_ID_FPU :
|
||||
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
|
||||
break;
|
||||
/* vApplicationExceptionRegisterDump() is a callback function that the
|
||||
* application can optionally define to receive the populated xPortRegisterDump
|
||||
* structure. If the application chooses not to define a version of
|
||||
* vApplicationExceptionRegisterDump() then the weekly defined default
|
||||
* implementation within this file will be called instead. */
|
||||
vApplicationExceptionRegisterDump( &xRegisterDump );
|
||||
|
||||
#endif /* XPAR_MICROBLAZE_USE_FPU */
|
||||
}
|
||||
|
||||
/* vApplicationExceptionRegisterDump() is a callback function that the
|
||||
application can optionally define to receive the populated xPortRegisterDump
|
||||
structure. If the application chooses not to define a version of
|
||||
vApplicationExceptionRegisterDump() then the weekly defined default
|
||||
implementation within this file will be called instead. */
|
||||
vApplicationExceptionRegisterDump( &xRegisterDump );
|
||||
|
||||
/* Must not attempt to leave this function! */
|
||||
for( ;; )
|
||||
{
|
||||
portNOP();
|
||||
}
|
||||
}
|
||||
/* Must not attempt to leave this function! */
|
||||
for( ; ; )
|
||||
{
|
||||
portNOP();
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortExceptionsInstallHandlers( void )
|
||||
{
|
||||
static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
|
||||
void vPortExceptionsInstallHandlers( void )
|
||||
{
|
||||
static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
|
||||
|
||||
if( ulHandlersAlreadyInstalled == pdFALSE )
|
||||
{
|
||||
ulHandlersAlreadyInstalled = pdTRUE;
|
||||
if( ulHandlersAlreadyInstalled == pdFALSE )
|
||||
{
|
||||
ulHandlersAlreadyInstalled = pdTRUE;
|
||||
|
||||
#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
|
||||
#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
|
||||
#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
|
||||
#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
|
||||
|
||||
#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
|
||||
#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
|
||||
#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
|
||||
#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
|
||||
|
||||
#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
|
||||
#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
|
||||
#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
|
||||
#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
|
||||
|
||||
#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
|
||||
#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
|
||||
#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
|
||||
#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
|
||||
|
||||
#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
|
||||
#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
|
||||
#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
|
||||
#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
|
||||
|
||||
#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
|
||||
#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
|
||||
#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
|
||||
#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
|
||||
|
||||
#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
|
||||
#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
|
||||
#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
|
||||
#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
|
||||
|
||||
#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
|
||||
#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
|
||||
#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
|
||||
#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
|
||||
|
||||
#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
|
||||
#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
|
||||
#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
|
||||
microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
|
||||
#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
|
||||
|
||||
microblaze_enable_exceptions();
|
||||
}
|
||||
}
|
||||
microblaze_enable_exceptions();
|
||||
}
|
||||
}
|
||||
|
||||
/* Exclude the entire file if the MicroBlaze is not configured to handle
|
||||
exceptions, or the application defined configuration item
|
||||
configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
|
||||
* exceptions, or the application defined configuration item
|
||||
* configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
|
||||
#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -25,15 +25,15 @@
|
|||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* BSP includes. */
|
||||
#include <mb_interface.h>
|
||||
#include <xparameters.h>
|
||||
#include <mb_interface.h>
|
||||
#include <xparameters.h>
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
|
|
@ -46,175 +46,177 @@ extern "C" {
|
|||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#else
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#endif
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Interrupt control macros and functions. */
|
||||
void microblaze_disable_interrupts( void );
|
||||
void microblaze_enable_interrupts( void );
|
||||
#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
|
||||
#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
|
||||
void microblaze_disable_interrupts( void );
|
||||
void microblaze_enable_interrupts( void );
|
||||
#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
|
||||
#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section macros. */
|
||||
void vPortEnterCritical( void );
|
||||
void vPortExitCritical( void );
|
||||
#define portENTER_CRITICAL() { \
|
||||
extern volatile UBaseType_t uxCriticalNesting; \
|
||||
microblaze_disable_interrupts(); \
|
||||
uxCriticalNesting++; \
|
||||
}
|
||||
void vPortEnterCritical( void );
|
||||
void vPortExitCritical( void );
|
||||
#define portENTER_CRITICAL() \
|
||||
{ \
|
||||
extern volatile UBaseType_t uxCriticalNesting; \
|
||||
microblaze_disable_interrupts(); \
|
||||
uxCriticalNesting++; \
|
||||
}
|
||||
|
||||
#define portEXIT_CRITICAL() { \
|
||||
extern volatile UBaseType_t uxCriticalNesting; \
|
||||
/* Interrupts are disabled, so we can */ \
|
||||
/* access the variable directly. */ \
|
||||
uxCriticalNesting--; \
|
||||
if( uxCriticalNesting == 0 ) \
|
||||
{ \
|
||||
/* The nesting has unwound and we \
|
||||
can enable interrupts again. */ \
|
||||
portENABLE_INTERRUPTS(); \
|
||||
} \
|
||||
}
|
||||
#define portEXIT_CRITICAL() \
|
||||
{ \
|
||||
extern volatile UBaseType_t uxCriticalNesting; \
|
||||
/* Interrupts are disabled, so we can */ \
|
||||
/* access the variable directly. */ \
|
||||
uxCriticalNesting--; \
|
||||
if( uxCriticalNesting == 0 ) \
|
||||
{ \
|
||||
/* The nesting has unwound and we \
|
||||
* can enable interrupts again. */ \
|
||||
portENABLE_INTERRUPTS(); \
|
||||
} \
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The yield macro maps directly to the vPortYield() function. */
|
||||
void vPortYield( void );
|
||||
#define portYIELD() vPortYield()
|
||||
void vPortYield( void );
|
||||
#define portYIELD() vPortYield()
|
||||
|
||||
/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
|
||||
sets a flag to say that a yield has been requested. The interrupt exit code
|
||||
then checks this flag, and calls vTaskSwitchContext() before restoring a task
|
||||
context, if the flag is not false. This is done to prevent multiple calls to
|
||||
vTaskSwitchContext() being made from a single interrupt, as a single interrupt
|
||||
can result in multiple peripherals being serviced. */
|
||||
extern volatile uint32_t ulTaskSwitchRequested;
|
||||
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
|
||||
* sets a flag to say that a yield has been requested. The interrupt exit code
|
||||
* then checks this flag, and calls vTaskSwitchContext() before restoring a task
|
||||
* context, if the flag is not false. This is done to prevent multiple calls to
|
||||
* vTaskSwitchContext() being made from a single interrupt, as a single interrupt
|
||||
* can result in multiple peripherals being serviced. */
|
||||
extern volatile uint32_t ulTaskSwitchRequested;
|
||||
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
|
||||
|
||||
#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
|
||||
#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
|
||||
|
||||
/* Generic helper function. */
|
||||
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
|
||||
{
|
||||
uint8_t ucReturn;
|
||||
/* Generic helper function. */
|
||||
__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
|
||||
{
|
||||
uint8_t ucReturn;
|
||||
|
||||
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
|
||||
return ucReturn;
|
||||
}
|
||||
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
|
||||
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
return ucReturn;
|
||||
}
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 4
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portNOP() asm volatile ( "NOP" )
|
||||
#define portBYTE_ALIGNMENT 4
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portNOP() asm volatile ( "NOP" )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* The following structure is used by the FreeRTOS exception handler. It is
|
||||
filled with the MicroBlaze context as it was at the time the exception occurred.
|
||||
This is done as an aid to debugging exception occurrences. */
|
||||
typedef struct PORT_REGISTER_DUMP
|
||||
{
|
||||
/* The following structure members hold the values of the MicroBlaze
|
||||
registers at the time the exception was raised. */
|
||||
uint32_t ulR1_SP;
|
||||
uint32_t ulR2_small_data_area;
|
||||
uint32_t ulR3;
|
||||
uint32_t ulR4;
|
||||
uint32_t ulR5;
|
||||
uint32_t ulR6;
|
||||
uint32_t ulR7;
|
||||
uint32_t ulR8;
|
||||
uint32_t ulR9;
|
||||
uint32_t ulR10;
|
||||
uint32_t ulR11;
|
||||
uint32_t ulR12;
|
||||
uint32_t ulR13_read_write_small_data_area;
|
||||
uint32_t ulR14_return_address_from_interrupt;
|
||||
uint32_t ulR15_return_address_from_subroutine;
|
||||
uint32_t ulR16_return_address_from_trap;
|
||||
uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
|
||||
uint32_t ulR18;
|
||||
uint32_t ulR19;
|
||||
uint32_t ulR20;
|
||||
uint32_t ulR21;
|
||||
uint32_t ulR22;
|
||||
uint32_t ulR23;
|
||||
uint32_t ulR24;
|
||||
uint32_t ulR25;
|
||||
uint32_t ulR26;
|
||||
uint32_t ulR27;
|
||||
uint32_t ulR28;
|
||||
uint32_t ulR29;
|
||||
uint32_t ulR30;
|
||||
uint32_t ulR31;
|
||||
uint32_t ulPC;
|
||||
uint32_t ulESR;
|
||||
uint32_t ulMSR;
|
||||
uint32_t ulEAR;
|
||||
uint32_t ulFSR;
|
||||
uint32_t ulEDR;
|
||||
* filled with the MicroBlaze context as it was at the time the exception occurred.
|
||||
* This is done as an aid to debugging exception occurrences. */
|
||||
typedef struct PORT_REGISTER_DUMP
|
||||
{
|
||||
/* The following structure members hold the values of the MicroBlaze
|
||||
* registers at the time the exception was raised. */
|
||||
uint32_t ulR1_SP;
|
||||
uint32_t ulR2_small_data_area;
|
||||
uint32_t ulR3;
|
||||
uint32_t ulR4;
|
||||
uint32_t ulR5;
|
||||
uint32_t ulR6;
|
||||
uint32_t ulR7;
|
||||
uint32_t ulR8;
|
||||
uint32_t ulR9;
|
||||
uint32_t ulR10;
|
||||
uint32_t ulR11;
|
||||
uint32_t ulR12;
|
||||
uint32_t ulR13_read_write_small_data_area;
|
||||
uint32_t ulR14_return_address_from_interrupt;
|
||||
uint32_t ulR15_return_address_from_subroutine;
|
||||
uint32_t ulR16_return_address_from_trap;
|
||||
uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
|
||||
uint32_t ulR18;
|
||||
uint32_t ulR19;
|
||||
uint32_t ulR20;
|
||||
uint32_t ulR21;
|
||||
uint32_t ulR22;
|
||||
uint32_t ulR23;
|
||||
uint32_t ulR24;
|
||||
uint32_t ulR25;
|
||||
uint32_t ulR26;
|
||||
uint32_t ulR27;
|
||||
uint32_t ulR28;
|
||||
uint32_t ulR29;
|
||||
uint32_t ulR30;
|
||||
uint32_t ulR31;
|
||||
uint32_t ulPC;
|
||||
uint32_t ulESR;
|
||||
uint32_t ulMSR;
|
||||
uint32_t ulEAR;
|
||||
uint32_t ulFSR;
|
||||
uint32_t ulEDR;
|
||||
|
||||
/* A human readable description of the exception cause. The strings used
|
||||
are the same as the #define constant names found in the
|
||||
microblaze_exceptions_i.h header file */
|
||||
int8_t *pcExceptionCause;
|
||||
/* A human readable description of the exception cause. The strings used
|
||||
* are the same as the #define constant names found in the
|
||||
* microblaze_exceptions_i.h header file */
|
||||
int8_t * pcExceptionCause;
|
||||
|
||||
/* The human readable name of the task that was running at the time the
|
||||
exception occurred. This is the name that was given to the task when the
|
||||
task was created using the FreeRTOS xTaskCreate() API function. */
|
||||
char *pcCurrentTaskName;
|
||||
/* The human readable name of the task that was running at the time the
|
||||
* exception occurred. This is the name that was given to the task when the
|
||||
* task was created using the FreeRTOS xTaskCreate() API function. */
|
||||
char * pcCurrentTaskName;
|
||||
|
||||
/* The handle of the task that was running a the time the exception
|
||||
occurred. */
|
||||
void * xCurrentTaskHandle;
|
||||
|
||||
} xPortRegisterDump;
|
||||
/* The handle of the task that was running a the time the exception
|
||||
* occurred. */
|
||||
void * xCurrentTaskHandle;
|
||||
} xPortRegisterDump;
|
||||
|
||||
|
||||
/*
|
||||
|
|
@ -252,7 +254,9 @@ typedef struct PORT_REGISTER_DUMP
|
|||
* pdPASS is returned if the function executes successfully. Any other value
|
||||
* being returned indicates that the function did not execute correctly.
|
||||
*/
|
||||
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
|
||||
BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID,
|
||||
XInterruptHandler pxHandler,
|
||||
void * pvCallBackRef );
|
||||
|
||||
|
||||
/*
|
||||
|
|
@ -273,7 +277,7 @@ BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandle
|
|||
* XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
|
||||
*
|
||||
*/
|
||||
void vPortEnableInterrupt( uint8_t ucInterruptID );
|
||||
void vPortEnableInterrupt( uint8_t ucInterruptID );
|
||||
|
||||
/*
|
||||
* Disables the interrupt, within the interrupt controller, for the peripheral
|
||||
|
|
@ -293,7 +297,7 @@ void vPortEnableInterrupt( uint8_t ucInterruptID );
|
|||
* XPAR_INTC_0_GPIO_1_VEC_ID - for the button inputs.
|
||||
*
|
||||
*/
|
||||
void vPortDisableInterrupt( uint8_t ucInterruptID );
|
||||
void vPortDisableInterrupt( uint8_t ucInterruptID );
|
||||
|
||||
/*
|
||||
* This is an application defined callback function used to install the tick
|
||||
|
|
@ -305,7 +309,7 @@ void vPortDisableInterrupt( uint8_t ucInterruptID );
|
|||
* The name of the interrupt handler that should be installed is vPortTickISR(),
|
||||
* which the function below declares as an extern.
|
||||
*/
|
||||
void vApplicationSetupTimerInterrupt( void );
|
||||
void vApplicationSetupTimerInterrupt( void );
|
||||
|
||||
/*
|
||||
* This is an application defined callback function used to clear whichever
|
||||
|
|
@ -318,7 +322,7 @@ void vApplicationSetupTimerInterrupt( void );
|
|||
* implementation should not require modification provided the example definition
|
||||
* of vApplicationSetupTimerInterrupt() is also not modified.
|
||||
*/
|
||||
void vApplicationClearTimerInterrupt( void );
|
||||
void vApplicationClearTimerInterrupt( void );
|
||||
|
||||
/*
|
||||
* vPortExceptionsInstallHandlers() is only available when the MicroBlaze
|
||||
|
|
@ -341,7 +345,7 @@ void vApplicationClearTimerInterrupt( void );
|
|||
* See the description of vApplicationExceptionRegisterDump() for information
|
||||
* on the processing performed by the FreeRTOS exception handler.
|
||||
*/
|
||||
void vPortExceptionsInstallHandlers( void );
|
||||
void vPortExceptionsInstallHandlers( void );
|
||||
|
||||
/*
|
||||
* The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
|
||||
|
|
@ -357,12 +361,11 @@ void vPortExceptionsInstallHandlers( void );
|
|||
* register dump information. For example, an implementation could be provided
|
||||
* that wrote the register dump data to a display, or a UART port.
|
||||
*/
|
||||
void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
|
||||
void vApplicationExceptionRegisterDump( xPortRegisterDump * xRegisterDump );
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue