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a5dbc2b1de
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406 changed files with 108795 additions and 106323 deletions
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@ -34,143 +34,144 @@
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#include <sys/ports_def.h>
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the HCS12 port.
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*----------------------------------------------------------*/
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* Implementation of functions defined in portable.h for the HCS12 port.
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*----------------------------------------------------------*/
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/*
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* Configure a timer to generate the RTOS tick at the frequency specified
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* Configure a timer to generate the RTOS tick at the frequency specified
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* within FreeRTOSConfig.h.
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*/
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static void prvSetupTimerInterrupt( void );
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/* NOTE: Interrupt service routines must be in non-banked memory - as does the
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scheduler startup function. */
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#define ATTR_NEAR __attribute__((near))
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* scheduler startup function. */
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#define ATTR_NEAR __attribute__( ( near ) )
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/* Manual context switch function. This is the SWI ISR. */
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// __attribute__((interrupt))
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/* __attribute__((interrupt)) */
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void ATTR_NEAR vPortYield( void );
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/* Tick context switch function. This is the timer ISR. */
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// __attribute__((interrupt))
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/* __attribute__((interrupt)) */
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void ATTR_NEAR vPortTickInterrupt( void );
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/* Function in non-banked memory which actually switches to first task. */
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BaseType_t ATTR_NEAR xStartSchedulerNear( void );
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/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
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critical section should not be left (i.e. interrupts should not be re-enabled)
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until the nesting depth reaches 0. This variable simply tracks the nesting
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depth. Each task maintains it's own critical nesting depth variable so
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uxCriticalNesting is saved and restored from the task stack during a context
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switch. */
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volatile UBaseType_t uxCriticalNesting = 0x80; // un-initialized
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/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
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* critical section should not be left (i.e. interrupts should not be re-enabled)
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* until the nesting depth reaches 0. This variable simply tracks the nesting
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* depth. Each task maintains it's own critical nesting depth variable so
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* uxCriticalNesting is saved and restored from the task stack during a context
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* switch. */
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volatile UBaseType_t uxCriticalNesting = 0x80; /* un-initialized */
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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/*
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* See header file for description.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/* Setup the initial stack of the task. The stack is set exactly as
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* expected by the portRESTORE_CONTEXT() macro. In this case the stack as
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* expected by the HCS12 RTI instruction. */
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/* Setup the initial stack of the task. The stack is set exactly as
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expected by the portRESTORE_CONTEXT() macro. In this case the stack as
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expected by the HCS12 RTI instruction. */
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/* The address of the task function is placed in the stack byte at a time. */
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*pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 1 );
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*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pxCode ) ) + 0 );
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/* Next are all the registers that form part of the task context. */
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/* The address of the task function is placed in the stack byte at a time. */
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*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
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*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
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/* Y register */
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*--pxTopOfStack = ( StackType_t ) 0xff;
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*--pxTopOfStack = ( StackType_t ) 0xee;
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/* Next are all the registers that form part of the task context. */
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/* X register */
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*--pxTopOfStack = ( StackType_t ) 0xdd;
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*--pxTopOfStack = ( StackType_t ) 0xcc;
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/* Y register */
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*--pxTopOfStack = ( StackType_t ) 0xff;
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*--pxTopOfStack = ( StackType_t ) 0xee;
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/* A register contains parameter high byte. */
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*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 0 );
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/* X register */
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*--pxTopOfStack = ( StackType_t ) 0xdd;
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*--pxTopOfStack = ( StackType_t ) 0xcc;
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/* A register contains parameter high byte. */
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*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
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/* B register contains parameter low byte. */
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*--pxTopOfStack = ( StackType_t ) *( ( ( StackType_t * ) ( &pvParameters ) ) + 1 );
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/* B register contains parameter low byte. */
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*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
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/* CCR: Note that when the task starts interrupts will be enabled since
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* "I" bit of CCR is cleared */
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*--pxTopOfStack = ( StackType_t ) 0x80; /* keeps Stop disabled (MCU default) */
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/* CCR: Note that when the task starts interrupts will be enabled since
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"I" bit of CCR is cleared */
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*--pxTopOfStack = ( StackType_t ) 0x80; // keeps Stop disabled (MCU default)
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/* tmp softregs used by GCC. Values right now don't matter. */
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__asm("\n\
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/* tmp softregs used by GCC. Values right now don't matter. */
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__asm( "\n\
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movw _.frame, 2,-%0 \n\
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movw _.tmp, 2,-%0 \n\
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movw _.z, 2,-%0 \n\
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movw _.xy, 2,-%0 \n\
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;movw _.d2, 2,-%0 \n\
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;movw _.d1, 2,-%0 \n\
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": "=A"(pxTopOfStack) : "0"(pxTopOfStack) );
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" : "=A" ( pxTopOfStack ) : "0" ( pxTopOfStack ) );
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#ifdef BANKED_MODEL
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/* The page of the task. */
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*--pxTopOfStack = 0x30; // can only directly start in PPAGE 0x30
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#endif
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/* The critical nesting depth is initialised with 0 (meaning not in
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a critical section). */
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*--pxTopOfStack = ( StackType_t ) 0x00;
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#ifdef BANKED_MODEL
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/* The page of the task. */
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*--pxTopOfStack = 0x30; /* can only directly start in PPAGE 0x30 */
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#endif
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/* The critical nesting depth is initialised with 0 (meaning not in
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* a critical section). */
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*--pxTopOfStack = ( StackType_t ) 0x00;
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return pxTopOfStack;
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* It is unlikely that the HCS12 port will get stopped. */
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/* It is unlikely that the HCS12 port will get stopped. */
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}
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/*-----------------------------------------------------------*/
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static void prvSetupTimerInterrupt( void )
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{
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/* Enable hardware RTI timer */
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/* Ignores configTICK_RATE_HZ */
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RTICTL = 0x50; // 16 MHz xtal: 976.56 Hz, 1024mS
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CRGINT |= 0x80; // RTIE
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/* Enable hardware RTI timer */
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/* Ignores configTICK_RATE_HZ */
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RTICTL = 0x50; /* 16 MHz xtal: 976.56 Hz, 1024mS */
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CRGINT |= 0x80; /* RTIE */
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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/* xPortStartScheduler() does not start the scheduler directly because
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the header file containing the xPortStartScheduler() prototype is part
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of the common kernel code, and therefore cannot use the CODE_SEG pragma.
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Instead it simply calls the locally defined xNearStartScheduler() -
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which does use the CODE_SEG pragma. */
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/* xPortStartScheduler() does not start the scheduler directly because
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* the header file containing the xPortStartScheduler() prototype is part
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* of the common kernel code, and therefore cannot use the CODE_SEG pragma.
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* Instead it simply calls the locally defined xNearStartScheduler() -
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* which does use the CODE_SEG pragma. */
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int16_t register d;
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__asm ("jmp xStartSchedulerNear ; will never return": "=d"(d));
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return d;
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int16_t register d;
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__asm( "jmp xStartSchedulerNear ; will never return": "=d" ( d ) );
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return d;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xStartSchedulerNear( void )
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{
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/* Configure the timer that will generate the RTOS tick. Interrupts are
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disabled when this function is called. */
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prvSetupTimerInterrupt();
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/* Configure the timer that will generate the RTOS tick. Interrupts are
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* disabled when this function is called. */
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prvSetupTimerInterrupt();
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/* Restore the context of the first task. */
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portRESTORE_CONTEXT();
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/* Restore the context of the first task. */
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portRESTORE_CONTEXT();
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portISR_TAIL();
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portISR_TAIL();
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/* Should not get here! */
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return pdFALSE;
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/* Should not get here! */
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return pdFALSE;
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}
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/*-----------------------------------------------------------*/
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@ -184,53 +185,53 @@ BaseType_t xStartSchedulerNear( void )
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*/
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void vPortYield( void )
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{
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portISR_HEAD();
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/* NOTE: This is the trap routine (swi) although not defined as a trap.
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It will fill the stack the same way as an ISR in order to mix preemtion
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and cooperative yield. */
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portISR_HEAD();
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portSAVE_CONTEXT();
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vTaskSwitchContext();
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portRESTORE_CONTEXT();
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/* NOTE: This is the trap routine (swi) although not defined as a trap.
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* It will fill the stack the same way as an ISR in order to mix preemtion
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* and cooperative yield. */
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portISR_TAIL();
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portSAVE_CONTEXT();
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vTaskSwitchContext();
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portRESTORE_CONTEXT();
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portISR_TAIL();
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}
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/*-----------------------------------------------------------*/
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/*
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* RTOS tick interrupt service routine. If the cooperative scheduler is
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* being used then this simply increments the tick count. If the
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* RTOS tick interrupt service routine. If the cooperative scheduler is
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* being used then this simply increments the tick count. If the
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* preemptive scheduler is being used a context switch can occur.
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*/
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void vPortTickInterrupt( void )
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{
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portISR_HEAD();
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portISR_HEAD();
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/* Clear tick timer flag */
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CRGFLG = 0x80;
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/* Clear tick timer flag */
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CRGFLG = 0x80;
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#if configUSE_PREEMPTION == 1
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{
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/* A context switch might happen so save the context. */
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portSAVE_CONTEXT();
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#if configUSE_PREEMPTION == 1
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{
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/* A context switch might happen so save the context. */
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portSAVE_CONTEXT();
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/* Increment the tick ... */
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if( xTaskIncrementTick() != pdFALSE )
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{
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/* A context switch is necessary. */
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vTaskSwitchContext();
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}
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/* Increment the tick ... */
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if( xTaskIncrementTick() != pdFALSE )
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{
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/* A context switch is necessary. */
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vTaskSwitchContext();
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}
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/* Restore the context of a task - which may be a different task
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to that interrupted. */
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portRESTORE_CONTEXT();
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}
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#else
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{
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xTaskIncrementTick();
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}
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#endif
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/* Restore the context of a task - which may be a different task
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* to that interrupted. */
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portRESTORE_CONTEXT();
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}
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#else /* if configUSE_PREEMPTION == 1 */
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{
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xTaskIncrementTick();
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}
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#endif /* if configUSE_PREEMPTION == 1 */
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portISR_TAIL();
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portISR_TAIL();
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}
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@ -26,11 +26,11 @@
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#define PORTMACRO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*-----------------------------------------------------------
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* Port specific definitions.
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@ -43,38 +43,38 @@ extern "C" {
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*/
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint8_t
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#define portBASE_TYPE char
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint8_t
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#define portBASE_TYPE char
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typedef portSTACK_TYPE StackType_t;
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typedef signed char BaseType_t;
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typedef unsigned char UBaseType_t;
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typedef portSTACK_TYPE StackType_t;
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typedef signed char BaseType_t;
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typedef unsigned char UBaseType_t;
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#if( configUSE_16_BIT_TICKS == 1 )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#else
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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#endif
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#if ( configUSE_16_BIT_TICKS == 1 )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#else
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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#endif
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/*-----------------------------------------------------------*/
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/* Hardware specifics. */
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#define portBYTE_ALIGNMENT 1
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portYIELD() __asm( "swi" );
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#define portBYTE_ALIGNMENT 1
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portYIELD() __asm( "swi" );
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/*-----------------------------------------------------------*/
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/* Critical section handling. */
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#define portENABLE_INTERRUPTS() __asm( "cli" )
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#define portDISABLE_INTERRUPTS() __asm( "sei" )
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#define portENABLE_INTERRUPTS() __asm( "cli" )
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#define portDISABLE_INTERRUPTS() __asm( "sei" )
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/*
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* Disable interrupts before incrementing the count of critical section nesting.
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@ -82,29 +82,29 @@ typedef unsigned char UBaseType_t;
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* re-enabled. Once interrupts are disabled the nesting count can be accessed
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* directly. Each task maintains its own nesting count.
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*/
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#define portENTER_CRITICAL() \
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{ \
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extern volatile UBaseType_t uxCriticalNesting; \
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\
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portDISABLE_INTERRUPTS(); \
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uxCriticalNesting++; \
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}
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#define portENTER_CRITICAL() \
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{ \
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extern volatile UBaseType_t uxCriticalNesting; \
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\
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portDISABLE_INTERRUPTS(); \
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uxCriticalNesting++; \
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}
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/*
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* Interrupts are disabled so we can access the nesting count directly. If the
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* nesting is found to be 0 (no nesting) then we are leaving the critical
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* section and interrupts can be re-enabled.
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*/
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#define portEXIT_CRITICAL() \
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{ \
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extern volatile UBaseType_t uxCriticalNesting; \
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\
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uxCriticalNesting--; \
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if( uxCriticalNesting == 0 ) \
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{ \
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portENABLE_INTERRUPTS(); \
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} \
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}
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#define portEXIT_CRITICAL() \
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{ \
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extern volatile UBaseType_t uxCriticalNesting; \
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\
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uxCriticalNesting--; \
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if( uxCriticalNesting == 0 ) \
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{ \
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portENABLE_INTERRUPTS(); \
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} \
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}
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/*-----------------------------------------------------------*/
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/* Task utilities. */
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|
@ -119,15 +119,16 @@ typedef unsigned char UBaseType_t;
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* register is also stored as part of the tasks context.
|
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*/
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|
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#ifdef BANKED_MODEL
|
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/*
|
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* Load the stack pointer for the task, then pull the critical nesting
|
||||
* count and PPAGE register from the stack. The remains of the
|
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* context are restored by the RTI instruction.
|
||||
*/
|
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#define portRESTORE_CONTEXT() \
|
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{ \
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__asm( " \n\
|
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#ifdef BANKED_MODEL
|
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|
||||
/*
|
||||
* Load the stack pointer for the task, then pull the critical nesting
|
||||
* count and PPAGE register from the stack. The remains of the
|
||||
* context are restored by the RTI instruction.
|
||||
*/
|
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#define portRESTORE_CONTEXT() \
|
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{ \
|
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__asm( " \n\
|
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.globl pxCurrentTCB ; void * \n\
|
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.globl uxCriticalNesting ; char \n\
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\n\
|
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|
@ -136,17 +137,17 @@ typedef unsigned char UBaseType_t;
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\n\
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movb 1,sp+,uxCriticalNesting \n\
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movb 1,sp+,0x30 ; PPAGE \n\
|
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" ); \
|
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}
|
||||
" ); \
|
||||
}
|
||||
|
||||
/*
|
||||
* By the time this macro is called the processor has already stacked the
|
||||
* registers. Simply stack the nesting count and PPAGE value, then save
|
||||
* the task stack pointer.
|
||||
*/
|
||||
#define portSAVE_CONTEXT() \
|
||||
{ \
|
||||
__asm( " \n\
|
||||
/*
|
||||
* By the time this macro is called the processor has already stacked the
|
||||
* registers. Simply stack the nesting count and PPAGE value, then save
|
||||
* the task stack pointer.
|
||||
*/
|
||||
#define portSAVE_CONTEXT() \
|
||||
{ \
|
||||
__asm( " \n\
|
||||
.globl pxCurrentTCB ; void * \n\
|
||||
.globl uxCriticalNesting ; char \n\
|
||||
\n\
|
||||
|
@ -155,18 +156,18 @@ typedef unsigned char UBaseType_t;
|
|||
\n\
|
||||
ldx pxCurrentTCB \n\
|
||||
sts 0,x ; Stack \n\
|
||||
" ); \
|
||||
}
|
||||
#else
|
||||
" ); \
|
||||
}
|
||||
#else /* ifdef BANKED_MODEL */
|
||||
|
||||
/*
|
||||
* These macros are as per the BANKED versions above, but without saving
|
||||
* and restoring the PPAGE register.
|
||||
*/
|
||||
/*
|
||||
* These macros are as per the BANKED versions above, but without saving
|
||||
* and restoring the PPAGE register.
|
||||
*/
|
||||
|
||||
#define portRESTORE_CONTEXT() \
|
||||
{ \
|
||||
__asm( " \n\
|
||||
#define portRESTORE_CONTEXT() \
|
||||
{ \
|
||||
__asm( " \n\
|
||||
.globl pxCurrentTCB ; void * \n\
|
||||
.globl uxCriticalNesting ; char \n\
|
||||
\n\
|
||||
|
@ -174,12 +175,12 @@ typedef unsigned char UBaseType_t;
|
|||
lds 0,x ; Stack \n\
|
||||
\n\
|
||||
movb 1,sp+,uxCriticalNesting \n\
|
||||
" ); \
|
||||
}
|
||||
" ); \
|
||||
}
|
||||
|
||||
#define portSAVE_CONTEXT() \
|
||||
{ \
|
||||
__asm( " \n\
|
||||
#define portSAVE_CONTEXT() \
|
||||
{ \
|
||||
__asm( " \n\
|
||||
.globl pxCurrentTCB ; void * \n\
|
||||
.globl uxCriticalNesting ; char \n\
|
||||
\n\
|
||||
|
@ -187,29 +188,29 @@ typedef unsigned char UBaseType_t;
|
|||
\n\
|
||||
ldx pxCurrentTCB \n\
|
||||
sts 0,x ; Stack \n\
|
||||
" ); \
|
||||
}
|
||||
#endif
|
||||
" ); \
|
||||
}
|
||||
#endif /* ifdef BANKED_MODEL */
|
||||
|
||||
/*
|
||||
* Utility macros to save/restore correct software registers for GCC. This is
|
||||
* useful when GCC does not generate appropriate ISR head/tail code.
|
||||
*/
|
||||
#define portISR_HEAD() \
|
||||
{ \
|
||||
__asm(" \n\
|
||||
#define portISR_HEAD() \
|
||||
{ \
|
||||
__asm( " \n\
|
||||
movw _.frame, 2,-sp \n\
|
||||
movw _.tmp, 2,-sp \n\
|
||||
movw _.z, 2,-sp \n\
|
||||
movw _.xy, 2,-sp \n\
|
||||
;movw _.d2, 2,-sp \n\
|
||||
;movw _.d1, 2,-sp \n\
|
||||
"); \
|
||||
}
|
||||
" ); \
|
||||
}
|
||||
|
||||
#define portISR_TAIL() \
|
||||
{ \
|
||||
__asm(" \n\
|
||||
#define portISR_TAIL() \
|
||||
{ \
|
||||
__asm( " \n\
|
||||
movw 2,sp+, _.xy \n\
|
||||
movw 2,sp+, _.z \n\
|
||||
movw 2,sp+, _.tmp \n\
|
||||
|
@ -217,8 +218,8 @@ typedef unsigned char UBaseType_t;
|
|||
;movw 2,sp+, _.d1 \n\
|
||||
;movw 2,sp+, _.d2 \n\
|
||||
rti \n\
|
||||
"); \
|
||||
}
|
||||
" ); \
|
||||
}
|
||||
|
||||
/*
|
||||
* Utility macro to call macros above in correct order in order to perform a
|
||||
|
@ -227,19 +228,18 @@ typedef unsigned char UBaseType_t;
|
|||
* variables portYIELD() should be used in it's place.
|
||||
*/
|
||||
|
||||
#define portTASK_SWITCH_FROM_ISR() \
|
||||
portSAVE_CONTEXT(); \
|
||||
vTaskSwitchContext(); \
|
||||
portRESTORE_CONTEXT();
|
||||
#define portTASK_SWITCH_FROM_ISR() \
|
||||
portSAVE_CONTEXT(); \
|
||||
vTaskSwitchContext(); \
|
||||
portRESTORE_CONTEXT();
|
||||
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue