mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-09-01 11:53:53 -04:00
Start of a new ColdFire/CodeWarrior demo.
This commit is contained in:
parent
8e219f83f0
commit
709b7ee223
57 changed files with 8456 additions and 0 deletions
48
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RCM.h
Normal file
48
Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221_RCM.h
Normal file
|
@ -0,0 +1,48 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.95
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF52221_RCM_H__
|
||||
#define __MCF52221_RCM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Reset Controller Module (RCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RCM_RCR (*(vuint8 *)(0x40110000))
|
||||
#define MCF_RCM_RSR (*(vuint8 *)(0x40110001))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RCR */
|
||||
#define MCF_RCM_RCR_LVDE (0x1)
|
||||
#define MCF_RCM_RCR_LVDRE (0x4)
|
||||
#define MCF_RCM_RCR_LVDIE (0x8)
|
||||
#define MCF_RCM_RCR_LVDF (0x10)
|
||||
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
|
||||
#define MCF_RCM_RCR_SOFTRST (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RSR */
|
||||
#define MCF_RCM_RSR_LOL (0x1)
|
||||
#define MCF_RCM_RSR_LOC (0x2)
|
||||
#define MCF_RCM_RSR_EXT (0x4)
|
||||
#define MCF_RCM_RSR_POR (0x8)
|
||||
#define MCF_RCM_RSR_SOFT (0x20)
|
||||
#define MCF_RCM_RSR_LVD (0x40)
|
||||
|
||||
|
||||
#endif /* __MCF52221_RCM_H__ */
|
Loading…
Add table
Add a link
Reference in a new issue