mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 13:01:57 -04:00
Armv8.1-m: Add pacbti support (#1147)
* copyright-checker: Add FreeRTOS Arm collab copyright FreeRTOS Arm collab files shall have both Amazon's and Arm's copyright headers. Hence, the copyright checker is modified to check for both copyrights. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> * armv8-m: Add support for IAR with TFM FREERTOS PORT As the case for ARMClang, and GCC toolchains, IAR with TFM FreeRTOS Port support is added. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> * armv8-m: Do not overwrite Control register value The current ARMv8-M FreeRTOS-Kernel Port code implementation is modified in a way that allows the CONTROL register's value to be retained rather than being overwritten. This is needed for adding PACBTI support as the special-purpose CONTROL register `PAC_EN`, `UPAC_EN`, `BTI_EN`, and `UBTI_EN` PACBTI enablement bits should be configured before calling `vRestoreContextOfFirstTask()` function which currently overwrite the value inside the CONTROL register. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> * armv8.1-m: Add PACBTI support to kernel non-secure implementation In this commit, Pointer Authentication, and Branch Target Identification Extension (PACBTI) support is added for Non-Secure and Non-TrustZone variants of Cortex-M85 FreeRTOS-Kernel Port. The PACBTI support is added for Arm Compiler For Embedded, and IAR toolchains only. The support in the kernel is not yet enabled for GNU toolchain due to known issues. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> * Fix CI check Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> --------- Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> Co-authored-by: Ahmed Ismail <ahmism01@e133373.arm.com> Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Ahmed Ismail
GitHub
parent
e400cc93b7
commit
7081e76f5a
5
.github/.cSpellWords.txt
vendored
5
.github/.cSpellWords.txt
vendored
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@ -448,6 +448,7 @@ MAINRDY
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MAIR
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Mang
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Mbits
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mbranch
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mcause
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MCFR
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MCKA
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@ -586,6 +587,8 @@ OWATCOM
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OWDR
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OWER
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OWSR
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pacbti
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PACBTI
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PAGEN
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PCDR
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PCER
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@ -900,6 +903,7 @@ TXTEN
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TXUBR
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TXVC
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TXVDIS
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UBTI
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UDCP
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UNACKED
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uncrustify
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@ -915,6 +919,7 @@ UNSUB
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UNSUBACK
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unsubscriptions
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unsuspended
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UPAC
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URAD
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URAT
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URSTEN
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85
.github/scripts/kernel_checker.py
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85
.github/scripts/kernel_checker.py
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@ -28,6 +28,7 @@
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# */
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import os
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import re
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from common.header_checker import HeaderChecker
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#--------------------------------------------------------------------------------------------------
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@ -106,6 +107,15 @@ KERNEL_THIRD_PARTY_PATTERNS = [
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r'.*portable/GCC/AVR32_UC3/.*',
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]
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KERNEL_ARM_COLLAB_FILES_PATTERNS = [
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r'.*portable/ARMv8M/*',
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r'.*portable/.*/ARM_CM23*',
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r'.*portable/.*/ARM_CM33*',
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r'.*portable/.*/ARM_CM35*',
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r'.*portable/.*/ARM_CM55*',
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r'.*portable/.*/ARM_CM85*',
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]
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KERNEL_HEADER = [
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'/*\n',
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' * FreeRTOS Kernel <DEVELOPMENT BRANCH>\n',
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@ -139,12 +149,85 @@ KERNEL_HEADER = [
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FREERTOS_COPYRIGHT_REGEX = r"^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$"
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FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX = r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$)|" + \
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r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d Arm Limited and/or its affiliates( \*\/)?$)|" + \
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r"(^(;|#)?( *(\/\*|\*|#|\/\/))? <open-source-office@arm.com>( \*\/)?$)"
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class KernelHeaderChecker(HeaderChecker):
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def __init__(
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self,
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header,
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padding=1000,
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ignored_files=None,
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ignored_ext=None,
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ignored_patterns=None,
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py_ext=None,
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asm_ext=None,
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third_party_patterns=None,
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copyright_regex = None
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):
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super().__init__(header, padding, ignored_files, ignored_ext, ignored_patterns,
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py_ext, asm_ext, third_party_patterns, copyright_regex)
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self.armCollabRegex = re.compile(FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX)
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self.armCollabFilesPatternList = []
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for pattern in KERNEL_ARM_COLLAB_FILES_PATTERNS:
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self.armCollabFilesPatternList.append(re.compile(pattern))
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def isArmCollabFile(self, path):
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for pattern in self.armCollabFilesPatternList:
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if pattern.match(path):
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return True
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return False
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def checkArmCollabFile(self, path):
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isValid = False
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file_ext = os.path.splitext(path)[-1]
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with open(path, encoding="utf-8", errors="ignore") as file:
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chunk = file.read(len("".join(self.header)) + self.padding)
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lines = [("%s\n" % line) for line in chunk.strip().splitlines()][
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: len(self.header) + 2
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]
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if (len(lines) > 0) and (lines[0].find("#!") == 0):
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lines.remove(lines[0])
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# Split lines in sections.
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headers = dict()
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headers["text"] = []
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headers["copyright"] = []
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headers["spdx"] = []
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for line in lines:
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if self.armCollabRegex.match(line):
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headers["copyright"].append(line)
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elif "SPDX-License-Identifier:" in line:
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headers["spdx"].append(line)
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else:
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headers["text"].append(line)
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text_equal = self.isValidHeaderSection(file_ext, "text", headers["text"])
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spdx_equal = self.isValidHeaderSection(file_ext, "spdx", headers["spdx"])
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if text_equal and spdx_equal and len(headers["copyright"]) == 3:
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isValid = True
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return isValid
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def customCheck(self, path):
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isValid = False
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if self.isArmCollabFile(path):
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isValid = self.checkArmCollabFile(path)
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return isValid
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def main():
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parser = HeaderChecker.configArgParser()
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args = parser.parse_args()
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# Configure the checks then run
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checker = HeaderChecker(KERNEL_HEADER,
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checker = KernelHeaderChecker(KERNEL_HEADER,
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copyright_regex=FREERTOS_COPYRIGHT_REGEX,
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ignored_files=KERNEL_IGNORED_FILES,
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ignored_ext=KERNEL_IGNORED_EXTENSIONS,
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@ -138,15 +138,18 @@ if(NOT FREERTOS_PORT)
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" IAR_ARM_CM33_NONSECURE - Compiler: IAR Target: ARM Cortex-M33 non-secure\n"
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" IAR_ARM_CM33_SECURE - Compiler: IAR Target: ARM Cortex-M33 secure\n"
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" IAR_ARM_CM33_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M33 non-trustzone non-secure\n"
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" IAR_ARM_CM33_TFM - Compiler: IAR Target: ARM Cortex-M33 non-secure for TF-M\n"
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" IAR_ARM_CM35P_NONSECURE - Compiler: IAR Target: ARM Cortex-M35P non-secure\n"
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" IAR_ARM_CM35P_SECURE - Compiler: IAR Target: ARM Cortex-M35P secure\n"
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" IAR_ARM_CM35P_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M35P non-trustzone non-secure\n"
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" IAR_ARM_CM55_NONSECURE - Compiler: IAR Target: ARM Cortex-M55 non-secure\n"
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" IAR_ARM_CM55_SECURE - Compiler: IAR Target: ARM Cortex-M55 secure\n"
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" IAR_ARM_CM55_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M55 non-trustzone non-secure\n"
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" IAR_ARM_CM55_TFM - Compiler: IAR Target: ARM Cortex-M55 non-secure for TF-M\n"
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" IAR_ARM_CM85_NONSECURE - Compiler: IAR Target: ARM Cortex-M85 non-secure\n"
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" IAR_ARM_CM85_SECURE - Compiler: IAR Target: ARM Cortex-M85 secure\n"
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" IAR_ARM_CM85_NTZ_NONSECURE - Compiler: IAR Target: ARM Cortex-M85 non-trustzone non-secure\n"
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" IAR_ARM_CM85_TFM - Compiler: IAR Target: ARM Cortex-M85 non-secure for TF-M\n"
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" IAR_ARM_CRX_NOGIC - Compiler: IAR Target: ARM Cortex-Rx no GIC\n"
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" IAR_ATMEGA323 - Compiler: IAR Target: ATMega323\n"
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" IAR_ATMEL_SAM7S64 - Compiler: IAR Target: Atmel SAM7S64\n"
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@ -17,7 +17,7 @@ files.
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## Getting Started
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### Prerequisites
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Coverity can be run on any platform mentioned [here](https://sig-docs.synopsys.com/polaris/topics/c_coverity-compatible-platforms.html).
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Coverity can be run on any platform mentioned [here](https://documentation.blackduck.com/bundle/coverity-docs/page/deploy-install-guide/topics/supported_platforms_for_coverity_analysis.html).
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The following are the prerequisites to generate coverity report:
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1. CMake version > 3.13.0 (You can check whether you have this by typing `cmake --version`).
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@ -3032,6 +3032,18 @@
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#define configCONTROL_INFINITE_LOOP()
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#endif
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/* Set configENABLE_PAC and/or configENABLE_BTI to 1 to enable PAC and/or BTI
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* support and 0 to disable them. These are currently used in ARMv8.1-M ports. */
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#if ( portHAS_PACBTI_FEATURE == 1 )
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#ifndef configENABLE_PAC
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#define configENABLE_PAC 0
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#endif
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#ifndef configENABLE_BTI
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#define configENABLE_BTI 0
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#endif
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#endif
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/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
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* dynamically allocated RAM, in which case when any task is deleted it is known
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* that both the task's stack and TCB need to be freed. Sometimes the
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2024 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
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#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
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#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
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#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
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#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
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/*-----------------------------------------------------------*/
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/**
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@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
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* any secure calls.
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*/
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#define portNO_SECURE_CONTEXT 0
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/**
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* @brief Constants required to check and configure PACBTI security feature implementation.
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*/
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#if ( portHAS_PACBTI_FEATURE == 1 )
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#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
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#define portCONTROL_UPAC_EN ( 1UL << 7UL )
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#define portCONTROL_PAC_EN ( 1UL << 6UL )
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#define portCONTROL_UBTI_EN ( 1UL << 5UL )
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#define portCONTROL_BTI_EN ( 1UL << 4UL )
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#endif /* portHAS_PACBTI_FEATURE */
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/*-----------------------------------------------------------*/
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/**
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@ -410,6 +427,26 @@ static void prvTaskExitError( void );
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static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
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#endif /* configENABLE_FPU */
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#if ( portHAS_PACBTI_FEATURE == 1 )
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/**
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* @brief Configures PACBTI features.
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*
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* This function configures the Pointer Authentication, and Branch Target
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* Identification security features as per the user configuration. It returns
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* the value of the special purpose CONTROL register accordingly, and optionally
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* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
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* architecture based) target supports PACBTI security feature.
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*
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* @param xWriteControlRegister Used to control whether the special purpose
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* CONTROL register should be updated or not.
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*
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* @return CONTROL register value according to the configured PACBTI option.
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*/
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static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
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#endif /* portHAS_PACBTI_FEATURE */
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/**
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* @brief Setup the timer to generate the tick interrupts.
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*
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@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
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{
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uint32_t ulIndex = 0;
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uint32_t ulControl = 0x0;
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xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
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ulIndex++;
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@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
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xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
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ulIndex++;
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#if ( portHAS_PACBTI_FEATURE == 1 )
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{
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/* Check PACBTI security feature configuration before pushing the
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* CONTROL register's value on task's TCB. */
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ulControl = prvConfigurePACBTI( pdFALSE );
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}
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#endif /* portHAS_PACBTI_FEATURE */
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if( xRunPrivileged == pdTRUE )
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{
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xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
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xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
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xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
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ulIndex++;
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}
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else
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{
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xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
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xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
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xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
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ulIndex++;
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}
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@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
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portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
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portNVIC_SHPR2_REG = 0;
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#if ( portHAS_PACBTI_FEATURE == 1 )
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{
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/* Set the CONTROL register value based on PACBTI security feature
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* configuration before starting the first task. */
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( void) prvConfigurePACBTI( pdTRUE );
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}
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#endif /* portHAS_PACBTI_FEATURE */
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#if ( configENABLE_MPU == 1 )
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{
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/* Setup the Memory Protection Unit (MPU). */
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@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
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#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
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/*-----------------------------------------------------------*/
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#if ( portHAS_PACBTI_FEATURE == 1 )
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static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
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{
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uint32_t ulControl = 0x0;
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/* Ensure that PACBTI is implemented. */
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configASSERT( portID_ISAR5_REG != 0x0 );
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/* Enable UsageFault exception if PAC or BTI is enabled. */
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#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
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{
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portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
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}
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#endif
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#if( configENABLE_PAC == 1 )
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{
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ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
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}
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#endif
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#if( configENABLE_BTI == 1 )
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{
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ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
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}
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#endif
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if( xWriteControlRegister == pdTRUE )
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{
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__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
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}
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return ulControl;
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}
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#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
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/*-----------------------------------------------------------*/
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|
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@ -1,6 +1,8 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
|
||||
*
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@ -51,6 +53,7 @@
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#define portARCH_NAME "Cortex-M23"
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#define portHAS_ARMV8M_MAIN_EXTENSION 0
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#define portARMV8M_MINOR_VERSION 0
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#define portHAS_PACBTI_FEATURE 0
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#define portDONT_DISCARD __attribute__( ( used ) )
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/*-----------------------------------------------------------*/
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|
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|
|
|
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|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -134,8 +136,9 @@
|
|||
" ldr r4, =xSecureContext \n"
|
||||
" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
|
||||
" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -130,8 +132,9 @@
|
|||
" \n"
|
||||
" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
" msr psplim, r1 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
|
|||
ldr r4, =xSecureContext
|
||||
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
|
||||
msr psplim, r2 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
|
|||
|
||||
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
msr psplim, r1 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -453,6 +453,12 @@ add_library(freertos_kernel_port OBJECT
|
|||
IAR/ARM_CM33_NTZ/non_secure/portasm.s
|
||||
IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S>
|
||||
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_TFM>:
|
||||
IAR/ARM_CM33_NTZ/non_secure/port.c
|
||||
IAR/ARM_CM33_NTZ/non_secure/portasm.s
|
||||
IAR/ARM_CM33_NTZ/non_secure/mpu_wrappers_v2_asm.S
|
||||
ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
|
||||
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM35P_NONSECURE>:
|
||||
IAR/ARM_CM35P/non_secure/port.c
|
||||
IAR/ARM_CM35P/non_secure/portasm.s
|
||||
|
|
@ -486,6 +492,12 @@ add_library(freertos_kernel_port OBJECT
|
|||
IAR/ARM_CM55_NTZ/non_secure/portasm.s
|
||||
IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S>
|
||||
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_TFM>:
|
||||
IAR/ARM_CM55_NTZ/non_secure/port.c
|
||||
IAR/ARM_CM55_NTZ/non_secure/portasm.s
|
||||
IAR/ARM_CM55_NTZ/non_secure/mpu_wrappers_v2_asm.S
|
||||
ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
|
||||
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NONSECURE>:
|
||||
IAR/ARM_CM85/non_secure/port.c
|
||||
IAR/ARM_CM85/non_secure/portasm.s
|
||||
|
|
@ -502,6 +514,12 @@ add_library(freertos_kernel_port OBJECT
|
|||
IAR/ARM_CM85_NTZ/non_secure/portasm.s
|
||||
IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S>
|
||||
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_TFM>:
|
||||
IAR/ARM_CM85_NTZ/non_secure/port.c
|
||||
IAR/ARM_CM85_NTZ/non_secure/portasm.s
|
||||
IAR/ARM_CM85_NTZ/non_secure/mpu_wrappers_v2_asm.S
|
||||
ThirdParty/GCC/ARM_TFM/os_wrapper_freertos.c>
|
||||
|
||||
# ARMv7-R Ports for IAR EWARM
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CRX_NOGIC>:
|
||||
IAR/ARM_CRx_No_GIC/port.c
|
||||
|
|
@ -755,13 +773,112 @@ if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR
|
|||
FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|55|85)_NONSECURE" OR
|
||||
FREERTOS_PORT MATCHES "GCC_ARM_CM(33|55|85)_TFM" OR
|
||||
FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NTZ_NONSECURE" OR
|
||||
FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NONSECURE"
|
||||
FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|55|85)_NONSECURE" OR
|
||||
FREERTOS_PORT MATCHES "IAR_ARM_CM(33|55|85)_TFM"
|
||||
)
|
||||
target_sources(freertos_kernel_port PRIVATE
|
||||
Common/mpu_wrappers.c
|
||||
Common/mpu_wrappers_v2.c
|
||||
)
|
||||
endif()
|
||||
|
||||
if (DEFINED FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG )
|
||||
|
||||
if(${CMAKE_C_COMPILER_ID} STREQUAL "GNU")
|
||||
message(FATAL_ERROR "ARMv8.1-M PACBTI support in the kernel is not yet enabled for GNU toolchain due to known issues.")
|
||||
endif()
|
||||
|
||||
if(FREERTOS_PORT MATCHES ".*ARM_CM85")
|
||||
if(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_STANDARD")
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=standard>)
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=bti+pac-ret>>)
|
||||
target_compile_definitions(freertos_config
|
||||
INTERFACE
|
||||
configENABLE_PAC=1
|
||||
configENABLE_BTI=1
|
||||
)
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI")
|
||||
if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang")
|
||||
target_compile_options(freertos_kernel_port
|
||||
PUBLIC
|
||||
-mbranch-protection=bti+pac-ret+leaf
|
||||
)
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_PAC=1
|
||||
configENABLE_BTI=1
|
||||
)
|
||||
elseif(${CMAKE_C_COMPILER_ID} STREQUAL "IAR")
|
||||
message(FATAL_ERROR "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI PACBTI option is not supported on IAR Compiler.")
|
||||
endif()
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET")
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=pac-ret>)
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=pac-ret>>)
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_PAC=1
|
||||
)
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF")
|
||||
if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang")
|
||||
target_compile_options(freertos_kernel_port
|
||||
PUBLIC
|
||||
-mbranch-protection=pac-ret+leaf
|
||||
)
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_PAC=1
|
||||
)
|
||||
elseif(${CMAKE_C_COMPILER_ID} STREQUAL "IAR")
|
||||
message(FATAL_ERROR "ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF PACBTI option is not supported on IAR Compiler.")
|
||||
endif()
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_BTI")
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},ARMClang>:-mbranch-protection=bti>)
|
||||
target_compile_options(freertos_kernel_port PUBLIC $<$<STREQUAL:${CMAKE_C_COMPILER_ID},IAR>:$<$<COMPILE_LANGUAGE:C,CXX>:--branch_protection=bti>>)
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_BTI=1
|
||||
)
|
||||
elseif(FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE")
|
||||
if(${CMAKE_C_COMPILER_ID} STREQUAL "ARMClang")
|
||||
target_compile_options(freertos_kernel_port
|
||||
PUBLIC
|
||||
-mbranch-protection=none
|
||||
)
|
||||
endif()
|
||||
target_compile_definitions(freertos_config
|
||||
PUBLIC
|
||||
configENABLE_PAC=0
|
||||
configENABLE_BTI=0
|
||||
)
|
||||
else()
|
||||
message(FATAL_ERROR "Invalid FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG configuration, the supported configurations are
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_STANDARD,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF_BTI,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_PACRET,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_PACRET_LEAF,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_BTI,
|
||||
ARM_V_8_1_M_PACBTI_CONFIG_NONE
|
||||
")
|
||||
endif()
|
||||
if(NOT FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG STREQUAL "ARM_V_8_1_M_PACBTI_CONFIG_NONE")
|
||||
# The reason why `--library_security=pacbti-m` link option is defined for both `freertos_kernel_port`, and
|
||||
# `freertos_kernel` targets even though `freertos_kernel_port` gets linked to `freertos_kernel` is that the
|
||||
# `freertos_kernel_port` is an object library where its linker options don't propagate to the targets that
|
||||
# link against it.
|
||||
target_link_options(freertos_kernel_port
|
||||
PUBLIC
|
||||
--library_security=pacbti-m
|
||||
)
|
||||
target_link_options(freertos_kernel
|
||||
PUBLIC
|
||||
--library_security=pacbti-m
|
||||
)
|
||||
endif()
|
||||
else()
|
||||
message(FATAL_ERROR "FREERTOS_ARM_V_8_1_M_PACBTI_CONFIG option is currently only supported on ARM Cortex-M85 FreeRTOS port.")
|
||||
endif()
|
||||
endif()
|
||||
|
||||
add_library(freertos_kernel_port_headers INTERFACE)
|
||||
|
||||
target_include_directories(freertos_kernel_port_headers INTERFACE
|
||||
|
|
@ -956,6 +1073,7 @@ target_include_directories(freertos_kernel_port_headers INTERFACE
|
|||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/non_secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33/secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33_NTZ/non_secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM33_TFM>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM33_NTZ/non_secure>
|
||||
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM35P_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM35P/non_secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM35P_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM35P/secure>
|
||||
|
|
@ -965,10 +1083,12 @@ target_include_directories(freertos_kernel_port_headers INTERFACE
|
|||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/non_secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55/secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM55_TFM>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM55_NTZ/non_secure>
|
||||
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/non_secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_SECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85/secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_NTZ_NONSECURE>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85_NTZ/non_secure>
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CM85_TFM>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CM85_NTZ/non_secure>
|
||||
|
||||
# ARMv7-R Ports for IAR EWARM
|
||||
$<$<STREQUAL:${FREERTOS_PORT},IAR_ARM_CRX_NOGIC>:${CMAKE_CURRENT_LIST_DIR}/IAR/ARM_CRx_No_GIC>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -134,8 +136,9 @@
|
|||
" ldr r4, =xSecureContext \n"
|
||||
" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
|
||||
" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -130,8 +132,9 @@
|
|||
" \n"
|
||||
" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
" msr psplim, r1 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -134,8 +136,9 @@
|
|||
" ldr r4, =xSecureContext \n"
|
||||
" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
|
||||
" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -130,8 +132,9 @@
|
|||
" \n"
|
||||
" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
" msr psplim, r1 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -134,8 +136,9 @@
|
|||
" ldr r4, =xSecureContext \n"
|
||||
" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
|
||||
" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -130,8 +132,9 @@
|
|||
" \n"
|
||||
" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
" msr psplim, r1 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -134,8 +136,9 @@
|
|||
" ldr r4, =xSecureContext \n"
|
||||
" str r1, [r4] \n" /* Set xSecureContext to this task's value for the same. */
|
||||
" msr psplim, r2 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -130,8 +132,9 @@
|
|||
" \n"
|
||||
" ldm r0!, {r1-r2} \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
" msr psplim, r1 \n" /* Set this task's PSPLIM value. */
|
||||
" movs r1, #2 \n" /* r1 = 2. */
|
||||
" msr CONTROL, r1 \n" /* Switch to use PSP in the thread mode. */
|
||||
" mrs r1, control \n" /* Obtain current control register value. */
|
||||
" orrs r1, r1, #2 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
|
||||
" msr control, r1 \n" /* Write back the new control register value. */
|
||||
" adds r0, #32 \n" /* Discard everything up to r0. */
|
||||
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
|
||||
" isb \n"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __attribute__( ( used ) )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M23"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 0
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
|
|||
ldr r4, =xSecureContext
|
||||
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
|
||||
msr psplim, r2 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
|
|||
|
||||
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
msr psplim, r1 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M33"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
|
|||
ldr r4, =xSecureContext
|
||||
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
|
||||
msr psplim, r2 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
|
|||
|
||||
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
msr psplim, r1 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -51,6 +53,7 @@
|
|||
#define portARCH_NAME "Cortex-M35P"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 0
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
|
|||
ldr r4, =xSecureContext
|
||||
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
|
||||
msr psplim, r2 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
|
|||
|
||||
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
msr psplim, r1 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M55"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 0
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -179,8 +181,9 @@ vRestoreContextOfFirstTask:
|
|||
ldr r4, =xSecureContext
|
||||
str r1, [r4] /* Set xSecureContext to this task's value for the same. */
|
||||
msr psplim, r2 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -110,6 +112,7 @@ typedef void ( * portISR_t )( void );
|
|||
#define portSCB_VTOR_REG ( *( ( portISR_t ** ) 0xe000ed08 ) )
|
||||
#define portSCB_SYS_HANDLER_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
|
||||
#define portSCB_MEM_FAULT_ENABLE_BIT ( 1UL << 16UL )
|
||||
#define portSCB_USG_FAULT_ENABLE_BIT ( 1UL << 18UL )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -373,6 +376,20 @@ typedef void ( * portISR_t )( void );
|
|||
* any secure calls.
|
||||
*/
|
||||
#define portNO_SECURE_CONTEXT 0
|
||||
|
||||
/**
|
||||
* @brief Constants required to check and configure PACBTI security feature implementation.
|
||||
*/
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
#define portID_ISAR5_REG ( *( ( volatile uint32_t * ) 0xe000ed74 ) )
|
||||
|
||||
#define portCONTROL_UPAC_EN ( 1UL << 7UL )
|
||||
#define portCONTROL_PAC_EN ( 1UL << 6UL )
|
||||
#define portCONTROL_UBTI_EN ( 1UL << 5UL )
|
||||
#define portCONTROL_BTI_EN ( 1UL << 4UL )
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
|
|
@ -410,6 +427,26 @@ static void prvTaskExitError( void );
|
|||
static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
|
||||
#endif /* configENABLE_FPU */
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
/**
|
||||
* @brief Configures PACBTI features.
|
||||
*
|
||||
* This function configures the Pointer Authentication, and Branch Target
|
||||
* Identification security features as per the user configuration. It returns
|
||||
* the value of the special purpose CONTROL register accordingly, and optionally
|
||||
* updates the CONTROL register value. Currently, only Cortex-M85 (ARMv8.1-M
|
||||
* architecture based) target supports PACBTI security feature.
|
||||
*
|
||||
* @param xWriteControlRegister Used to control whether the special purpose
|
||||
* CONTROL register should be updated or not.
|
||||
*
|
||||
* @return CONTROL register value according to the configured PACBTI option.
|
||||
*/
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister );
|
||||
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
/**
|
||||
* @brief Setup the timer to generate the tick interrupts.
|
||||
*
|
||||
|
|
@ -1457,6 +1494,7 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPU_SETTINGS * xMPUSettings ) /* PRIVILEGED_FUNCTION */
|
||||
{
|
||||
uint32_t ulIndex = 0;
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
xMPUSettings->ulContext[ ulIndex ] = 0x04040404; /* r4. */
|
||||
ulIndex++;
|
||||
|
|
@ -1503,16 +1541,24 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
|
|||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) pxEndOfStack; /* PSPLIM. */
|
||||
ulIndex++;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Check PACBTI security feature configuration before pushing the
|
||||
* CONTROL register's value on task's TCB. */
|
||||
ulControl = prvConfigurePACBTI( pdFALSE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
if( xRunPrivileged == pdTRUE )
|
||||
{
|
||||
xMPUSettings->ulTaskFlags |= portTASK_IS_PRIVILEGED_FLAG;
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_PRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
else
|
||||
{
|
||||
xMPUSettings->ulTaskFlags &= ( ~portTASK_IS_PRIVILEGED_FLAG );
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED; /* CONTROL. */
|
||||
xMPUSettings->ulContext[ ulIndex ] = ( ulControl | ( uint32_t ) portINITIAL_CONTROL_UNPRIVILEGED ); /* CONTROL. */
|
||||
ulIndex++;
|
||||
}
|
||||
|
||||
|
|
@ -1740,6 +1786,14 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
|
|||
portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
|
||||
portNVIC_SHPR2_REG = 0;
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
{
|
||||
/* Set the CONTROL register value based on PACBTI security feature
|
||||
* configuration before starting the first task. */
|
||||
( void) prvConfigurePACBTI( pdTRUE );
|
||||
}
|
||||
#endif /* portHAS_PACBTI_FEATURE */
|
||||
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
{
|
||||
/* Setup the Memory Protection Unit (MPU). */
|
||||
|
|
@ -2158,3 +2212,42 @@ BaseType_t xPortIsInsideInterrupt( void )
|
|||
|
||||
#endif /* #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( portHAS_PACBTI_FEATURE == 1 )
|
||||
|
||||
static uint32_t prvConfigurePACBTI( BaseType_t xWriteControlRegister )
|
||||
{
|
||||
uint32_t ulControl = 0x0;
|
||||
|
||||
/* Ensure that PACBTI is implemented. */
|
||||
configASSERT( portID_ISAR5_REG != 0x0 );
|
||||
|
||||
/* Enable UsageFault exception if PAC or BTI is enabled. */
|
||||
#if( ( configENABLE_PAC == 1 ) || ( configENABLE_BTI == 1 ) )
|
||||
{
|
||||
portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_USG_FAULT_ENABLE_BIT;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_PAC == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UPAC_EN | portCONTROL_PAC_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
#if( configENABLE_BTI == 1 )
|
||||
{
|
||||
ulControl |= ( portCONTROL_UBTI_EN | portCONTROL_BTI_EN );
|
||||
}
|
||||
#endif
|
||||
|
||||
if( xWriteControlRegister == pdTRUE )
|
||||
{
|
||||
__asm volatile ( "msr control, %0" : : "r" ( ulControl ) );
|
||||
}
|
||||
|
||||
return ulControl;
|
||||
}
|
||||
|
||||
#endif /* #if ( portHAS_PACBTI_FEATURE == 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -165,8 +167,9 @@ vRestoreContextOfFirstTask:
|
|||
|
||||
ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
|
||||
msr psplim, r1 /* Set this task's PSPLIM value. */
|
||||
movs r1, #2 /* r1 = 2. */
|
||||
msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
|
||||
mrs r1, control /* Obtain current control register value. */
|
||||
orrs r1, r1, #2 /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
|
||||
msr control, r1 /* Write back the new control register value. */
|
||||
adds r0, #32 /* Discard everything up to r0. */
|
||||
msr psp, r0 /* This is now the new top of stack to use in the task. */
|
||||
isb
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
|
||||
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
* Copyright 2024 Arm Limited and/or its affiliates
|
||||
* <open-source-office@arm.com>
|
||||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
|
|
@ -56,6 +58,7 @@
|
|||
#define portARCH_NAME "Cortex-M85"
|
||||
#define portHAS_ARMV8M_MAIN_EXTENSION 1
|
||||
#define portARMV8M_MINOR_VERSION 1
|
||||
#define portHAS_PACBTI_FEATURE 1
|
||||
#define portDONT_DISCARD __root
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue