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Correct alignment issue in GCC and RVDS Cortex-A9 port that was preventing full floating point usage in interrupts (other ports will be updated likewise).

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Update the Zynq demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
This commit is contained in:
Richard Barry 2017-01-18 18:33:48 +00:00
parent d67dcf9c74
commit 6ffaa6f018
22 changed files with 78 additions and 309 deletions
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9
FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S
View file

@ -217,16 +217,17 @@ FreeRTOS_IRQ_Handler:
LDR r0, [r2]
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
future use. */
future use. _RB_ Does this ever actually need to be done provided the start
of the stack is 8-byte aligned? */
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
/* Call the interrupt handler. */
PUSH {r0-r3, lr}
/* Call the interrupt handler. r4 pushed to maintain alignment. */
PUSH {r0-r4, lr}
LDR r1, vApplicationIRQHandlerConst
BLX r1
POP {r0-r3, lr}
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i

9
FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s
View file

@ -124,16 +124,17 @@ FreeRTOS_IRQ_Handler
LDR r0, [r2]
; Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
; future use.
; future use. _RB_ Does this ever actually need to be done provided the
; start of the stack is 8-byte aligned?
MOV r2, sp
AND r2, r2, #4
SUB sp, sp, r2
; Call the interrupt handler
PUSH {r0-r3, lr}
; Call the interrupt handler. r4 is pushed to maintain alignment.
PUSH {r0-r4, lr}
LDR r1, =vApplicationIRQHandler
BLX r1
POP {r0-r3, lr}
POP {r0-r4, lr}
ADD sp, sp, r2
CPSID i