mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-20 05:21:59 -04:00
Add barrier instructions to GCC CM3/4 code.
This commit is contained in:
parent
a7fb62cb9c
commit
6d20e2b5cd
|
@ -56,19 +56,19 @@
|
||||||
***************************************************************************
|
***************************************************************************
|
||||||
|
|
||||||
|
|
||||||
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
|
http://www.FreeRTOS.org - Documentation, books, training, latest versions,
|
||||||
license and Real Time Engineers Ltd. contact details.
|
license and Real Time Engineers Ltd. contact details.
|
||||||
|
|
||||||
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
|
||||||
including FreeRTOS+Trace - an indispensable productivity tool, and our new
|
including FreeRTOS+Trace - an indispensable productivity tool, and our new
|
||||||
fully thread aware and reentrant UDP/IP stack.
|
fully thread aware and reentrant UDP/IP stack.
|
||||||
|
|
||||||
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
|
http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
|
||||||
Integrity Systems, who sell the code with commercial support,
|
Integrity Systems, who sell the code with commercial support,
|
||||||
indemnification and middleware, under the OpenRTOS brand.
|
indemnification and middleware, under the OpenRTOS brand.
|
||||||
|
|
||||||
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
|
||||||
engineered and independently SIL3 certified version for use in safety and
|
engineered and independently SIL3 certified version for use in safety and
|
||||||
mission critical applications that require provable dependability.
|
mission critical applications that require provable dependability.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
@ -259,6 +259,11 @@ void vPortYieldFromISR( void )
|
||||||
{
|
{
|
||||||
/* Set a PendSV to request a context switch. */
|
/* Set a PendSV to request a context switch. */
|
||||||
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
||||||
|
|
||||||
|
/* Barriers are normally not required but do ensure the code is completely
|
||||||
|
within the specified behaviour for the architecture. */
|
||||||
|
__asm volatile( "dsb" );
|
||||||
|
__asm volatile( "isb" );
|
||||||
}
|
}
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
@ -266,6 +271,8 @@ void vPortEnterCritical( void )
|
||||||
{
|
{
|
||||||
portDISABLE_INTERRUPTS();
|
portDISABLE_INTERRUPTS();
|
||||||
uxCriticalNesting++;
|
uxCriticalNesting++;
|
||||||
|
__asm volatile( "dsb" );
|
||||||
|
__asm volatile( "isb" );
|
||||||
}
|
}
|
||||||
/*-----------------------------------------------------------*/
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
@ -438,6 +445,8 @@ void xPortSysTickHandler( void )
|
||||||
if( xModifiableIdleTime > 0 )
|
if( xModifiableIdleTime > 0 )
|
||||||
{
|
{
|
||||||
__asm volatile( "wfi" );
|
__asm volatile( "wfi" );
|
||||||
|
__asm volatile( "dsb" );
|
||||||
|
__asm volatile( "isb" );
|
||||||
}
|
}
|
||||||
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
|
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue