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Arm-Cortex-R82: Add MPU support (#1347)
* arm-cortex-r82: Add MPU support This commit introduces support for the Memory Protection Unit (MPU) to the ARM Cortex-R82 port. The MPU enhances system security by allowing the definition of memory regions with specific access permissions. The following changes have been made: - Added MPU configuration functions in `port.c` to set up memory regions and their attributes. - Updated `portASM.S` to include assembly routines for MPU and context switching with MPU support. - Created `mpu_wrappers_v2_asm.c` to provide assembly wrappers for MPU operations. - Updated `portmacro.h` to include MPU-related macros and definitions. - Modified `task.h` to include MPU-related task attributes. - Updated `CMakeLists.txt` to include the new MPU source file. - Enhanced the `README.md` with instructions on MPU configuration. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> * cortex-r82: Minor code improvements This commit includes minor code improvements to enhance readability and maintainability of the Cortex-R82 port files. Changes include refactoring variable names, optimizing comments, and improving code structure without altering functionality. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> * tasks: Disable stack-depth check if MPU wrappers is set This stack-depth check should not be performed for ports where portUSING_MPU_WRAPPERS is set to 1. In this case, pxTopOfStack and pxNewTCB->pxTopOfStack reside in different memory regions: pxTopOfStack is in unprivileged SRAM, while pxNewTCB->pxTopOfStack is in privileged SRAM. This is because pxPortInitialiseStack() returns the address of `ullContext` array rather than the decremented pxTopOfStack, as is done in the non-MPU case. Consequently, this check is not valid in this scenario. Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com> --------- Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
This commit is contained in:
Ahmed Ismail
GitHub
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commit
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10 changed files with 3130 additions and 504 deletions
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@ -1,7 +1,7 @@
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2025 Arm Limited and/or its affiliates
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* Copyright 2025-2026 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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@ -109,14 +109,21 @@
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/**
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* @brief SVC numbers.
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*/
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#define portSVC_YIELD 105
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#define portSVC_START_FIRST_TASK 106
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#define portSVC_DISABLE_INTERRUPTS 107
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#define portSVC_ENABLE_INTERRUPTS 108
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#define portSVC_GET_CORE_ID 109
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#define portSVC_MASK_ALL_INTERRUPTS 110
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#define portSVC_UNMASK_ALL_INTERRUPTS 111
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#define portSVC_UNMASK_INTERRUPTS 112
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#define portSVC_SYSTEM_CALL_EXIT 104
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#define portSVC_YIELD 105
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#define portSVC_START_FIRST_TASK 106
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#define portSVC_DISABLE_INTERRUPTS 107
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#define portSVC_ENABLE_INTERRUPTS 108
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#define portSVC_GET_CORE_ID 109
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#define portSVC_MASK_ALL_INTERRUPTS 110
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#define portSVC_UNMASK_ALL_INTERRUPTS 111
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#define portSVC_UNMASK_INTERRUPTS 112
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#define portSVC_CHECK_PRIVILEGE 113
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#define portSVC_SAVE_TASK_CONTEXT 114
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#define portSVC_RESTORE_CONTEXT 115
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#define portSVC_DELETE_CURRENT_TASK 116
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#define portSVC_INTERRUPT_CORE 117
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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#define portYIELD() __asm volatile ( "SVC %0" : : "i" ( portSVC_YIELD ) : "memory" )
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@ -132,22 +139,21 @@
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extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
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extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
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extern void vPortClearInterruptMaskFromISR( UBaseType_t uxNewMaskValue );
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extern void vInterruptCore( uint32_t ulInterruptID, uint32_t ulCoreID );
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extern void vInterruptCore( uint32_t ulInterruptID, uint8_t ucCoreID );
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#endif /* if !defined(__ASSEMBLER__) */
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/* Use SVC so this is safe from EL0. EL1 sites in the port use direct MSR. */\
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/* Use SVC so this is safe from EL0. EL1 sites in the port use direct MSR. */
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#define portDISABLE_INTERRUPTS() __asm volatile ( "SVC %0" : : "i" ( portSVC_DISABLE_INTERRUPTS ) : "memory" )
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#define portENABLE_INTERRUPTS() __asm volatile ( "SVC %0" : : "i" ( portSVC_ENABLE_INTERRUPTS ) : "memory" )
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/* In all GICs 255 can be written to the priority mask register to unmask all
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* (but the lowest) interrupt priority. */
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#define portUNMASK_VALUE ( 0xFFUL )
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#if !defined(__ASSEMBLER__)
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/* These macros do not globally disable/enable interrupts. They do mask off
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* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
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* interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
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#if ( configNUMBER_OF_CORES == 1 )
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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@ -173,7 +179,7 @@
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#if !defined(__ASSEMBLER__)
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/* Prototype of the FreeRTOS tick handler. This must be installed as the
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* handler for whichever peripheral is used to generate the RTOS tick. */
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* handler for whichever peripheral is used to generate the RTOS tick. */
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void FreeRTOS_Tick_Handler( void );
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#endif /* if !defined(__ASSEMBLER__) */
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@ -193,7 +199,8 @@
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* nothing to prevent it from being called accidentally. */
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#define vPortTaskUsesFPU()
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#endif
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#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
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#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
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#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
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#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
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@ -205,12 +212,10 @@
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Store/clear the ready priorities in a bit map. */
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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@ -220,7 +225,7 @@
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#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
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#endif /* configASSERT */
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#define portNOP() __asm volatile ( "NOP" )
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#define portNOP() __asm volatile ( "NOP" )
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#define portINLINE __inline
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/* The number of bits to shift for an interrupt priority is dependent on the
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@ -246,6 +251,7 @@
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#define portINTERRUPT_PRIORITY_REGISTER_OFFSET ( 0x400U )
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#define portYIELD_CORE_INT_ID ( 0x0U )
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#define portMAX_API_PRIORITY_MASK ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
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#if ( configNUMBER_OF_CORES > 1 )
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@ -258,36 +264,274 @@
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} ePortRTOSLock;
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extern volatile uint64_t ullCriticalNestings[ configNUMBER_OF_CORES ];
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extern void vPortRecursiveLock( BaseType_t xCoreID,
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extern void vPortRecursiveLock( uint8_t ucCoreID,
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ePortRTOSLock eLockNum,
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BaseType_t uxAcquire );
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extern BaseType_t xPortGetCoreID( void );
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extern uint8_t ucPortGetCoreID( void );
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extern uint8_t ucPortGetCoreIDFromIsr( void );
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#endif /* if !defined(__ASSEMBLER__) */
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#define portSET_INTERRUPT_MASK() uxPortSetInterruptMask()
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#define portCLEAR_INTERRUPT_MASK( x ) vPortClearInterruptMask( x )
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#define portMAX_CORE_COUNT configNUMBER_OF_CORES
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#define portGET_CORE_ID() xPortGetCoreID()
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#define portMAX_CORE_COUNT configNUMBER_OF_CORES
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#define portGET_CORE_ID() ucPortGetCoreID()
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#define portGET_CORE_ID_FROM_ISR() ucPortGetCoreIDFromIsr()
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/* Use SGI 0 as the yield core interrupt. */
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#define portYIELD_CORE( xCoreID ) vInterruptCore( portYIELD_CORE_INT_ID, ( uint32_t ) xCoreID )
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/* Use SGI 0 as the yield core interrupt. */
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#define portYIELD_CORE( xCoreID ) vInterruptCore( portYIELD_CORE_INT_ID, ( uint8_t ) xCoreID )
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#define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eIsrLock, pdFALSE )
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#define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eIsrLock, pdTRUE )
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#define portRELEASE_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdFALSE )
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#define portGET_ISR_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eIsrLock, pdTRUE )
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#define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eTaskLock, pdFALSE )
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#define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( xCoreID ), eTaskLock, pdTRUE )
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#define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( xCoreID ) ] )
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#define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ullCriticalNestings[ ( xCoreID ) ] = ( x ) )
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#define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( xCoreID ) ]++ )
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#define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( xCoreID ) ]-- )
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#define portRELEASE_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdFALSE )
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#define portGET_TASK_LOCK( xCoreID ) vPortRecursiveLock( ( uint8_t ) xCoreID, eTaskLock, pdTRUE )
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#define portGET_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ] )
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#define portSET_CRITICAL_NESTING_COUNT( xCoreID, x ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ] = ( x ) )
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#define portINCREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ]++ )
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#define portDECREMENT_CRITICAL_NESTING_COUNT( xCoreID ) ( ullCriticalNestings[ ( uint8_t ) xCoreID ]-- )
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#endif /* configNUMBER_OF_CORES > 1 */
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#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
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/**
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* @brief MPU specific constants.
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*/
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#if ( configENABLE_MPU == 1 )
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#if !defined(__ASSEMBLER__)
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extern BaseType_t xPortIsTaskPrivileged( void );
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#endif /* if !defined(__ASSEMBLER__) */
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/* Device memory attributes used in MAIR_EL1 registers.
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*
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* 8-bit values encoded as follows:
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* Bit[7:4] - 0000 - Device Memory
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* Bit[3:2] - 00 --> Device-nGnRnE
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* 01 --> Device-nGnRE
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* 10 --> Device-nGRE
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* 11 --> Device-GRE
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* Bit[1:0] - 00.
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*/
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#define portMPU_DEVICE_MEMORY_nGnRnE ( 0x00 )
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#define portMPU_DEVICE_MEMORY_nGnRE ( 0x04 )
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#define portMPU_DEVICE_MEMORY_nGRE ( 0x08 )
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#define portMPU_DEVICE_MEMORY_GRE ( 0x0C )
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/* MPU settings that can be overridden in FreeRTOSConfig.h. */
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#ifndef configTOTAL_MPU_REGIONS
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#define configTOTAL_MPU_REGIONS ( 16UL )
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#endif
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#define portPRIVILEGED_FLASH_REGION ( 0ULL ) /* Privileged flash region number. */
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#define portUNPRIVILEGED_FLASH_REGION ( 1ULL ) /* Unprivileged flash region number. */
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#define portUNPRIVILEGED_SYSCALLS_REGION ( 2ULL ) /* Unprivileged syscalls region number. */
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#define portPRIVILEGED_RAM_REGION ( 3ULL ) /* Privileged RAM region number. */
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#define portSTACK_REGION ( 4ULL ) /* Stack region number. */
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#define portSTACK_REGION_INDEX ( 0ULL ) /* Stack region index in the xRegionSettings array. */
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#define portFIRST_CONFIGURABLE_REGION ( 5ULL ) /* First user configurable region number. */
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#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 1UL )
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#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
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#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
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#if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
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#define portACL_ENTRY_SIZE_BITS ( 32UL )
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#endif /* configENABLE_ACCESS_CONTROL_LIST == 1 */
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#if !defined(__ASSEMBLER__)
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/**
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* @brief Settings to define an MPU region.
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*/
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typedef struct MPURegionSettings
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{
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uint64_t ullPrbarEl1; /**< PRBAR_EL1 for the region. */
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uint64_t ullPrlarEl1; /**< PRLAR_EL1 for the region. */
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} MPURegionSettings_t;
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#ifndef configSYSTEM_CALL_STACK_SIZE
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#define configSYSTEM_CALL_STACK_SIZE 128 /* must be defined to the desired size of the system call stack in words for using MPU wrappers v2. */
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#endif
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/**
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* @brief System call info.
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*/
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typedef struct SYSTEM_CALL_INFO
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{
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/* Used to save both the user-mode stack pointer (SP_EL0) and link register (X30)
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* at system call entry so they can be restored or referenced safely even if the task
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* switches out while executing the system call.
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*/
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uint64_t ullLinkRegisterAtSystemCallEntry;
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uint64_t ullUserSPAtSystemCallEntry;
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} xSYSTEM_CALL_INFO;
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#endif /* if !defined(__ASSEMBLER__) */
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/**
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* @brief Task context as stored in the TCB.
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*/
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#if ( configENABLE_FPU == 1 )
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/*
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* +-----------+------------+--------------------------------+-------------+------------------+
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* | Q0-Q31 | FPSR, FPCR | CRITICAL_NESTING, FPU_CONTEXT | X0-X30, XZR | INIT_PSTATE, PC |
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* +-----------+------------+--------------------------------+-------------+------------------+
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*
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* <-----------><-----------><-------------------------------><------------><----------------->
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* 64 2 2 32 2
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*/
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#define MAX_CONTEXT_SIZE 102
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#else /* #if ( configENABLE_FPU == 1 ) */
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/*
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* +--------------------------------+-------------+------------------+
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* | CRITICAL_NESTING, FPU_CONTEXT | X0-X30, XZR | INIT_PSTATE, PC |
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* +--------------------------------+-------------+------------------+
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* <-------------------------------><------------><------------------>
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* 2 32 2
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*/
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#define MAX_CONTEXT_SIZE 36
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#endif /* #if ( configENABLE_FPU == 1 ) */
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#if !defined(__ASSEMBLER__)
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typedef struct MPU_SETTINGS
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{
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uint64_t ullTaskUnprivilegedSP; /* Task's unprivileged user stack pointer. */
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uint64_t ullMairEl1; /* MAIR_EL1 for the task containing attributes. */
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MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /* Settings for tasks' regions. */
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uint64_t ullContext[ MAX_CONTEXT_SIZE + configSYSTEM_CALL_STACK_SIZE ]; /* Task's saved context. */
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uint64_t ullTaskFlags;
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xSYSTEM_CALL_INFO xSystemCallInfo;
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#if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
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uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
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#endif /* configENABLE_ACCESS_CONTROL_LIST */
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} xMPU_SETTINGS;
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#endif /* if !defined(__ASSEMBLER__) */
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#define portUSING_MPU_WRAPPERS ( 1 )
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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/* Normal memory attributes used in MAIR_EL1 registers. */
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#define portMPU_NORMAL_MEMORY_NON_CACHEABLE ( 0x44 ) /* Non-cacheable. */
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#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
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#define portMPU_MAIR_EL1_ATTR0_POS ( 0UL )
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#define portMPU_MAIR_EL1_ATTR0_MASK ( 0x00000000000000ffULL )
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#define portMPU_MAIR_EL1_ATTR1_POS ( 8UL )
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#define portMPU_MAIR_EL1_ATTR1_MASK ( 0x000000000000ff00ULL )
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#define portMPU_MAIR_EL1_ATTR2_POS ( 16UL )
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#define portMPU_MAIR_EL1_ATTR2_MASK ( 0x0000000000ff0000ULL )
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#define portMPU_MAIR_EL1_ATTR3_POS ( 24UL )
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#define portMPU_MAIR_EL1_ATTR3_MASK ( 0x00000000ff000000ULL )
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#define portMPU_MAIR_EL1_ATTR4_POS ( 32UL )
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#define portMPU_MAIR_EL1_ATTR4_MASK ( 0x000000ff00000000ULL )
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#define portMPU_MAIR_EL1_ATTR5_POS ( 40UL )
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#define portMPU_MAIR_EL1_ATTR5_MASK ( 0x0000ff0000000000ULL )
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#define portMPU_MAIR_EL1_ATTR6_POS ( 48UL )
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#define portMPU_MAIR_EL1_ATTR6_MASK ( 0x00ff000000000000ULL )
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#define portMPU_MAIR_EL1_ATTR7_POS ( 56UL )
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#define portMPU_MAIR_EL1_ATTR7_MASK ( 0xff00000000000000ULL )
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#define portMPU_PRBAR_EL1_ADDRESS_MASK ( 0x0000FFFFFFFFFFC0ULL )
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#define portMPU_PRLAR_EL1_ADDRESS_MASK ( 0x0000FFFFFFFFFFC0ULL )
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#define portMPU_PRBAR_EL1_ACCESS_PERMISSIONS_MASK ( 3ULL<< 2ULL )
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#define portMPU_REGION_NON_SHAREABLE ( 0ULL << 4ULL )
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#define portMPU_REGION_OUTER_SHAREABLE ( 2ULL << 4ULL )
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#define portMPU_REGION_INNER_SHAREABLE ( 3ULL << 4ULL )
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#define portMPU_REGION_PRIVILEGED_READ_WRITE ( 0ULL << 2ULL )
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#define portMPU_REGION_READ_WRITE ( 1ULL << 2ULL )
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#define portMPU_REGION_PRIVILEGED_READ_ONLY ( 2ULL << 2ULL )
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#define portMPU_REGION_READ_ONLY ( 3ULL << 2ULL )
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#define portMPU_REGION_EXECUTE_NEVER ( 1ULL << 1ULL )
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#define portMPU_PRLAR_EL1_ATTR_INDEX0 ( 0ULL << 1ULL )
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#define portMPU_PRLAR_EL1_ATTR_INDEX1 ( 1ULL << 1ULL )
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#define portMPU_PRLAR_EL1_ATTR_INDEX2 ( 2ULL << 1ULL )
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#define portMPU_PRLAR_EL1_ATTR_INDEX3 ( 3ULL << 1ULL )
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#define portMPU_PRLAR_EL1_ATTR_INDEX4 ( 4ULL << 1ULL )
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#define portMPU_PRLAR_EL1_ATTR_INDEX5 ( 5ULL << 1ULL )
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#define portMPU_PRLAR_EL1_ATTR_INDEX6 ( 6ULL << 1ULL )
|
||||
#define portMPU_PRLAR_EL1_ATTR_INDEX7 ( 7ULL << 1ULL )
|
||||
|
||||
#define portMPU_PRLAR_EL1_REGION_ENABLE ( 1ULL )
|
||||
|
||||
#define portMPU_ENABLE_BIT ( 1ULL << 0ULL )
|
||||
#define portMPU_PRIV_BACKGROUND_ENABLE_BIT ( 1ULL << 17ULL )
|
||||
|
||||
/* Max value that fits in a uint64_t type. */
|
||||
#define portUINT64_MAX ( ~( ( uint64_t ) 0 ) )
|
||||
#define portADD_UINT64_WILL_OVERFLOW( a, b ) ( ( a ) > ( portUINT64_MAX - ( b ) ) )
|
||||
|
||||
/* Extract first address of the MPU region as encoded in the
|
||||
* PRBAR_EL1 register value. */
|
||||
#define portEXTRACT_FIRST_ADDRESS_FROM_PRBAR_EL1( prbar_el1 ) \
|
||||
( ( prbar_el1 ) & portMPU_PRBAR_EL1_ADDRESS_MASK )
|
||||
|
||||
/* Extract last address of the MPU region as encoded in the
|
||||
* PRLAR_EL1 register value. */
|
||||
#define portEXTRACT_LAST_ADDRESS_FROM_PRLAR_EL1( prlar_el1 ) \
|
||||
( ( ( prlar_el1 ) & portMPU_PRLAR_EL1_ADDRESS_MASK ) | ~portMPU_PRLAR_EL1_ADDRESS_MASK )
|
||||
|
||||
/* Does addr lies within [start, end] address range? */
|
||||
#define portIS_ADDRESS_WITHIN_RANGE( addr, start, end ) \
|
||||
( ( ( addr ) >= ( start ) ) && ( ( addr ) <= ( end ) ) )
|
||||
|
||||
/* Is the access request satisfied by the available permissions? */
|
||||
#define portIS_AUTHORIZED( accessRequest, permissions ) \
|
||||
( ( ( permissions ) & ( accessRequest ) ) == accessRequest )
|
||||
|
||||
/**
|
||||
* @brief Offsets in the task's stack (context).
|
||||
*/
|
||||
#if ( configUSE_TASK_FPU_SUPPORT == portTASK_HAVE_FPU_CONTEXT_BY_DEFAULT )
|
||||
#define portOFFSET_TO_PC ( 68 )
|
||||
#define portOFFSET_TO_LR ( 70 )
|
||||
#define portOFFSET_TO_X0 ( 100 )
|
||||
#define portOFFSET_TO_X1 ( 101 )
|
||||
#define portOFFSET_TO_X2 ( 98 )
|
||||
#define portOFFSET_TO_X3 ( 99 )
|
||||
#else
|
||||
#define portOFFSET_TO_PC ( 2 )
|
||||
#define portOFFSET_TO_LR ( 4 )
|
||||
#define portOFFSET_TO_X0 ( 34 )
|
||||
#define portOFFSET_TO_X1 ( 35 )
|
||||
#define portOFFSET_TO_X2 ( 32 )
|
||||
#define portOFFSET_TO_X3 ( 33 )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Flag used to mark that a Task is privileged.
|
||||
*
|
||||
* @ingroup Port Privilege
|
||||
*/
|
||||
#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
|
||||
|
||||
/**
|
||||
* @brief Checks whether or not the calling task is privileged.
|
||||
*
|
||||
* @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
|
||||
*/
|
||||
#define portIS_TASK_PRIVILEGED() xPortIsTaskPrivileged()
|
||||
|
||||
#else
|
||||
|
||||
#define portPRIVILEGE_BIT ( 0x0UL )
|
||||
|
||||
#endif /* #if ( configENABLE_MPU == 1 ) */
|
||||
|
||||
#define portPSTATE_I_BIT ( 0x7 )
|
||||
|
||||
/* *INDENT-OFF* */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue