Arm-Cortex-R82: Add MPU support (#1347)

* arm-cortex-r82: Add MPU support

This commit introduces support for the Memory Protection Unit (MPU)
to the ARM Cortex-R82 port. The MPU enhances system security
by allowing the definition of memory regions with specific access
permissions. The following changes have been made:
- Added MPU configuration functions in `port.c` to set up memory
  regions and their attributes.
- Updated `portASM.S` to include assembly routines for MPU
  and context switching with MPU support.
- Created `mpu_wrappers_v2_asm.c` to provide assembly wrappers for
  MPU operations.
- Updated `portmacro.h` to include MPU-related macros and definitions.
- Modified `task.h` to include MPU-related task attributes.
- Updated `CMakeLists.txt` to include the new MPU source file.
- Enhanced the `README.md` with instructions on MPU configuration.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

* cortex-r82: Minor code improvements

This commit includes minor code improvements to enhance readability
and maintainability of the Cortex-R82 port files. Changes include
refactoring variable names, optimizing comments, and improving code
structure without altering functionality.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

* tasks: Disable stack-depth check if MPU wrappers is set

This stack-depth check should not be performed for ports
where portUSING_MPU_WRAPPERS is set to 1.
In this case, pxTopOfStack and pxNewTCB->pxTopOfStack reside
in different memory regions: pxTopOfStack is in unprivileged SRAM,
while pxNewTCB->pxTopOfStack is in privileged SRAM.
This is because pxPortInitialiseStack() returns the address of
`ullContext` array rather than the decremented pxTopOfStack,
as is done in the non-MPU case.
Consequently, this check is not valid in this scenario.

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

---------

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

portable/GCC/ARM_CR82/README.md

@@ -18,6 +18,12 @@ The port is supported and tested on the following toolchains:
 - The port does not perform cache maintenance for shared buffers.
 - If your hardware or model doesn't support full cache coherency, you must handle cache clean/invalidate operations, memory attributes, and any additional barriers in your BSP/application (especially around shared-memory regions).
 
+# MPU Support
+
+- This port supports the FreeRTOS MPU on both single-core and SMP (multi-core) configurations. Enable via `configENABLE_MPU = 1`; the port programs MPU regions per task on each active core.
+
+- Minimum MPU granularity and alignment: 64 bytes. Ensure any user‑defined region base and size are 64‑byte aligned.
+
 # SMP Multicore Bring-up
 
 For SMP systems using this port, the application only needs to start the scheduler on the primary core and issue an SVC from each secondary core once they are online. The kernel coordinates the rest and ensures all cores are properly managed.
@@ -39,4 +45,4 @@ Secondary core flow (to be done in each core’s reset handler):
 2. Wait for the primary core's signal that shared initialization is complete (i.e., `ucPrimaryCoreInitDoneFlag` set to 1).
 3. Update `VBAR_EL1` from the boot vector table to the FreeRTOS vector table.
 4. Initialize the GIC redistributor and enable SGIs so interrupts from the primary core are receivable; signal the primary that this secondary is online and ready by setting the its flag in the `ucSecondaryCoresReadyFlags` array.
-5. Issue an SVC with immediate value `106` to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on this core.
+5. Issue an SVC with immediate value `106` (i.e., `portSVC_START_FIRST_TASK`) to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on this core.