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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Added Keil Blinky build configuration for the MB9B500 FM3.
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Richard Barry
parent
a67536618a
commit
6cb1ea3ae4
3 changed files with 1667 additions and 0 deletions
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;/************************************************************************/
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;/* (C) Fujitsu Semiconductor Europe GmbH */
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;/* */
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;/* The following software deliverable is intended for and must only be */
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;/* used for reference and in an evaluation laboratory environment. */
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;/* It is provided on an as-is basis without charge and is subject to */
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;/* alterations. */
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;/* It is the user’s obligation to fully test the software in its */
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;/* environment and to ensure proper functionality, qualification and */
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;/* compliance with component specifications. */
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;/* */
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;/* In the event the software deliverable includes the use of open */
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;/* source components, the provisions of the governing open source */
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;/* license agreement shall apply with respect to such software */
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;/* deliverable. */
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;/* FSEU does not warrant that the deliverables do not infringe any */
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;/* third party intellectual property right (IPR). In the event that */
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;/* the deliverables infringe a third party IPR it is the sole */
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;/* responsibility of the customer to obtain necessary licenses to */
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;/* continue the usage of the deliverable. */
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;/* */
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;/* To the maximum extent permitted by applicable law FSEU disclaims all */
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;/* warranties, whether express or implied, in particular, but not */
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;/* limited to, warranties of merchantability and fitness for a */
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;/* particular purpose for which the deliverable is not designated. */
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;/* */
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;/* To the maximum extent permitted by applicable law, FSEU's liability */
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;/* is restricted to intention and gross negligence. */
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;/* FSEU is not liable for consequential damages. */
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;/* */
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;/* (V1.4) */
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;/************************************************************************/
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;/* Startup for ARM */
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;/* Version V1.02 */
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;/* Date 2011-01-12 */
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;/* Target-mcu MB9B5xx */
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;/************************************************************************/
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; Stack Configuration
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; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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Stack_Size EQU 0x00000200
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; Heap Configuration
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; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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DCD CSV_Handler ; 0: Clock Super Visor
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DCD SWDT_Handler ; 1: Software Watchdog Timer
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DCD LVD_Handler ; 2: Low Voltage Detector
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DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
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DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
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DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
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DCD DT_Handler ; 6: Dual Timer / Quad Decoder
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DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
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DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
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DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
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DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
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DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
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DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
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DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
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DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
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DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
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DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
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DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
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DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
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DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
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DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
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DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
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DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
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DCD PPG_Handler ; 23: PPG
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DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
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DCD ADC0_IRQHandler ; 25: ADC0
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DCD ADC1_IRQHandler ; 26: ADC1
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DCD ADC2_IRQHandler ; 27: ADC2
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DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
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DCD MFT_IPC_IRQHandler ; 29: Input Capture
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DCD MFT_OPC_IRQHandler ; 30: Output Compare
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DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
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DCD CAN0_IRQHandler ; 32: CAN ch.0
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DCD CAN1_IRQHandler ; 33: CAN ch.1
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DCD USBF_Handler ; 34: USB Function
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DCD USB_Handler ; 35: USB Function / USB HOST
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DCD DummyHandler ; 36: Reserved
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DCD DummyHandler ; 37: Reserved
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DCD DMAC0_Handler ; 38: DMAC ch.0
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DCD DMAC1_Handler ; 39: DMAC ch.1
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DCD DMAC2_Handler ; 40: DMAC ch.2
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DCD DMAC3_Handler ; 41: DMAC ch.3
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DCD DMAC4_Handler ; 42: DMAC ch.4
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DCD DMAC5_Handler ; 43: DMAC ch.5
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DCD DMAC6_Handler ; 44: DMAC ch.6
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DCD DMAC7_Handler ; 45: DMAC ch.7
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DCD DummyHandler ; 46: Reserved
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DCD DummyHandler ; 47: Reserved
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT CSV_Handler [WEAK]
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EXPORT SWDT_Handler [WEAK]
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EXPORT LVD_Handler [WEAK]
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EXPORT MFT_WG_IRQHandler [WEAK]
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EXPORT INT0_7_Handler [WEAK]
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EXPORT INT8_15_Handler [WEAK]
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EXPORT DT_Handler [WEAK]
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EXPORT MFS0RX_IRQHandler [WEAK]
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EXPORT MFS0TX_IRQHandler [WEAK]
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EXPORT MFS1RX_IRQHandler [WEAK]
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EXPORT MFS1TX_IRQHandler [WEAK]
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EXPORT MFS2RX_IRQHandler [WEAK]
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EXPORT MFS2TX_IRQHandler [WEAK]
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EXPORT MFS3RX_IRQHandler [WEAK]
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EXPORT MFS3TX_IRQHandler [WEAK]
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EXPORT MFS4RX_IRQHandler [WEAK]
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EXPORT MFS4TX_IRQHandler [WEAK]
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EXPORT MFS5RX_IRQHandler [WEAK]
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EXPORT MFS5TX_IRQHandler [WEAK]
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EXPORT MFS6RX_IRQHandler [WEAK]
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EXPORT MFS6TX_IRQHandler [WEAK]
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EXPORT MFS7RX_IRQHandler [WEAK]
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EXPORT MFS7TX_IRQHandler [WEAK]
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EXPORT PPG_Handler [WEAK]
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EXPORT TIM_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT ADC1_IRQHandler [WEAK]
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EXPORT ADC2_IRQHandler [WEAK]
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EXPORT MFT_FRT_IRQHandler [WEAK]
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EXPORT MFT_IPC_IRQHandler [WEAK]
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EXPORT MFT_OPC_IRQHandler [WEAK]
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EXPORT BT_IRQHandler [WEAK]
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EXPORT CAN0_IRQHandler [WEAK]
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EXPORT CAN1_IRQHandler [WEAK]
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EXPORT USBF_Handler [WEAK]
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EXPORT USB_Handler [WEAK]
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EXPORT DMAC0_Handler [WEAK]
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EXPORT DMAC1_Handler [WEAK]
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EXPORT DMAC2_Handler [WEAK]
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EXPORT DMAC3_Handler [WEAK]
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EXPORT DMAC4_Handler [WEAK]
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EXPORT DMAC5_Handler [WEAK]
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EXPORT DMAC6_Handler [WEAK]
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EXPORT DMAC7_Handler [WEAK]
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EXPORT DummyHandler [WEAK]
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CSV_Handler
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SWDT_Handler
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LVD_Handler
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MFT_WG_IRQHandler
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INT0_7_Handler
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INT8_15_Handler
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DT_Handler
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MFS0RX_IRQHandler
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MFS0TX_IRQHandler
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MFS1RX_IRQHandler
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MFS1TX_IRQHandler
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MFS2RX_IRQHandler
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MFS2TX_IRQHandler
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MFS3RX_IRQHandler
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MFS3TX_IRQHandler
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MFS4RX_IRQHandler
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MFS4TX_IRQHandler
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MFS5RX_IRQHandler
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MFS5TX_IRQHandler
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MFS6RX_IRQHandler
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MFS6TX_IRQHandler
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MFS7RX_IRQHandler
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MFS7TX_IRQHandler
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PPG_Handler
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TIM_IRQHandler
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ADC0_IRQHandler
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ADC1_IRQHandler
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ADC2_IRQHandler
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MFT_FRT_IRQHandler
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MFT_IPC_IRQHandler
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MFT_OPC_IRQHandler
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BT_IRQHandler
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CAN0_IRQHandler
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CAN1_IRQHandler
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USBF_Handler
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USB_Handler
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DMAC0_Handler
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DMAC1_Handler
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DMAC2_Handler
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DMAC3_Handler
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DMAC4_Handler
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DMAC5_Handler
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DMAC6_Handler
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DMAC7_Handler
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DummyHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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