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Handle interrupt acknowledge register in Cortex-A53 SRE port (#392)

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Let the FreeRTOS IRQ handler properly store and restore the ICCIAR
register value around the vApplicationIRQHandler() call.

Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com>

Co-authored-by: Stephane Viau <stephane.viau@oss.nxp.com>
Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
This commit is contained in:
Stephane Viau 2021-10-15 18:21:56 +02:00 committed by GitHub
parent a030d0a02b
commit 68ddb32b55
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1 changed files with 13 additions and 0 deletions
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13
portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S
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@ -303,6 +303,13 @@ FreeRTOS_IRQ_Handler:
/* Maintain the interrupt nesting information across the function call. */ /* Maintain the interrupt nesting information across the function call. */
STP X1, X5, [SP, #-0x10]! STP X1, X5, [SP, #-0x10]!
/* Read value from the interrupt acknowledge register, which is stored in W0
for future parameter and interrupt clearing use. */
MRS X0, S3_0_C12_C12_0 /* read ICC_IAR1_EL1 and store ICCIAR in X0 as parameter */
/* Maintain the ICCIAR value across the function call. */
STP X0, X1, [SP, #-0x10]!
/* Call the C handler. */ /* Call the C handler. */
BL vApplicationIRQHandler BL vApplicationIRQHandler
@ -311,6 +318,12 @@ FreeRTOS_IRQ_Handler:
DSB SY DSB SY
ISB SY ISB SY
/* Restore the ICCIAR value. */
LDP X0, X1, [SP], #0x10
/* End IRQ processing by writing ICCIAR to the EOI register. */
MSR S3_0_C12_C12_1, X0 /* ICC_EOIR1_EL1 */
/* Restore the critical nesting count. */ /* Restore the critical nesting count. */
LDP X1, X5, [SP], #0x10 LDP X1, X5, [SP], #0x10
STR X1, [X5] STR X1, [X5]