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This commit is contained in:
Richard Barry 2011-08-27 14:20:58 +00:00
parent df4feccb98
commit 678396f61b
12 changed files with 560 additions and 502 deletions
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14
Demo/MicroBlaze_Spartan-6_EthernetFull/PlatformStudioProject/system.mhs
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@ -75,11 +75,11 @@ BEGIN microblaze
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0xc0000000
PARAMETER C_ICACHE_HIGHADDR = 0xc7ffffff
PARAMETER C_USE_ICACHE = 0
PARAMETER C_USE_ICACHE = 1
PARAMETER C_ICACHE_ALWAYS_USED = 1
PARAMETER C_DCACHE_BASEADDR = 0xc0000000
PARAMETER C_DCACHE_HIGHADDR = 0xc7ffffff
PARAMETER C_USE_DCACHE = 0
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_ALWAYS_USED = 1
PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1
PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1
@ -99,10 +99,14 @@ BEGIN microblaze
PARAMETER C_NUMBER_OF_PC_BRK = 7
PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2
PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2
PARAMETER C_CACHE_BYTE_SIZE = 16384
PARAMETER C_DCACHE_BYTE_SIZE = 16384
BUS_INTERFACE M_AXI_DP = axi4lite_0
BUS_INTERFACE DEBUG = microblaze_0_debug
BUS_INTERFACE DLMB = microblaze_0_dlmb
BUS_INTERFACE ILMB = microblaze_0_ilmb
BUS_INTERFACE M_AXI_DC = axi4_0
BUS_INTERFACE M_AXI_IC = axi4_0
PORT MB_RESET = proc_sys_reset_0_MB_Reset
PORT CLK = clk_100_0000MHzPLL0
PORT INTERRUPT = microblaze_0_interrupt
@ -201,7 +205,7 @@ BEGIN mdm
PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
PARAMETER C_BASEADDR = 0x74800000
PARAMETER C_HIGHADDR = 0x748FFFFF
PARAMETER C_HIGHADDR = 0x7480FFFF
BUS_INTERFACE S_AXI = axi4lite_0
BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
PORT S_AXI_ACLK = clk_50_0000MHzPLL0
@ -274,14 +278,14 @@ BEGIN axi_s6_ddrx
PARAMETER C_MCB_RZQ_LOC = K7
PARAMETER C_MCB_ZIO_LOC = R7
PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E
PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG & ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 1
PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 1
PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 1
PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 1
PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 1
PARAMETER C_S0_AXI_BASEADDR = 0x80000000
PARAMETER C_S0_AXI_HIGHADDR = 0x87ffffff
PARAMETER C_S0_AXI_HIGHADDR = 0x807FFFFF
PARAMETER C_S0_AXI_STRICT_COHERENCY = 0
BUS_INTERFACE S0_AXI = axi4_0
PORT mcbx_dram_clk = mcbx_dram_clk