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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Update to use the kernel critical nesting.
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f3eb5028a3
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@ -131,11 +131,6 @@
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mflo s6
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sw s6, 8(s5)
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/* Each task maintains its own nesting count. */
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la s6, uxCriticalNesting
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lw s6, (s6)
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sw s6, 4(s5)
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/* Update the task stack pointer value if nesting is zero. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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@ -199,13 +194,6 @@
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addiu k1, k1, -1
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sw k1, 0(k0)
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/* Restore the critical nesting count. */
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la k0, uxCriticalNesting
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lw k1, 4(s5)
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sw k1, (k0)
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/* If the critical nesting is not zero then set status as if within
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a critical section. */
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lw k0, portSTATUS_STACK_LOCATION(s5)
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lw k1, portEPC_STACK_LOCATION(s5)
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@ -62,24 +62,15 @@
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#define portIE_BIT ( 0x00000001 )
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#define portEXL_BIT ( 0x00000002 )
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#define portSW0_ENABLE ( 0x00000100 )
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#define portIPL_SHIFT ( 10 )
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#define portALL_IPL_BITS ( 0x3f << portIPL_SHIFT )
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/* The EXL bit is set to ensure interrupts do not occur while the context of
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the first task is being restored. */
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#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portSW0_ENABLE )
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/* Records the nesting depth of calls to portENTER_CRITICAL(). */
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unsigned portBASE_TYPE uxCriticalNesting = 0x55555555;
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/* Records the interrupt nesting depth. This starts at one as it will be
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decremented to 0 when the first task starts. */
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volatile unsigned portBASE_TYPE uxInterruptNesting = 0x01;
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/* Used to store the original interrupt mask when the mask level is temporarily
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raised during an ISR. */
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volatile unsigned portBASE_TYPE uxSavedStatusRegister = 0;
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/* Stores the task stack pointer when a switch is made to use the system stack. */
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unsigned portBASE_TYPE uxSavedTaskStackPointer = 0;
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@ -126,7 +117,7 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
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*pxTopOfStack = (portSTACK_TYPE) pvParameters; /* Parameters to pass in */
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pxTopOfStack -= 14;
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*pxTopOfStack = (portSTACK_TYPE) 0x00000000; /* critical nesting level */
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*pxTopOfStack = (portSTACK_TYPE) 0x00000000; /* critical nesting level - no longer used. */
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pxTopOfStack--;
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return pxTopOfStack;
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@ -154,39 +145,6 @@ void vPortEndScheduler(void)
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}
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/*-----------------------------------------------------------*/
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void vPortEnterCritical(void)
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{
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unsigned portLONG ulStatus;
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/* Mask interrupts at and below the kernel interrupt priority. */
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ulStatus = _CP0_GET_STATUS();
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ulStatus |= ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT );
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_CP0_SET_STATUS( ulStatus );
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/* Once interrupts are disabled we can access the nesting count directly. */
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uxCriticalNesting++;
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical(void)
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{
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unsigned portLONG ulStatus;
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/* If we are in a critical section then we can access the nesting count
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directly. */
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uxCriticalNesting--;
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/* Has the nesting unwound? */
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if( uxCriticalNesting == 0 )
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{
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/* Unmask all interrupts. */
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ulStatus = _CP0_GET_STATUS();
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ulStatus &= ~portALL_IPL_BITS;
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_CP0_SET_STATUS( ulStatus );
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}
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xPortStartScheduler( void )
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{
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extern void vPortStartFirstTask( void );
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@ -224,9 +182,11 @@ unsigned portLONG ulStatus;
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void vPortIncrementTick( void )
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{
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vPortSetInterruptMaskFromISR();
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unsigned portBASE_TYPE uxSavedStatus;
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uxSavedStatus = uxPortSetInterruptMaskFromISR();
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vTaskIncrementTick();
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vPortClearInterruptMaskFromISR();
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vPortClearInterruptMaskFromISR( uxSavedStatus );
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/* If we are using the preemptive scheduler then we might want to select
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a different task to execute. */
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@ -239,15 +199,19 @@ void vPortIncrementTick( void )
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}
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/*-----------------------------------------------------------*/
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void vPortSetInterruptMaskFromISR( void )
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unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR( void )
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{
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unsigned portBASE_TYPE uxSavedStatusRegister;
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asm volatile ( "di" );
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uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
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_CP0_SET_STATUS( ( uxSavedStatusRegister | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );
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return uxSavedStatusRegister;
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}
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/*-----------------------------------------------------------*/
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void vPortClearInterruptMaskFromISR( void )
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void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE uxSavedStatusRegister )
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{
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_CP0_SET_STATUS( uxSavedStatusRegister );
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}
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@ -57,7 +57,6 @@
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.set noreorder
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.extern pxCurrentTCB
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.extern uxCriticalNesting
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.extern vTaskSwitchContext
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.extern vPortIncrementTick
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.extern xISRStackTop
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@ -189,11 +188,6 @@ vPortYieldISR:
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mflo s7
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sw s7, 8(s5)
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/* Each task maintains its own nesting count. */
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la s7, uxCriticalNesting
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lw s7, (s7)
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sw s7, 4(s5)
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/* Save the stack pointer to the task. */
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la s7, pxCurrentTCB
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lw s7, (s7)
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@ -276,33 +270,19 @@ vPortYieldISR:
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/* Switch back to use the real stack pointer. */
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add sp, zero, s5
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/* Restore the critical nesting depth. */
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la s5, uxCriticalNesting
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lw k0, 4(sp)
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sw k0, (s5)
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/* Restore the real s5 value. */
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lw s5, 40(sp)
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/* If the critical nesting is not zero and a yield is not pended
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then set status as if within a critical section. */
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lw s5, portSTATUS_STACK_LOCATION(sp)
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beq k0, zero, .+28
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nop
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mfc0 k1, _CP0_CAUSE
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andi k1, k1, 256
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bne k1, zero, .+12
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nop
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or s5, s5, (configMAX_SYSCALL_INTERRUPT_PRIORITY<<10)
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lw k1, portSTATUS_STACK_LOCATION(sp)
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lw k0, portEPC_STACK_LOCATION(sp)
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mtc0 s5, _CP0_STATUS
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ehb
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/* Restore the real s5 value. */
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lw s5, 40(sp)
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/* Remove stack frame. */
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addiu sp, sp, portCONTEXT_SIZE
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mtc0 k1, _CP0_STATUS
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ehb
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mtc0 k0, _CP0_EPC
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eret
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nop
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@ -92,18 +92,40 @@ extern "C" {
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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#define portDISABLE_INTERRUPTS() INTDisableInterrupts()
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#define portENABLE_INTERRUPTS() INTEnableInterrupts()
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#define portIPL_SHIFT ( 10 )
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#define portALL_IPL_BITS ( 0x3f << portIPL_SHIFT )
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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#define portDISABLE_INTERRUPTS() \
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{ \
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unsigned portLONG ulStatus; \
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\
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/* Mask interrupts at and below the kernel interrupt priority. */ \
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ulStatus = _CP0_GET_STATUS(); \
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ulStatus |= ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ); \
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_CP0_SET_STATUS( ulStatus ); \
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}
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extern void vPortSetInterruptMaskFromISR();
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extern void vPortClearInterruptMaskFromISR();
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#define portSET_INTERRUPT_MASK_FROM_ISR() vPortSetInterruptMaskFromISR()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR() vPortClearInterruptMaskFromISR()
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#define portENABLE_INTERRUPTS() \
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{ \
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unsigned portLONG ulStatus; \
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\
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/* Unmask all interrupts. */ \
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ulStatus = _CP0_GET_STATUS(); \
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ulStatus &= ~portALL_IPL_BITS; \
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_CP0_SET_STATUS( ulStatus ); \
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}
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extern void vTaskEnterCritical( void );
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extern void vTaskExitCritical( void );
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#define portCRITICAL_NESTING_IN_TCB 1
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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extern unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR();
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extern void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE );
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#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
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/*-----------------------------------------------------------*/
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