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synced 2025-04-19 21:11:57 -04:00
Update RISC-V port to use a separate interrupt stack.
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@ -34,6 +34,16 @@
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#include "task.h"
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#include "portmacro.h"
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#ifdef configISR_STACK_SIZE
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/* The stack used by interrupt service routines. */
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static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
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const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 1 ] );
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#else
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#warning What should _sp be named?
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extern const uint32_t _sp[];
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const uint32_t xISRStackTop = ( uint32_t ) _sp;
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#endif
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/*
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* Setup the timer to generate the tick interrupts. The implementation in this
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* file is weak to allow application writers to change the timer used to
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@ -54,6 +64,30 @@ const uint64_t *pullNextTime = &ullNextTime;
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const uint32_t ulTimerIncrementsForOneTick = ( uint32_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */
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volatile uint64_t * const pullMachineTimerCompareRegister = ( volatile uint64_t * const ) ( configCLINT_BASE_ADDRESS + 0x4000 );
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/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
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stack checking. A problem in the ISR stack will trigger an assert, not call the
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stack overflow hook function (because the stack overflow hook is specific to a
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task stack, not the ISR stack). */
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#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
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#warning This path not tested, or even compiled yet.
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/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
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the task stacks, and so will legitimately appear in many positions within
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the ISR stack. */
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#define portISR_STACK_FILL_BYTE 0xee
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static const uint8_t ucExpectedStackBytes[] = {
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
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portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
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#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
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#else
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/* Define the function away. */
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#define portCHECK_ISR_STACK()
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#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
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/*-----------------------------------------------------------*/
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void prvTaskExitError( void )
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@ -194,22 +228,11 @@ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLI
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/* Prepare the time to use after the next tick interrupt. */
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ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;
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/* Enable timer interrupt */
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/* Enable timer interrupt. */
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__asm volatile( "csrs mie, %0" :: "r"(0x80) ); /* 1<<7 for timer interrupt. */
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}
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/*-----------------------------------------------------------*/
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void Software_IRQHandler( void )
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{
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volatile uint32_t * const ulSoftInterrupt = ( uint32_t * ) configCLINT_BASE_ADDRESS;
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vTaskSwitchContext();
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/* Clear software interrupt. */
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*( ( uint32_t * ) configCLINT_BASE_ADDRESS ) &= 0x08UL;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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extern void xPortStartFirstTask( void );
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@ -218,10 +241,15 @@ extern void xPortStartFirstTask( void );
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{
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volatile uint32_t mtvec = 0;
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/* Check the least significant two bits of mtvec are 00 - indicating single
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vector mode. */
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/* Check the least significant two bits of mtvec are 00 - indicating
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single vector mode. */
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__asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );
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configASSERT( ( mtvec & 0x03UL ) == 0 );
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/* Check alignment of the interrupt stack - which is the same as the
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stack that was being used by main() prior to the scheduler being
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started. */
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configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
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}
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#endif
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@ -49,7 +49,7 @@
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.extern pullMachineTimerCompareRegister
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.extern pullNextTime
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.extern ulTimerIncrementsForOneTick
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.extern xISRStackTop
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/*-----------------------------------------------------------*/
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@ -136,14 +136,13 @@ vPortTrapHandler:
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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test_if_environment_call:
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li t0, 11 /* 11 == environment call when using qemu. */
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bne a0, t0, test_if_timer
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addi a1, a1, 4 /* Synchronous so return to the instruction after the environment call. */
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sw a1, 0( sp ) /* Save updated exception return address. */
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/*_RB_ Does stack need aligning here? */
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lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal vTaskSwitchContext
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j processed_source
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@ -167,13 +166,15 @@ test_if_timer:
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add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
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sw t4, 0(t1) /* Store new low word of ullNextTime. */
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sw t6, 4(t1) /* Store new high word of ullNextTime. */
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lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal xTaskIncrementTick
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beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
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jal vTaskSwitchContext
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j processed_source
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as_yet_unhandled:
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j as_yet_unhandled /* External interrupt? */
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// ebreak /* External interrupt? */
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j as_yet_unhandled
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processed_source:
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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@ -70,8 +70,9 @@ not need to be guarded with a critical section. */
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/* Scheduler utilities. */
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#define portYIELD() __asm volatile( "ecall" ); // software interrupt alternative *( ( uint32_t * ) configCLINT_BASE_ADDRESS ) |= 0x08UL
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYield()
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extern void vTaskSwitchContext( void );
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#define portYIELD() __asm volatile( "ecall" );
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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@ -84,12 +85,37 @@ extern void vTaskEnterCritical( void );
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extern void vTaskExitCritical( void );
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#define portSET_INTERRUPT_MASK_FROM_ISR() 0
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )
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#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" )
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#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" )
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
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#define portDISABLE_INTERRUPTS() __asm volatile( "csrc mstatus, 8" ); __asm volatile( "fence" )
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#define portENABLE_INTERRUPTS() __asm volatile( "csrs mstatus, 8" ); __asm volatile( "fence" )
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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/*-----------------------------------------------------------*/
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/* Architecture specific optimisations. */
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#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
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#endif
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#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
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/* Check the configuration. */
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#if( configMAX_PRIORITIES > 32 )
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#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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#endif
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/* Store/clear the ready priorities in a bit map. */
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#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
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#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
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/*-----------------------------------------------------------*/
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#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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/*-----------------------------------------------------------*/
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/* Task function macros as described on the FreeRTOS.org WEB site. These are
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@ -107,7 +133,6 @@ not necessary for to use this port. They are defined so the common demo files
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#ifndef portFORCE_INLINE
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#define portFORCE_INLINE inline __attribute__(( always_inline))
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#endif
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portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void ) {}
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#ifdef __cplusplus
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}
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