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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Notes:
+ The MPU port is not supported in this revision number. + The documentation for the static allocation functions in the header files has not yet been updated for this revision. Kernel updates: + Simplify the static allocation of objects implementation. + Introduce configSUPPORT_DYNAMIC_ALLOCATION in addition to the existing configSUPPORT_STATIC_ALLOCATION so FreeRTOS can be built without providing a heap at all. Demo application updates: + Update the demos to take into account the new configSUPPORT_DYNAMIC_ALLOCATION constant. + Add an MSVC demo that only uses static allocation, and does not include a FreeRTOS heap. + Update the MSVC project to use both configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION. + Update the MingW project to use only configSUPPORT_DYNAMIC_ALLOCATION.
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283bc18d23
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50 changed files with 2350 additions and 3914 deletions
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@ -84,6 +84,10 @@
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#include <xintc_i.h>
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#include <xtmrctr.h>
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#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
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#error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
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#endif
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/* Tasks are started with interrupts enabled. */
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#define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 )
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@ -99,7 +103,7 @@ to reach zero, so it is initialised to a high value. */
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debugging. */
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#define portISR_STACK_FILL_VALUE 0x55555555
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/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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maintains it's own count, so this variable is saved as part of the task
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context. */
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volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
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@ -117,10 +121,10 @@ uint32_t *pulISRStack;
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static void prvSetupTimerInterrupt( void );
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/*-----------------------------------------------------------*/
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/*
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* Initialise the stack of a task to look exactly as if a call to
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/*
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* Initialise the stack of a task to look exactly as if a call to
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* portSAVE_CONTEXT had been made.
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*
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*
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* See the header file portable.h.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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@ -129,16 +133,16 @@ extern void *_SDA2_BASE_, *_SDA_BASE_;
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const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
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const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
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/* Place a few bytes of known values on the bottom of the stack.
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/* Place a few bytes of known values on the bottom of the stack.
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This is essential for the Microblaze port and these lines must
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not be omitted. The parameter value will overwrite the
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not be omitted. The parameter value will overwrite the
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0x22222222 value during the function prologue. */
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*pxTopOfStack = ( StackType_t ) 0x11111111;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x22222222;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x33333333;
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pxTopOfStack--;
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pxTopOfStack--;
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/* First stack an initial value for the critical section nesting. This
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is initialised to zero as tasks are started with interrupts enabled. */
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@ -261,7 +265,7 @@ void vPortEndScheduler( void )
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/*-----------------------------------------------------------*/
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/*
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* Manual context switch called by portYIELD or taskYIELD.
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* Manual context switch called by portYIELD or taskYIELD.
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*/
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void vPortYield( void )
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{
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@ -280,7 +284,7 @@ extern void VPortYieldASM( void );
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/*-----------------------------------------------------------*/
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/*
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* Hardware initialisation to generate the RTOS tick.
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* Hardware initialisation to generate the RTOS tick.
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*/
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static void prvSetupTimerInterrupt( void )
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{
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@ -295,12 +299,12 @@ UBaseType_t uxMask;
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XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
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XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
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/* Set the timer interrupt enable bit while maintaining the other bit
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/* Set the timer interrupt enable bit while maintaining the other bit
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states. */
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uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
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XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
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XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
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XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
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XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
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XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
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/*
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* The interrupt handler placed in the interrupt vector when the scheduler is
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* started. The task context has already been saved when this is called.
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* This handler determines the interrupt source and calls the relevant
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* This handler determines the interrupt source and calls the relevant
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* peripheral handler.
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*/
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void vTaskISRHandler( void )
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{
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static uint32_t ulPending;
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static uint32_t ulPending;
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/* Which interrupts are pending? */
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ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
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}
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/*-----------------------------------------------------------*/
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/*
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/*
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* Handler for the timer interrupt.
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*/
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void vTickISR( void *pvBaseAddress )
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}
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/* Clear the timer interrupt */
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ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
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ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
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XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
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}
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/*-----------------------------------------------------------*/
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