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Synopsys ARC v1 Port: add support to Synopsys ARC v1 series cores (#110)
* Synopsys Port: Adding support to Synopsys ARC v1 series cores ARC v1 cores include ARC605, ARC610d, and ARC710d Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com> * Synopsys ARC v1 port: run uncrustify to fix code style Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com> * Synopsys port: modify license headers, change copyright only Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
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11 changed files with 867 additions and 6 deletions
321
portable/ThirdParty/GCC/ARC_v1/arc_support.s
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portable/ThirdParty/GCC/ARC_v1/arc_support.s
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/*
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* FreeRTOS Kernel V10.2.1
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* Copyright (C) 2020 Synopsys, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/**
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* \file
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* \ingroup OS_FREERTOS
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* \brief freertos support for arc processor
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* like task dispatcher, interrupt handler
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*/
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/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */
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/*
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* core-dependent part in assemble language (for arc)
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*/
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#define __ASSEMBLY__
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#include "arc/arc.h"
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#include "arc/arc_asm_common.h"
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/*
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* task dispatcher
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*
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*/
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.text
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.align 4
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.global dispatch
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dispatch:
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/*
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* the pre-conditions of this routine are task context, CPU is
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* locked, dispatch is enabled.
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*/
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SAVE_NONSCRATCH_REGS /* save callee save registers */
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mov r1, dispatch_r
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PUSH r1 /* save return address */
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ld r0, [pxCurrentTCB]
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bl dispatcher
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/* return routine when task dispatch happened in task context */
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dispatch_r:
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RESTORE_NONSCRATCH_REGS /* recover registers */
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j [blink]
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/*
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* start dispatch
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*/
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.global start_dispatch
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.align 4
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start_dispatch:
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/*
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* this routine is called in the non-task context during the startup of the kernel
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* , and all the interrupts are locked.
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*
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* when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt).
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* In target_initialize, all interrupt priority mask should be cleared, cpu should be
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* locked, the interrupts outside the kernel such as fiq can be
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* enabled.
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*/
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clri
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mov r0, 0
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st r0, [exc_nest_count]
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b dispatcher_0
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/*
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* dispatcher
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*/
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dispatcher:
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ld r1, [ulCriticalNesting]
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PUSH r1 /* save critical nesting */
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st sp, [r0] /* save stack pointer of current task, r0->pxCurrentTCB */
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jl vTaskSwitchContext /* change the value of pxCurrentTCB */
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/*
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* before dispatcher is called, task context | cpu locked | dispatch enabled
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* should be satisfied. In this routine, the processor will jump
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* into the entry of next to run task
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*
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* i.e. kernel mode, IRQ disabled, dispatch enabled
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*/
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dispatcher_0:
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ld r1, [pxCurrentTCB]
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ld sp, [r1] /* recover task stack */
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#if ARC_FEATURE_STACK_CHECK
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lr r0, [AUX_STATUS32]
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bclr r0, r0, AUX_STATUS_BIT_SC
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flag r0
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jl vPortSetStackCheck
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lr r0, [AUX_STATUS32]
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bset r0, r0, AUX_STATUS_BIT_SC
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flag r0
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#endif
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POP r0 /* get critical nesting */
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st r0, [ulCriticalNesting]
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POP r0 /* get return address */
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j [r0]
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/*
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* task startup routine
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*
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*/
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.text
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.global start_r
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.align 4
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start_r:
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seti /* unlock cpu */
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mov blink, vPortEndTask /* set return address */
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POP r1 /* get task function body */
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POP r0 /* get task parameters */
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j [r1]
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/****** exceptions and interrupts handing ******/
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/****** entry for exception handling ******/
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.global exc_entry_cpu
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.align 4
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exc_entry_cpu:
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EXCEPTION_PROLOGUE
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mov blink, sp
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mov r3, sp /* as exception handler's para(p_excinfo) */
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ld r1, [exc_nest_count]
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add r1, r1, 1
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st r1, [exc_nest_count]
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brne r1, 0, exc_handler_1
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/* change to exception stack if interrupt happened in task context */
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mov sp, _e_stack
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exc_handler_1:
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PUSH blink
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/* find the exception cause */
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#if ARC_FEATURE_CORE_700
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lr r0, [AUX_ECR]
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lsr r0, r0, 16
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bmsk r0, r0, 7
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#endif
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mov r1, exc_int_handler_table
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ld.as r2, [r1, r0]
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mov r0, r3
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jl [r2] /* !!!!jump to exception handler where interrupts are not allowed! */
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/* interrupts are not allowed */
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ret_exc:
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POP sp
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mov r1, exc_nest_count
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ld r0, [r1]
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sub r0, r0, 1
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st r0, [r1]
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brne r0, 0, ret_exc_1 /* nested exception case */
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lr r1, [AUX_IRQ_LV12]
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brne r1, 0, ret_exc_1 /* nested or pending interrupt case */
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ld r0, [context_switch_reqflg]
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brne r0, 0, ret_exc_2
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ret_exc_1: /* return from non-task context, interrupts or exceptions are nested */
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EXCEPTION_EPILOGUE
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#if ARC_FEATURE_CORE_600
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rtie ilink2
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#else
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rtie
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#endif
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/* there is a dispatch request */
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ret_exc_2:
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/* clear dispatch request */
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mov r0, 0
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st r0, [context_switch_reqflg]
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ld r0, [pxCurrentTCB]
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breq r0, 0, ret_exc_1
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SAVE_CALLEE_REGS /* save callee save registers */
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lr r0, [AUX_STATUS32]
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bclr r0, r0, AUX_STATUS_BIT_AE /* clear exception bit */
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flag r0
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mov r1, ret_exc_r /* save return address */
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PUSH r1
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bl dispatcher /* r0->pxCurrentTCB */
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ret_exc_r:
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/* recover exception status */
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lr r0, [AUX_STATUS32]
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bset r0, r0, AUX_STATUS_BIT_AE
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flag r0
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RESTORE_CALLEE_REGS /* recover registers */
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EXCEPTION_EPILOGUE
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#if ARC_FEATURE_CORE_600
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rtie ilink2
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#else
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rtie
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#endif
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/****** entry for normal interrupt exception handling ******/
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.global exc_entry_int /* entry for interrupt handling */
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.align 4
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exc_entry_int:
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INTERRUPT_PROLOGUE
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mov blink, sp
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/* disable interrupt */
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push r0
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lr r0, [AUX_STATUS32]
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push r0
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bclr r0, r0, AUX_STATUS_BIT_E1
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bclr r0, r0, AUX_STATUS_BIT_E2
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flag r0
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ld r3, [exc_nest_count]
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add r2, r3, 1
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st r2, [exc_nest_count]
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/* enable interrupt */
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pop r0
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flag r0
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pop r0
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brne r3, 0, irq_handler_1
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/* change to exception stack if interrupt happened in task context */
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mov sp, _e_stack
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#if ARC_FEATURE_STACK_CHECK
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lr r0, [AUX_STATUS32]
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bclr r0, r0, AUX_STATUS_BIT_SC
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flag r0
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#endif
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irq_handler_1:
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PUSH blink
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/* critical area */
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#if ARC_FEATURE_CORE_700
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lr r0, [AUX_IRQ_CAUSE1]
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#endif
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mov r1, exc_int_handler_table
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ld.as r2, [r1, r0] /* r2 = exc_int_handler_table + irqno *4 */
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/* handle software triggered interrupt */
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lr r3, [AUX_IRQ_HINT]
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cmp r3, r0
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bne.d irq_hint_handled
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xor r3, r3, r3
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sr r3, [AUX_IRQ_HINT]
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irq_hint_handled:
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jl [r2] /* jump to interrupt handler */
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/* no interrupts are allowed from here */
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ret_int:
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clri /* disable interrupt */
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POP sp
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mov r1, exc_nest_count
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ld r0, [r1]
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sub r0, r0, 1
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st r0, [r1]
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/* if there are multi-bits set in IRQ_LV12, it's still in nest interrupt */
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lr r1, [AUX_IRQ_LV12]
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ld r0, [context_switch_reqflg]
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brne r0, 0, ret_int_2
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ret_int_1: /* return from non-task context */
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INTERRUPT_EPILOGUE
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#if ARC_FEATURE_CORE_600
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/* TODO: series 600 IRQ6 and IRQ7 uses ilink2 */
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rtie ilink1
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#else
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rtie
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#endif
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/* there is a dispatch request */
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ret_int_2:
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/* clear dispatch request */
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mov r0, 0
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st r0, [context_switch_reqflg]
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ld r0, [pxCurrentTCB]
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breq r0, 0, ret_int_1
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/* r1 has old AUX_IRQ_LV12 */
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PUSH r1
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/* clear related bits in IRQ_ACT manually to simulate a irq return */
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SAVE_CALLEE_REGS /* save callee save registers */
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mov r1, ret_int_r /* save return address */
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PUSH r1
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bl dispatcher /* r0->pxCurrentTCB */
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ret_int_r:
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RESTORE_CALLEE_REGS /* recover registers */
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POPAX AUX_IRQ_LV12
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INTERRUPT_EPILOGUE
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#if ARC_FEATURE_CORE_600
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rtie ilink1
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#else
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rtie
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#endif
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/** @endcond */
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