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Kernel changes:
Exclude the entire croutine.c file when configUSE_CO_ROUTINES is 0. New ports: Added Cortex-M7 IAR and Keil port layers that include a minor errata workaround r0p1 Cortex-M7 devices. Added Cortex-M4F port layer for CCS. New demo applications: Added demo application for STM32F7. Added demo application for SAMv71.
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557 changed files with 284426 additions and 16 deletions
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@ -108,6 +108,12 @@
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#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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r0p1 port. */
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#define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
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#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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@ -262,6 +268,16 @@ static void prvTaskExitError( void )
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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/* This port can be used on all revisions of the Cortex-M7 core other than
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the r0p1 parts. r0p1 parts should use the port from the
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/source/portable/GCC/ARM_CM7/r0p1 directory. */
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configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
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configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
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#if( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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