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Associate secure context with task handle
The secure side context management code now checks that the secure context being saved or restored belongs to the task being switched-out or switched-in respectively. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Gaurav Aggarwal
Gaurav-Aggarwal-AWS
parent
ccaa0f4d6e
commit
61f7560243
53 changed files with 1796 additions and 1353 deletions
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@ -51,66 +51,66 @@ void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_
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" ldr r0, [r3] \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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" \n"
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#if ( configENABLE_MPU == 1 )
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" dmb \n"/* Complete outstanding transfers before disabling MPU. */
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" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
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" bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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" str r4, [r2] \n"/* Disable MPU. */
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" \n"
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" adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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" ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
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" ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r4, [r2] \n"/* Program MAIR0. */
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" ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
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" movs r4, #4 \n"/* r4 = 4. */
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" str r4, [r2] \n"/* Program RNR = 4. */
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" adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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" ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
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" \n"
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" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
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" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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" str r4, [r2] \n"/* Enable MPU. */
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" dsb \n"/* Force memory writes before continuing. */
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" dmb \n"/* Complete outstanding transfers before disabling MPU. */
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" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
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" bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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" str r4, [r2] \n"/* Disable MPU. */
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" \n"
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" adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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" ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
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" ldr r2, xMAIR0Const2 \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r4, [r2] \n"/* Program MAIR0. */
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" ldr r2, xRNRConst2 \n"/* r2 = 0xe000ed98 [Location of RNR]. */
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" movs r4, #4 \n"/* r4 = 4. */
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" str r4, [r2] \n"/* Program RNR = 4. */
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" adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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" ldr r2, xRBARConst2 \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r3!, {r4-r11} \n"/* Read 4 set of RBAR/RLAR registers from TCB. */
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" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
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" \n"
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" ldr r2, xMPUCTRLConst2 \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
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" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
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" str r4, [r2] \n"/* Enable MPU. */
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" dsb \n"/* Force memory writes before continuing. */
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#endif /* configENABLE_MPU */
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" \n"
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#if ( configENABLE_MPU == 1 )
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" ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
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" ldr r5, xSecureContextConst2 \n"
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" str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
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" msr psplim, r2 \n"/* Set this task's PSPLIM value. */
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" msr control, r3 \n"/* Set this task's CONTROL value. */
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" adds r0, #32 \n"/* Discard everything up to r0. */
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" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
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" bx r4 \n"/* Finally, branch to EXC_RETURN. */
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" ldm r0!, {r1-r4} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
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" ldr r5, xSecureContextConst2 \n"
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" str r1, [r5] \n"/* Set xSecureContext to this task's value for the same. */
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" msr psplim, r2 \n"/* Set this task's PSPLIM value. */
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" msr control, r3 \n"/* Set this task's CONTROL value. */
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" adds r0, #32 \n"/* Discard everything up to r0. */
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" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
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" bx r4 \n"/* Finally, branch to EXC_RETURN. */
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#else /* configENABLE_MPU */
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" ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
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" ldr r4, xSecureContextConst2 \n"
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" str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
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" msr psplim, r2 \n"/* Set this task's PSPLIM value. */
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" movs r1, #2 \n"/* r1 = 2. */
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" msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
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" adds r0, #32 \n"/* Discard everything up to r0. */
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" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
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" bx r3 \n"/* Finally, branch to EXC_RETURN. */
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" ldm r0!, {r1-r3} \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
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" ldr r4, xSecureContextConst2 \n"
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" str r1, [r4] \n"/* Set xSecureContext to this task's value for the same. */
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" msr psplim, r2 \n"/* Set this task's PSPLIM value. */
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" movs r1, #2 \n"/* r1 = 2. */
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" msr CONTROL, r1 \n"/* Switch to use PSP in the thread mode. */
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" adds r0, #32 \n"/* Discard everything up to r0. */
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" msr psp, r0 \n"/* This is now the new top of stack to use in the task. */
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" isb \n"
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" mov r0, #0 \n"
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" msr basepri, r0 \n"/* Ensure that interrupts are enabled when the first task starts. */
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" bx r3 \n"/* Finally, branch to EXC_RETURN. */
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#endif /* configENABLE_MPU */
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" \n"
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" .align 4 \n"
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"pxCurrentTCBConst2: .word pxCurrentTCB \n"
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"xSecureContextConst2: .word xSecureContext \n"
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#if ( configENABLE_MPU == 1 )
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"xMPUCTRLConst2: .word 0xe000ed94 \n"
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"xMAIR0Const2: .word 0xe000edc0 \n"
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"xRNRConst2: .word 0xe000ed98 \n"
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"xRBARConst2: .word 0xe000ed9c \n"
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"xMPUCTRLConst2: .word 0xe000ed94 \n"
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"xMAIR0Const2: .word 0xe000edc0 \n"
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"xRNRConst2: .word 0xe000ed98 \n"
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"xRBARConst2: .word 0xe000ed9c \n"
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#endif /* configENABLE_MPU */
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);
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}
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@ -217,62 +217,65 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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" .extern SecureContext_SaveContext \n"
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" .extern SecureContext_LoadContext \n"
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" \n"
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" mrs r1, psp \n"/* Read PSP in r1. */
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" ldr r2, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
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" ldr r0, [r2] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
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" ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
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" ldr r0, [r3] \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
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" ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r3] \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
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" mrs r2, psp \n"/* Read PSP in r2. */
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" \n"
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" cbz r0, save_ns_context \n"/* No secure context to save. */
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" push {r0-r2, r14} \n"
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" bl SecureContext_SaveContext \n"
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" bl SecureContext_SaveContext \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
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" pop {r0-r3} \n"/* LR is now in r3. */
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" mov lr, r3 \n"/* LR = r3. */
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" lsls r2, r3, #25 \n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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" bpl save_ns_context \n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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" lsls r1, r3, #25 \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
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" bpl save_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
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" \n"
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" ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r2, [r3] \n"/* Read pxCurrentTCB. */
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" ldr r1, [r3] \n"/* Read pxCurrentTCB.*/
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#if ( configENABLE_MPU == 1 )
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" subs r1, r1, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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" str r1, [r2] \n"/* Save the new top of stack in TCB. */
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" mrs r2, psplim \n"/* r2 = PSPLIM. */
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" mrs r3, control \n"/* r3 = CONTROL. */
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" mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
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" stmia r1!, {r0, r2-r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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" subs r2, r2, #16 \n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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" str r2, [r1] \n"/* Save the new top of stack in TCB. */
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" mrs r1, psplim \n"/* r1 = PSPLIM. */
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" mrs r3, control \n"/* r3 = CONTROL. */
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" mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
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" stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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#else /* configENABLE_MPU */
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" subs r1, r1, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
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" str r1, [r2] \n"/* Save the new top of stack in TCB. */
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" mrs r2, psplim \n"/* r2 = PSPLIM. */
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" mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
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" stmia r1!, {r0, r2-r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
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" subs r2, r2, #12 \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
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" str r2, [r1] \n"/* Save the new top of stack in TCB. */
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" mrs r1, psplim \n"/* r1 = PSPLIM. */
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" mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
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" stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
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#endif /* configENABLE_MPU */
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" b select_next_task \n"
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" \n"
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" save_ns_context: \n"
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" ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r2, [r3] \n"/* Read pxCurrentTCB. */
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" ldr r1, [r3] \n"/* Read pxCurrentTCB. */
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#if ( configENABLE_FPU == 1 )
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" tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
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" it eq \n"
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" vstmdbeq r1!, {s16-s31} \n"/* Store the FPU registers which are not saved automatically. */
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" tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
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" it eq \n"
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" vstmdbeq r2!, {s16-s31} \n"/* Store the FPU registers which are not saved automatically. */
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#endif /* configENABLE_FPU */
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#if ( configENABLE_MPU == 1 )
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" subs r1, r1, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
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" str r1, [r2] \n"/* Save the new top of stack in TCB. */
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" adds r1, r1, #16 \n"/* r1 = r1 + 16. */
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" stm r1, {r4-r11} \n"/* Store the registers that are not saved automatically. */
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" mrs r2, psplim \n"/* r2 = PSPLIM. */
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" mrs r3, control \n"/* r3 = CONTROL. */
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" mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
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" subs r1, r1, #16 \n"/* r1 = r1 - 16. */
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" stm r1, {r0, r2-r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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" subs r2, r2, #48 \n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
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" str r2, [r1] \n"/* Save the new top of stack in TCB. */
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" adds r2, r2, #16 \n"/* r2 = r2 + 16. */
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" stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
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" mrs r1, psplim \n"/* r1 = PSPLIM. */
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" mrs r3, control \n"/* r3 = CONTROL. */
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" mov r4, lr \n"/* r4 = LR/EXC_RETURN. */
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" subs r2, r2, #16 \n"/* r2 = r2 - 16. */
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" stmia r2!, {r0, r1, r3, r4} \n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
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#else /* configENABLE_MPU */
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" subs r1, r1, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
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" str r1, [r2] \n"/* Save the new top of stack in TCB. */
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" adds r1, r1, #12 \n"/* r1 = r1 + 12. */
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" stm r1, {r4-r11} \n"/* Store the registers that are not saved automatically. */
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" mrs r2, psplim \n"/* r2 = PSPLIM. */
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" mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
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" subs r1, r1, #12 \n"/* r1 = r1 - 12. */
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" stmia r1!, {r0, r2-r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
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" subs r2, r2, #44 \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
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" str r2, [r1] \n"/* Save the new top of stack in TCB. */
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" adds r2, r2, #12 \n"/* r2 = r2 + 12. */
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" stm r2, {r4-r11} \n"/* Store the registers that are not saved automatically. */
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" mrs r1, psplim \n"/* r1 = PSPLIM. */
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" mov r3, lr \n"/* r3 = LR/EXC_RETURN. */
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" subs r2, r2, #12 \n"/* r2 = r2 - 12. */
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" stmia r2!, {r0, r1, r3} \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
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#endif /* configENABLE_MPU */
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" \n"
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" select_next_task: \n"
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@ -284,87 +287,91 @@ void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
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" mov r0, #0 \n"/* r0 = 0. */
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" msr basepri, r0 \n"/* Enable interrupts. */
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" \n"
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" ldr r2, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r3, [r2] \n"/* Read pxCurrentTCB. */
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" ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
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" ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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" ldr r1, [r3] \n"/* Read pxCurrentTCB. */
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" ldr r2, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
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" \n"
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#if ( configENABLE_MPU == 1 )
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" dmb \n"/* Complete outstanding transfers before disabling MPU. */
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" ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
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" bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
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" str r4, [r2] \n"/* Disable MPU. */
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" \n"
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" adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
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" ldr r4, [r3] \n"/* r4 = *r3 i.e. r4 = MAIR0. */
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" ldr r2, xMAIR0Const \n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
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" str r4, [r2] \n"/* Program MAIR0. */
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" ldr r2, xRNRConst \n"/* r2 = 0xe000ed98 [Location of RNR]. */
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" movs r4, #4 \n"/* r4 = 4. */
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" str r4, [r2] \n"/* Program RNR = 4. */
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" adds r3, #4 \n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
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" ldr r2, xRBARConst \n"/* r2 = 0xe000ed9c [Location of RBAR]. */
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" ldmia r3!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
|
||||
" stmia r2!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
|
||||
" \n"
|
||||
" ldr r2, xMPUCTRLConst \n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r4, [r2] \n"/* Read the value of MPU_CTRL. */
|
||||
" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
|
||||
" str r4, [r2] \n"/* Enable MPU. */
|
||||
" dsb \n"/* Force memory writes before continuing. */
|
||||
" dmb \n"/* Complete outstanding transfers before disabling MPU. */
|
||||
" ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
|
||||
" bic r4, #1 \n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
|
||||
" str r4, [r3] \n"/* Disable MPU. */
|
||||
" \n"
|
||||
" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
|
||||
" ldr r4, [r1] \n"/* r4 = *r1 i.e. r4 = MAIR0. */
|
||||
" ldr r3, xMAIR0Const \n"/* r3 = 0xe000edc0 [Location of MAIR0]. */
|
||||
" str r4, [r3] \n"/* Program MAIR0. */
|
||||
" ldr r3, xRNRConst \n"/* r3 = 0xe000ed98 [Location of RNR]. */
|
||||
" movs r4, #4 \n"/* r4 = 4. */
|
||||
" str r4, [r3] \n"/* Program RNR = 4. */
|
||||
" adds r1, #4 \n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
|
||||
" ldr r3, xRBARConst \n"/* r3 = 0xe000ed9c [Location of RBAR]. */
|
||||
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
|
||||
" stmia r3!, {r4-r11} \n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
|
||||
" \n"
|
||||
" ldr r3, xMPUCTRLConst \n"/* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
|
||||
" ldr r4, [r3] \n"/* Read the value of MPU_CTRL. */
|
||||
" orr r4, #1 \n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
|
||||
" str r4, [r3] \n"/* Enable MPU. */
|
||||
" dsb \n"/* Force memory writes before continuing. */
|
||||
#endif /* configENABLE_MPU */
|
||||
" \n"
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
" ldmia r1!, {r0, r2-r4} \n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
|
||||
" msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
|
||||
" msr control, r3 \n"/* Restore the CONTROL register value for the task. */
|
||||
" mov lr, r4 \n"/* LR = r4. */
|
||||
" ldr r2, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
|
||||
" str r0, [r2] \n"/* Restore the task's xSecureContext. */
|
||||
" cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
|
||||
" push {r1,r4} \n"
|
||||
" bl SecureContext_LoadContext \n"/* Restore the secure context. */
|
||||
" pop {r1,r4} \n"
|
||||
" mov lr, r4 \n"/* LR = r4. */
|
||||
" lsls r2, r4, #25 \n"/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
|
||||
" bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
|
||||
" msr psp, r1 \n"/* Remember the new top of stack for the task. */
|
||||
" bx lr \n"
|
||||
" ldmia r2!, {r0, r1, r3, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
|
||||
" msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
|
||||
" msr control, r3 \n"/* Restore the CONTROL register value for the task. */
|
||||
" mov lr, r4 \n"/* LR = r4. */
|
||||
" ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
|
||||
" str r0, [r3] \n"/* Restore the task's xSecureContext. */
|
||||
" cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
|
||||
" ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r3] \n"/* Read pxCurrentTCB. */
|
||||
" push {r2, r4} \n"
|
||||
" bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
|
||||
" pop {r2, r4} \n"
|
||||
" mov lr, r4 \n"/* LR = r4. */
|
||||
" lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
|
||||
" bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
|
||||
" msr psp, r2 \n"/* Remember the new top of stack for the task. */
|
||||
" bx lr \n"
|
||||
#else /* configENABLE_MPU */
|
||||
" ldmia r1!, {r0, r2-r3} \n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
|
||||
" msr psplim, r2 \n"/* Restore the PSPLIM register value for the task. */
|
||||
" mov lr, r3 \n"/* LR = r3. */
|
||||
" ldr r2, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
|
||||
" str r0, [r2] \n"/* Restore the task's xSecureContext. */
|
||||
" cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
|
||||
" push {r1,r3} \n"
|
||||
" bl SecureContext_LoadContext \n"/* Restore the secure context. */
|
||||
" pop {r1,r3} \n"
|
||||
" mov lr, r3 \n"/* LR = r3. */
|
||||
" lsls r2, r3, #25 \n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
|
||||
" bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
|
||||
" msr psp, r1 \n"/* Remember the new top of stack for the task. */
|
||||
" bx lr \n"
|
||||
" ldmia r2!, {r0, r1, r4} \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
|
||||
" msr psplim, r1 \n"/* Restore the PSPLIM register value for the task. */
|
||||
" mov lr, r4 \n"/* LR = r4. */
|
||||
" ldr r3, xSecureContextConst \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
|
||||
" str r0, [r3] \n"/* Restore the task's xSecureContext. */
|
||||
" cbz r0, restore_ns_context \n"/* If there is no secure context for the task, restore the non-secure context. */
|
||||
" ldr r3, pxCurrentTCBConst \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
|
||||
" ldr r1, [r3] \n"/* Read pxCurrentTCB. */
|
||||
" push {r2, r4} \n"
|
||||
" bl SecureContext_LoadContext \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
|
||||
" pop {r2, r4} \n"
|
||||
" mov lr, r4 \n"/* LR = r4. */
|
||||
" lsls r1, r4, #25 \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
|
||||
" bpl restore_ns_context \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
|
||||
" msr psp, r2 \n"/* Remember the new top of stack for the task. */
|
||||
" bx lr \n"
|
||||
#endif /* configENABLE_MPU */
|
||||
" \n"
|
||||
" restore_ns_context: \n"
|
||||
" ldmia r1!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */
|
||||
" ldmia r2!, {r4-r11} \n"/* Restore the registers that are not automatically restored. */
|
||||
#if ( configENABLE_FPU == 1 )
|
||||
" tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
|
||||
" it eq \n"
|
||||
" vldmiaeq r1!, {s16-s31} \n"/* Restore the FPU registers which are not restored automatically. */
|
||||
" tst lr, #0x10 \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
|
||||
" it eq \n"
|
||||
" vldmiaeq r2!, {s16-s31} \n"/* Restore the FPU registers which are not restored automatically. */
|
||||
#endif /* configENABLE_FPU */
|
||||
" msr psp, r1 \n"/* Remember the new top of stack for the task. */
|
||||
" msr psp, r2 \n"/* Remember the new top of stack for the task. */
|
||||
" bx lr \n"
|
||||
" \n"
|
||||
" .align 4 \n"
|
||||
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
||||
"xSecureContextConst: .word xSecureContext \n"
|
||||
#if ( configENABLE_MPU == 1 )
|
||||
"xMPUCTRLConst: .word 0xe000ed94 \n"
|
||||
"xMAIR0Const: .word 0xe000edc0 \n"
|
||||
"xRNRConst: .word 0xe000ed98 \n"
|
||||
"xRBARConst: .word 0xe000ed9c \n"
|
||||
"xMPUCTRLConst: .word 0xe000ed94 \n"
|
||||
"xMAIR0Const: .word 0xe000edc0 \n"
|
||||
"xRNRConst: .word 0xe000ed98 \n"
|
||||
"xRBARConst: .word 0xe000ed9c \n"
|
||||
#endif /* configENABLE_MPU */
|
||||
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
|
||||
);
|
||||
|
|
@ -403,9 +410,9 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
|
|||
{
|
||||
__asm volatile
|
||||
(
|
||||
" ldr r1, [r0] \n"/* The first item in the TCB is the top of the stack. */
|
||||
" ldr r0, [r1] \n"/* The first item on the stack is the task's xSecureContext. */
|
||||
" cmp r0, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
|
||||
" ldr r2, [r0] \n"/* The first item in the TCB is the top of the stack. */
|
||||
" ldr r1, [r2] \n"/* The first item on the stack is the task's xSecureContext. */
|
||||
" cmp r1, #0 \n"/* Raise svc if task's xSecureContext is not NULL. */
|
||||
" it ne \n"
|
||||
" svcne %0 \n"/* Secure context is freed in the supervisor call. */
|
||||
" bx lr \n"/* Return. */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue