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Tidy up - spell check.

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This commit is contained in:
Richard Barry 2008-02-13 11:15:52 +00:00
parent 5a418b56fa
commit 613c764189
8 changed files with 242 additions and 179 deletions
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3
Demo/MB91460_Softune/91467d_FreeRTOS.prj
View file

@ -140,9 +140,10 @@ F7-10=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stddef.h
F7-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdarg.h F7-11=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdarg.h
F7-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h F7-12=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\stdlib.h
F7-13=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\string.h F7-13=- ..\..\..\..\..\..\devtools\Softune6\LIB\911\INCLUDE\string.h
F8=2 c 1 SRC\vectors.c F8=3 c 1 SRC\vectors.c
F8-1=- SRC\mb91467d.h F8-1=- SRC\mb91467d.h
F8-2=- SRC\watchdog\watchdog.h F8-2=- SRC\watchdog\watchdog.h
F8-3=- SRC\FreeRTOSConfig.h
F9=1 a 1 SRC\mb91467d.asm F9=1 a 1 SRC\mb91467d.asm
F9-1=- SRC\mb91467d.h F9-1=- SRC\mb91467d.h
F10=0 a 1 SRC\Start91460.asm F10=0 a 1 SRC\Start91460.asm

4
Demo/MB91460_Softune/91467d_FreeRTOS.wsp
View file

@ -19,7 +19,5 @@ WSP=C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\MB91460_Softune\
[EditState] [EditState]
STATE-1=SRC\main.c:18 STATE-1=SRC\main.c:18
STATE-2=..\..\Source\queue.c:988 Count=1
STATE-3=..\..\Source\tasks.c:1342
Count=3

2
Demo/MB91460_Softune/SRC/FreeRTOSConfig.h
View file

@ -78,4 +78,6 @@ to exclude the API function. */
#define INCLUDE_vTaskDelay 1 #define INCLUDE_vTaskDelay 1
#define INCLUDE_vResumeFromISR 1 #define INCLUDE_vResumeFromISR 1
#define configKERNEL_INTERRUPT_PRIORITY 30
#endif /* FREERTOS_CONFIG_H */ #endif /* FREERTOS_CONFIG_H */

111
Demo/MB91460_Softune/SRC/main.c
View file

@ -1,30 +1,72 @@
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /*
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
/* ELIGIBILITY FOR ANY PURPOSES. */
/* (C) Fujitsu Microelectronics Europe GmbH */ This file is part of the FreeRTOS.org distribution.
/*------------------------------------------------------------------------
MAIN.C FreeRTOS.org is free software; you can redistribute it and/or modify
- description it under the terms of the GNU General Public License as published by
- See README.TXT for project description and disclaimer. the Free Software Foundation; either version 2 of the License, or
-------------------------------------------------------------------------*/ (at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
***************************************************************************
*/
/* /*
* Creates all the demo application tasks, then starts the scheduler. The WEB * Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks. * documentation provides more details of the demo application tasks.
* *
* Main.c also creates a task called "Check". This only executes every three * In addition to the standard demo tasks, the follow demo specific tasks are
* seconds but has the highest priority so is guaranteed to get processor time. * create:
* Its main function is to check that all the other tasks are still operational. *
* Each task (other than the "flash" tasks) maintains a unique count that is * The "Check" task. This only executes every three seconds but has the highest
* incremented each time the task successfully completes its function. Should * priority so is guaranteed to get processor time. Its main function is to
* any error occur within such a task the count is permanently halted. The * check that all the other tasks are still operational. Most tasks maintain
* check task inspects the count of each task to ensure it has changed since * a unique count that is incremented each time the task successfully completes
* the last time the check task executed. If all the count variables have * its function. Should any error occur within such a task the count is
* changed all the tasks are still executing error free, and the check task * permanently halted. The check task inspects the count of each task to ensure
* toggles the onboard LED. Should any task contain an error at any time * it has changed since the last time the check task executed. If all the count
* variables have changed all the tasks are still executing error free, and the
* check task toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms. * the LED toggle rate will change from 3 seconds to 500ms.
* *
* The "Register Check" tasks. These tasks fill the CPU registers with known
* values, then check that each register still contains the expected value 0 the
* discovery of an unexpected value being indicative of an error in the RTOS
* context switch mechanism. The register check tasks operate at low priority
* so are switched in and out frequently.
*
* The "Trace Utility" task. This can be used to obtain trace and debug
* information via UART5.
*/ */
@ -72,7 +114,7 @@
top of the page. When the system is operating error free the 'Check' task top of the page. When the system is operating error free the 'Check' task
toggles an LED every three seconds. If an error is discovered in any task the toggles an LED every three seconds. If an error is discovered in any task the
rate is increased to 500 milliseconds. [in this case the '*' characters on the rate is increased to 500 milliseconds. [in this case the '*' characters on the
LCD represent LED's]*/ LCD represent LEDs]*/
#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS ) #define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) #define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS )
@ -94,7 +136,7 @@ LCD represent LED's]*/
* The function that implements the Check task. See the comments at the head * The function that implements the Check task. See the comments at the head
* of the page for implementation details. * of the page for implementation details.
*/ */
static void vErrorChecks( void *pvParameters ); static void prvErrorChecks( void *pvParameters );
/* /*
* Called by the Check task. Returns pdPASS if all the other tasks are found * Called by the Check task. Returns pdPASS if all the other tasks are found
@ -147,8 +189,9 @@ void main(void)
vCreateBlockTimeTasks(); vCreateBlockTimeTasks();
/* Start the 'Check' task which is defined in this file. */ /* Start the 'Check' task which is defined in this file. */
xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); xTaskCreate( prvErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the 'Register Test' tasks as described at the top of this file. */
xTaskCreate( vFirstRegisterTestTask, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); xTaskCreate( vFirstRegisterTestTask, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
xTaskCreate( vSecondRegisterTestTask, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); xTaskCreate( vSecondRegisterTestTask, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
@ -176,7 +219,7 @@ void main(void)
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters ) static void prvErrorChecks( void *pvParameters )
{ {
portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime; portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime;
@ -292,6 +335,8 @@ static unsigned portLONG ulLastRegTest1Counter = 0UL, ulLastRegTest2Counter = 0U
lReturn = pdFAIL; lReturn = pdFAIL;
} }
/* Record the current values of the register check cycle counters so we
can ensure they are still running the next time this function is called. */
ulLastRegTest1Counter = ulRegTest1Counter; ulLastRegTest1Counter = ulRegTest1Counter;
ulLastRegTest2Counter = ulRegTest2Counter; ulLastRegTest2Counter = ulRegTest2Counter;
@ -317,29 +362,29 @@ static void prvSetupHardware( void )
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* The below callback function is called from Delayed ISR if configUSE_IDLE_HOOK /* Idle hook function. */
is configured as 1. */
#if configUSE_IDLE_HOOK == 1 #if configUSE_IDLE_HOOK == 1
void vApplicationIdleHook( void ) void vApplicationIdleHook( void )
{ {
/* Are we using the idle task to kick the watchdog? */ /* Are we using the idle task to kick the watchdog? See watchdog.h
for watchdog kicking options. Note this is for demonstration only
and is not a suggested method of servicing the watchdog in a real
application. */
#if WATCHDOG == WTC_IN_IDLE #if WATCHDOG == WTC_IN_IDLE
Kick_Watchdog(); Kick_Watchdog();
#endif #endif
#if configUSE_CO_ROUTINES == 1
vCoRoutineSchedule();
#endif
} }
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* /* Tick hook function. */
The below callback function is called from Tick ISR if configUSE_TICK_HOOK
is configured as 1. */
#if configUSE_TICK_HOOK == 1 #if configUSE_TICK_HOOK == 1
void vApplicationTickHook( void ) void vApplicationTickHook( void )
{ {
/* Are we using the tick to kick the watchdog? See watchdog.h
for watchdog kicking options. Note this is for demonstration
only and is not a suggested method of servicing the watchdog in
a real application. */
#if WATCHDOG == WTC_IN_TICK #if WATCHDOG == WTC_IN_TICK
Kick_Watchdog(); Kick_Watchdog();
#endif #endif

33
Demo/MB91460_Softune/SRC/serial/serial.c
View file

@ -1,5 +1,5 @@
/* /*
FreeRTOS.org V4.7.0 - Copyright (C) 2003-2007 Richard Barry. FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution. This file is part of the FreeRTOS.org distribution.
@ -19,23 +19,30 @@
A special exception to the GPL can be applied should you wish to distribute A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception of http://www.FreeRTOS.org for full details of how and when the exception
can be applied. can be applied.
*************************************************************************** ***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
Also see http://www.SafeRTOS.com a version that has been certified for use Please ensure to read the configuration and relevant port sections of the
in safety critical systems, plus commercial licensing, development and online documentation.
support options.
+++ http://www.FreeRTOS.org +++
Documentation, latest information, license and contact details.
+++ http://www.SafeRTOS.com +++
A version that is certified for use in safety critical systems.
+++ http://www.OpenRTOS.com +++
Commercial support, development, porting, licensing and training services.
*************************************************************************** ***************************************************************************
*/ */
/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. /*
* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER.
* *
* This file only supports UART 2 * This file only supports UART 2
*/ */
@ -63,8 +70,6 @@ static volatile portSHORT sTHREEmpty;
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{ {
//unsigned portLONG ulBaudRateCount;
portENTER_CRITICAL(); portENTER_CRITICAL();
{ {
/* Create the queues used by the com test task. */ /* Create the queues used by the com test task. */
@ -78,10 +83,10 @@ xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned
SMR02 = 0x0d; /* enable SOT3, Reset, normal mode */ SMR02 = 0x0d; /* enable SOT3, Reset, normal mode */
SSR02 = 0x02; /* LSB first, enable receive interrupts */ SSR02 = 0x02; /* LSB first, enable receive interrupts */
PFR20_D0 = 1; // enable UART PFR20_D0 = 1; /* enable UART */
PFR20_D1 = 1; // enable UART PFR20_D1 = 1; /* enable UART */
EPFR20_D1 = 0; // enable UART EPFR20_D1 = 0; /* enable UART */
} }
portEXIT_CRITICAL(); portEXIT_CRITICAL();

255
Demo/MB91460_Softune/SRC/vectors.c
View file

@ -17,6 +17,7 @@
#include "mb91467d.h" #include "mb91467d.h"
#include "watchdog.h" #include "watchdog.h"
#include "FreeRTOSConfig.h"
/*------------------------------------------------------------------------ /*------------------------------------------------------------------------
InitIrqLevels() InitIrqLevels()
@ -34,133 +35,133 @@ void InitIrqLevels(void)
/* ICRxx */ /* ICRxx */
/* Softune Workbench Monitor Debugger is using ext int0 for abort function */ /* Softune Workbench Monitor Debugger is using ext int0 for abort function */
/* ICR00 = 31; *//* External Interrupt 0 */ /* ICR00 = 31; *//* External Interrupt 0 */
/* External Interrupt 1 */ /* External Interrupt 1 */
ICR01 = 31; /* External Interrupt 2 */ ICR01 = 31; /* External Interrupt 2 */
/* External Interrupt 3 */ /* External Interrupt 3 */
ICR02 = 31; /* External Interrupt 4 */ ICR02 = 31; /* External Interrupt 4 */
/* External Interrupt 5 */ /* External Interrupt 5 */
ICR03 = 31; /* External Interrupt 6 */ ICR03 = 31; /* External Interrupt 6 */
/* External Interrupt 7 */ /* External Interrupt 7 */
ICR04 = 31; /* External Interrupt 8 */ ICR04 = 31; /* External Interrupt 8 */
/* External Interrupt 9 */ /* External Interrupt 9 */
ICR05 = 31; /* External Interrupt 10 */ ICR05 = 31; /* External Interrupt 10 */
/* External Interrupt 11 */ /* External Interrupt 11 */
ICR06 = 31; /* External Interrupt 12 */ ICR06 = 31; /* External Interrupt 12 */
/* External Interrupt 13 */ /* External Interrupt 13 */
ICR07 = 31; /* External Interrupt 14 */ ICR07 = 31; /* External Interrupt 14 */
/* External Interrupt 15 */ /* External Interrupt 15 */
ICR08 = 30; /* Reload Timer 0 */ ICR08 = configKERNEL_INTERRUPT_PRIORITY; /* Reload Timer 0 */
/* Reload Timer 1 */ /* Reload Timer 1 */
ICR09 = 31; /* Reload Timer 2 */ ICR09 = 31; /* Reload Timer 2 */
/* Reload Timer 3 */ /* Reload Timer 3 */
ICR10 = 31; /* Reload Timer 4 */ ICR10 = 31; /* Reload Timer 4 */
/* Reload Timer 5 */ /* Reload Timer 5 */
ICR11 = 31; /* Reload Timer 6 */ ICR11 = 31; /* Reload Timer 6 */
/* Reload Timer 7 */ /* Reload Timer 7 */
ICR12 = 31; /* Free Run Timer 0 */ ICR12 = 31; /* Free Run Timer 0 */
/* Free Run Timer 1 */ /* Free Run Timer 1 */
ICR13 = 31; /* Free Run Timer 2 */ ICR13 = 31; /* Free Run Timer 2 */
/* Free Run Timer 3 */ /* Free Run Timer 3 */
ICR14 = 31; /* Free Run Timer 4 */ ICR14 = 31; /* Free Run Timer 4 */
/* Free Run Timer 5 */ /* Free Run Timer 5 */
ICR15 = 31; /* Free Run Timer 6 */ ICR15 = 31; /* Free Run Timer 6 */
/* Free Run Timer 7 */ /* Free Run Timer 7 */
ICR16 = 31; /* CAN 0 */ ICR16 = 31; /* CAN 0 */
/* CAN 1 */ /* CAN 1 */
ICR17 = 31; /* CAN 2 */ ICR17 = 31; /* CAN 2 */
/* CAN 3 */ /* CAN 3 */
ICR18 = 31; /* CAN 4 */ ICR18 = 31; /* CAN 4 */
/* CAN 5 */ /* CAN 5 */
ICR19 = 31; /* USART (LIN) 0 RX */ ICR19 = 31; /* USART (LIN) 0 RX */
/* USART (LIN) 0 TX */ /* USART (LIN) 0 TX */
ICR20 = 31; /* USART (LIN) 1 RX */ ICR20 = 31; /* USART (LIN) 1 RX */
/* USART (LIN) 1 TX */ /* USART (LIN) 1 TX */
ICR21 = 30; /* USART (LIN) 2 RX */ ICR21 = configKERNEL_INTERRUPT_PRIORITY; /* USART (LIN) 2 RX */
/* USART (LIN) 2 TX */ /* USART (LIN) 2 TX */
ICR22 = 31; /* USART (LIN) 3 RX */ ICR22 = 31; /* USART (LIN) 3 RX */
/* USART (LIN) 3 TX */ /* USART (LIN) 3 TX */
ICR23 = 30; /* System Reserved */ ICR23 = configKERNEL_INTERRUPT_PRIORITY; /* System Reserved */
/* Delayed Interrupt */ /* Delayed Interrupt */
ICR24 = 31; /* System Reserved */ ICR24 = 31; /* System Reserved */
/* System Reserved */ /* System Reserved */
ICR25 = 31; /* USART (LIN, FIFO) 4 RX */ ICR25 = 31; /* USART (LIN, FIFO) 4 RX */
/* USART (LIN, FIFO) 4 TX */ /* USART (LIN, FIFO) 4 TX */
ICR26 = 30; /* USART (LIN, FIFO) 5 RX */ ICR26 = configKERNEL_INTERRUPT_PRIORITY; /* USART (LIN, FIFO) 5 RX */
/* USART (LIN, FIFO) 5 TX */ /* USART (LIN, FIFO) 5 TX */
ICR27 = 31; /* USART (LIN, FIFO) 6 RX */ ICR27 = 31; /* USART (LIN, FIFO) 6 RX */
/* USART (LIN, FIFO) 6 TX */ /* USART (LIN, FIFO) 6 TX */
ICR28 = 31; /* USART (LIN, FIFO) 7 RX */ ICR28 = 31; /* USART (LIN, FIFO) 7 RX */
/* USART (LIN, FIFO) 7 TX */ /* USART (LIN, FIFO) 7 TX */
ICR29 = 31; /* I2C 0 / I2C 2 */ ICR29 = 31; /* I2C 0 / I2C 2 */
/* I2C 1 / I2C 3 */ /* I2C 1 / I2C 3 */
ICR30 = 31; /* USART (LIN, FIFO) 8 RX */ ICR30 = 31; /* USART (LIN, FIFO) 8 RX */
/* USART (LIN, FIFO) 8 TX */ /* USART (LIN, FIFO) 8 TX */
ICR31 = 31; /* USART (LIN, FIFO) 9 RX */ ICR31 = 31; /* USART (LIN, FIFO) 9 RX */
/* USART (LIN, FIFO) 9 TX */ /* USART (LIN, FIFO) 9 TX */
ICR32 = 31; /* USART (LIN, FIFO) 10 RX */ ICR32 = 31; /* USART (LIN, FIFO) 10 RX */
/* USART (LIN, FIFO) 10 TX */ /* USART (LIN, FIFO) 10 TX */
ICR33 = 31; /* USART (LIN, FIFO) 11 RX */ ICR33 = 31; /* USART (LIN, FIFO) 11 RX */
/* USART (LIN, FIFO) 11 TX */ /* USART (LIN, FIFO) 11 TX */
ICR34 = 31; /* USART (LIN, FIFO) 12 RX */ ICR34 = 31; /* USART (LIN, FIFO) 12 RX */
/* USART (LIN, FIFO) 12 TX */ /* USART (LIN, FIFO) 12 TX */
ICR35 = 31; /* USART (LIN, FIFO) 13 RX */ ICR35 = 31; /* USART (LIN, FIFO) 13 RX */
/* USART (LIN, FIFO) 13 TX */ /* USART (LIN, FIFO) 13 TX */
ICR36 = 31; /* USART (LIN, FIFO) 14 RX */ ICR36 = 31; /* USART (LIN, FIFO) 14 RX */
/* USART (LIN, FIFO) 14 TX */ /* USART (LIN, FIFO) 14 TX */
ICR37 = 31; /* USART (LIN, FIFO) 15 RX */ ICR37 = 31; /* USART (LIN, FIFO) 15 RX */
/* USART (LIN, FIFO) 15 TX */ /* USART (LIN, FIFO) 15 TX */
ICR38 = 31; /* Input Capture 0 */ ICR38 = 31; /* Input Capture 0 */
/* Input Capture 1 */ /* Input Capture 1 */
ICR39 = 31; /* Input Capture 2 */ ICR39 = 31; /* Input Capture 2 */
/* Input Capture 3 */ /* Input Capture 3 */
ICR40 = 31; /* Input Capture 4 */ ICR40 = 31; /* Input Capture 4 */
/* Input Capture 5 */ /* Input Capture 5 */
ICR41 = 31; /* Input Capture 6 */ ICR41 = 31; /* Input Capture 6 */
/* Input Capture 7 */ /* Input Capture 7 */
ICR42 = 31; /* Output Compare 0 */ ICR42 = 31; /* Output Compare 0 */
/* Output Compare 1 */ /* Output Compare 1 */
ICR43 = 31; /* Output Compare 2 */ ICR43 = 31; /* Output Compare 2 */
/* Output Compare 3 */ /* Output Compare 3 */
ICR44 = 31; /* Output Compare 4 */ ICR44 = 31; /* Output Compare 4 */
/* Output Compare 5 */ /* Output Compare 5 */
ICR45 = 31; /* Output Compare 6 */ ICR45 = 31; /* Output Compare 6 */
/* Output Compare 7 */ /* Output Compare 7 */
ICR46 = 31; /* Sound Generator */ ICR46 = 31; /* Sound Generator */
/* Phase Frequ. Modulator */ /* Phase Frequ. Modulator */
ICR47 = 31; /* System Reserved */ ICR47 = 31; /* System Reserved */
/* System Reserved */ /* System Reserved */
ICR48 = 31; /* Prog. Pulse Gen. 0 */ ICR48 = 31; /* Prog. Pulse Gen. 0 */
/* Prog. Pulse Gen. 1 */ /* Prog. Pulse Gen. 1 */
ICR49 = 31; /* Prog. Pulse Gen. 2 */ ICR49 = 31; /* Prog. Pulse Gen. 2 */
/* Prog. Pulse Gen. 3 */ /* Prog. Pulse Gen. 3 */
ICR50 = 31; /* Prog. Pulse Gen. 4 */ ICR50 = 31; /* Prog. Pulse Gen. 4 */
/* Prog. Pulse Gen. 5 */ /* Prog. Pulse Gen. 5 */
ICR51 = 31; /* Prog. Pulse Gen. 6 */ ICR51 = 31; /* Prog. Pulse Gen. 6 */
/* Prog. Pulse Gen. 7 */ /* Prog. Pulse Gen. 7 */
ICR52 = 31; /* Prog. Pulse Gen. 8 */ ICR52 = 31; /* Prog. Pulse Gen. 8 */
/* Prog. Pulse Gen. 9 */ /* Prog. Pulse Gen. 9 */
ICR53 = 31; /* Prog. Pulse Gen. 10 */ ICR53 = 31; /* Prog. Pulse Gen. 10 */
/* Prog. Pulse Gen. 11 */ /* Prog. Pulse Gen. 11 */
ICR54 = 31; /* Prog. Pulse Gen. 12 */ ICR54 = 31; /* Prog. Pulse Gen. 12 */
/* Prog. Pulse Gen. 13 */ /* Prog. Pulse Gen. 13 */
ICR55 = 31; /* Prog. Pulse Gen. 14 */ ICR55 = 31; /* Prog. Pulse Gen. 14 */
/* Prog. Pulse Gen. 15 */ /* Prog. Pulse Gen. 15 */
ICR56 = 31; /* Up/Down Counter 0 */ ICR56 = 31; /* Up/Down Counter 0 */
/* Up/Down Counter 1 */ /* Up/Down Counter 1 */
ICR57 = 31; /* Up/Down Counter 2 */ ICR57 = 31; /* Up/Down Counter 2 */
/* Up/Down Counter 3 */ /* Up/Down Counter 3 */
ICR58 = 31; /* Real Time Clock */ ICR58 = 31; /* Real Time Clock */
/* Calibration Unit */ /* Calibration Unit */
ICR59 = 31; /* A/D Converter 0 */ ICR59 = 31; /* A/D Converter 0 */
/* - */ /* - */
ICR60 = 31; /* Alarm Comperator 0 */ ICR60 = 31; /* Alarm Comperator 0 */
/* Alarm Comperator 1 */ /* Alarm Comperator 1 */
ICR61 = 31; /* Low Volage Detector */ ICR61 = 31; /* Low Volage Detector */
/* SMC Zero Point 0-5 */ /* SMC Zero Point 0-5 */
ICR62 = 31; /* Timebase Overflow */ ICR62 = 31; /* Timebase Overflow */
/* PLL Clock Gear */ /* PLL Clock Gear */
ICR63 = 31; /* DMA Controller */ ICR63 = 31; /* DMA Controller */
/* Main/Sub OSC stability wait */ /* Main/Sub OSC stability wait */
} }

7
Demo/MB91460_Softune/SRC/vectors.h
View file

@ -9,5 +9,10 @@
06.10.06 1.00 UMa Initial Version 06.10.06 1.00 UMa Initial Version
-----------------------------------------------------------------------------*/ -----------------------------------------------------------------------------*/
#ifndef VECTORS_H
#define VECTORS_H
void InitIrqLevels( void );
#endif
void InitIrqLevels(void);

6
Demo/MB91460_Softune/SRC/watchdog/watchdog.h
View file

@ -6,6 +6,10 @@
watchdog.h watchdog.h
- This file contains the defines and function declaration for hardware watchdog. - This file contains the defines and function declaration for hardware watchdog.
-------------------------------------------------------------------------*/ -------------------------------------------------------------------------*/
#ifndef WATCHDOG_H
#define WATCHDOG_H
/* /*
* Clear watchdog defines * Clear watchdog defines
*/ */
@ -44,3 +48,5 @@
void InitWatchdog (void); void InitWatchdog (void);
void vStartWatchdogTask(unsigned portSHORT); void vStartWatchdogTask(unsigned portSHORT);
#endif