mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 01:58:32 -04:00
Tidy up - spell check.
This commit is contained in:
Richard Barry
parent
5a418b56fa
commit
613c764189
8 changed files with 242 additions and 179 deletions
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@ -17,6 +17,7 @@
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#include "mb91467d.h"
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#include "watchdog.h"
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#include "FreeRTOSConfig.h"
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/*------------------------------------------------------------------------
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InitIrqLevels()
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@ -34,133 +35,133 @@ void InitIrqLevels(void)
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/* ICRxx */
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/* Softune Workbench Monitor Debugger is using ext int0 for abort function */
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/* ICR00 = 31; *//* External Interrupt 0 */
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/* External Interrupt 1 */
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ICR01 = 31; /* External Interrupt 2 */
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/* External Interrupt 3 */
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ICR02 = 31; /* External Interrupt 4 */
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/* External Interrupt 5 */
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ICR03 = 31; /* External Interrupt 6 */
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/* External Interrupt 7 */
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ICR04 = 31; /* External Interrupt 8 */
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/* External Interrupt 9 */
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ICR05 = 31; /* External Interrupt 10 */
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/* External Interrupt 11 */
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ICR06 = 31; /* External Interrupt 12 */
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/* External Interrupt 13 */
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ICR07 = 31; /* External Interrupt 14 */
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/* External Interrupt 15 */
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ICR08 = 30; /* Reload Timer 0 */
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/* Reload Timer 1 */
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ICR09 = 31; /* Reload Timer 2 */
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/* Reload Timer 3 */
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ICR10 = 31; /* Reload Timer 4 */
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/* Reload Timer 5 */
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ICR11 = 31; /* Reload Timer 6 */
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/* Reload Timer 7 */
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ICR12 = 31; /* Free Run Timer 0 */
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/* Free Run Timer 1 */
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ICR13 = 31; /* Free Run Timer 2 */
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/* Free Run Timer 3 */
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ICR14 = 31; /* Free Run Timer 4 */
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/* Free Run Timer 5 */
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ICR15 = 31; /* Free Run Timer 6 */
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/* Free Run Timer 7 */
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ICR16 = 31; /* CAN 0 */
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/* CAN 1 */
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ICR17 = 31; /* CAN 2 */
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/* CAN 3 */
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ICR18 = 31; /* CAN 4 */
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/* CAN 5 */
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ICR19 = 31; /* USART (LIN) 0 RX */
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/* USART (LIN) 0 TX */
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ICR20 = 31; /* USART (LIN) 1 RX */
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/* USART (LIN) 1 TX */
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ICR21 = 30; /* USART (LIN) 2 RX */
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/* USART (LIN) 2 TX */
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ICR22 = 31; /* USART (LIN) 3 RX */
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/* USART (LIN) 3 TX */
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ICR23 = 30; /* System Reserved */
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/* Delayed Interrupt */
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ICR24 = 31; /* System Reserved */
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/* System Reserved */
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ICR25 = 31; /* USART (LIN, FIFO) 4 RX */
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/* USART (LIN, FIFO) 4 TX */
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ICR26 = 30; /* USART (LIN, FIFO) 5 RX */
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/* USART (LIN, FIFO) 5 TX */
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ICR27 = 31; /* USART (LIN, FIFO) 6 RX */
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/* USART (LIN, FIFO) 6 TX */
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ICR28 = 31; /* USART (LIN, FIFO) 7 RX */
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/* USART (LIN, FIFO) 7 TX */
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ICR29 = 31; /* I2C 0 / I2C 2 */
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/* I2C 1 / I2C 3 */
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ICR30 = 31; /* USART (LIN, FIFO) 8 RX */
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/* USART (LIN, FIFO) 8 TX */
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ICR31 = 31; /* USART (LIN, FIFO) 9 RX */
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/* USART (LIN, FIFO) 9 TX */
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ICR32 = 31; /* USART (LIN, FIFO) 10 RX */
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/* USART (LIN, FIFO) 10 TX */
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ICR33 = 31; /* USART (LIN, FIFO) 11 RX */
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/* USART (LIN, FIFO) 11 TX */
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ICR34 = 31; /* USART (LIN, FIFO) 12 RX */
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/* USART (LIN, FIFO) 12 TX */
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ICR35 = 31; /* USART (LIN, FIFO) 13 RX */
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/* USART (LIN, FIFO) 13 TX */
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ICR36 = 31; /* USART (LIN, FIFO) 14 RX */
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/* USART (LIN, FIFO) 14 TX */
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ICR37 = 31; /* USART (LIN, FIFO) 15 RX */
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/* USART (LIN, FIFO) 15 TX */
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ICR38 = 31; /* Input Capture 0 */
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/* Input Capture 1 */
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ICR39 = 31; /* Input Capture 2 */
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/* Input Capture 3 */
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ICR40 = 31; /* Input Capture 4 */
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/* Input Capture 5 */
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ICR41 = 31; /* Input Capture 6 */
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/* Input Capture 7 */
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ICR42 = 31; /* Output Compare 0 */
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/* Output Compare 1 */
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ICR43 = 31; /* Output Compare 2 */
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/* Output Compare 3 */
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ICR44 = 31; /* Output Compare 4 */
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/* Output Compare 5 */
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ICR45 = 31; /* Output Compare 6 */
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/* Output Compare 7 */
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ICR46 = 31; /* Sound Generator */
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/* Phase Frequ. Modulator */
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ICR47 = 31; /* System Reserved */
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/* System Reserved */
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ICR48 = 31; /* Prog. Pulse Gen. 0 */
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/* Prog. Pulse Gen. 1 */
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ICR49 = 31; /* Prog. Pulse Gen. 2 */
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/* Prog. Pulse Gen. 3 */
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ICR50 = 31; /* Prog. Pulse Gen. 4 */
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/* Prog. Pulse Gen. 5 */
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ICR51 = 31; /* Prog. Pulse Gen. 6 */
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/* Prog. Pulse Gen. 7 */
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ICR52 = 31; /* Prog. Pulse Gen. 8 */
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/* Prog. Pulse Gen. 9 */
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ICR53 = 31; /* Prog. Pulse Gen. 10 */
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/* Prog. Pulse Gen. 11 */
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ICR54 = 31; /* Prog. Pulse Gen. 12 */
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/* Prog. Pulse Gen. 13 */
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ICR55 = 31; /* Prog. Pulse Gen. 14 */
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/* Prog. Pulse Gen. 15 */
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ICR56 = 31; /* Up/Down Counter 0 */
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/* Up/Down Counter 1 */
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ICR57 = 31; /* Up/Down Counter 2 */
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/* Up/Down Counter 3 */
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ICR58 = 31; /* Real Time Clock */
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/* Calibration Unit */
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ICR59 = 31; /* A/D Converter 0 */
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/* - */
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ICR60 = 31; /* Alarm Comperator 0 */
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/* Alarm Comperator 1 */
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ICR61 = 31; /* Low Volage Detector */
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/* SMC Zero Point 0-5 */
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ICR62 = 31; /* Timebase Overflow */
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/* PLL Clock Gear */
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ICR63 = 31; /* DMA Controller */
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/* Main/Sub OSC stability wait */
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/* External Interrupt 1 */
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ICR01 = 31; /* External Interrupt 2 */
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/* External Interrupt 3 */
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ICR02 = 31; /* External Interrupt 4 */
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/* External Interrupt 5 */
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ICR03 = 31; /* External Interrupt 6 */
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/* External Interrupt 7 */
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ICR04 = 31; /* External Interrupt 8 */
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/* External Interrupt 9 */
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ICR05 = 31; /* External Interrupt 10 */
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/* External Interrupt 11 */
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ICR06 = 31; /* External Interrupt 12 */
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/* External Interrupt 13 */
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ICR07 = 31; /* External Interrupt 14 */
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/* External Interrupt 15 */
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ICR08 = configKERNEL_INTERRUPT_PRIORITY; /* Reload Timer 0 */
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/* Reload Timer 1 */
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ICR09 = 31; /* Reload Timer 2 */
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/* Reload Timer 3 */
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ICR10 = 31; /* Reload Timer 4 */
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/* Reload Timer 5 */
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ICR11 = 31; /* Reload Timer 6 */
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/* Reload Timer 7 */
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ICR12 = 31; /* Free Run Timer 0 */
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/* Free Run Timer 1 */
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ICR13 = 31; /* Free Run Timer 2 */
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/* Free Run Timer 3 */
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ICR14 = 31; /* Free Run Timer 4 */
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/* Free Run Timer 5 */
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ICR15 = 31; /* Free Run Timer 6 */
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/* Free Run Timer 7 */
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ICR16 = 31; /* CAN 0 */
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/* CAN 1 */
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ICR17 = 31; /* CAN 2 */
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/* CAN 3 */
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ICR18 = 31; /* CAN 4 */
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/* CAN 5 */
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ICR19 = 31; /* USART (LIN) 0 RX */
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/* USART (LIN) 0 TX */
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ICR20 = 31; /* USART (LIN) 1 RX */
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/* USART (LIN) 1 TX */
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ICR21 = configKERNEL_INTERRUPT_PRIORITY; /* USART (LIN) 2 RX */
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/* USART (LIN) 2 TX */
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ICR22 = 31; /* USART (LIN) 3 RX */
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/* USART (LIN) 3 TX */
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ICR23 = configKERNEL_INTERRUPT_PRIORITY; /* System Reserved */
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/* Delayed Interrupt */
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ICR24 = 31; /* System Reserved */
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/* System Reserved */
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ICR25 = 31; /* USART (LIN, FIFO) 4 RX */
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/* USART (LIN, FIFO) 4 TX */
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ICR26 = configKERNEL_INTERRUPT_PRIORITY; /* USART (LIN, FIFO) 5 RX */
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/* USART (LIN, FIFO) 5 TX */
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ICR27 = 31; /* USART (LIN, FIFO) 6 RX */
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/* USART (LIN, FIFO) 6 TX */
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ICR28 = 31; /* USART (LIN, FIFO) 7 RX */
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/* USART (LIN, FIFO) 7 TX */
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ICR29 = 31; /* I2C 0 / I2C 2 */
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/* I2C 1 / I2C 3 */
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ICR30 = 31; /* USART (LIN, FIFO) 8 RX */
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/* USART (LIN, FIFO) 8 TX */
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ICR31 = 31; /* USART (LIN, FIFO) 9 RX */
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/* USART (LIN, FIFO) 9 TX */
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ICR32 = 31; /* USART (LIN, FIFO) 10 RX */
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/* USART (LIN, FIFO) 10 TX */
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ICR33 = 31; /* USART (LIN, FIFO) 11 RX */
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/* USART (LIN, FIFO) 11 TX */
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ICR34 = 31; /* USART (LIN, FIFO) 12 RX */
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/* USART (LIN, FIFO) 12 TX */
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ICR35 = 31; /* USART (LIN, FIFO) 13 RX */
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/* USART (LIN, FIFO) 13 TX */
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ICR36 = 31; /* USART (LIN, FIFO) 14 RX */
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/* USART (LIN, FIFO) 14 TX */
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ICR37 = 31; /* USART (LIN, FIFO) 15 RX */
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/* USART (LIN, FIFO) 15 TX */
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ICR38 = 31; /* Input Capture 0 */
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/* Input Capture 1 */
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ICR39 = 31; /* Input Capture 2 */
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/* Input Capture 3 */
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ICR40 = 31; /* Input Capture 4 */
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/* Input Capture 5 */
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ICR41 = 31; /* Input Capture 6 */
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/* Input Capture 7 */
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ICR42 = 31; /* Output Compare 0 */
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/* Output Compare 1 */
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ICR43 = 31; /* Output Compare 2 */
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/* Output Compare 3 */
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ICR44 = 31; /* Output Compare 4 */
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/* Output Compare 5 */
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ICR45 = 31; /* Output Compare 6 */
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/* Output Compare 7 */
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ICR46 = 31; /* Sound Generator */
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/* Phase Frequ. Modulator */
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ICR47 = 31; /* System Reserved */
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/* System Reserved */
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ICR48 = 31; /* Prog. Pulse Gen. 0 */
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/* Prog. Pulse Gen. 1 */
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ICR49 = 31; /* Prog. Pulse Gen. 2 */
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/* Prog. Pulse Gen. 3 */
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ICR50 = 31; /* Prog. Pulse Gen. 4 */
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/* Prog. Pulse Gen. 5 */
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ICR51 = 31; /* Prog. Pulse Gen. 6 */
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/* Prog. Pulse Gen. 7 */
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ICR52 = 31; /* Prog. Pulse Gen. 8 */
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/* Prog. Pulse Gen. 9 */
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ICR53 = 31; /* Prog. Pulse Gen. 10 */
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/* Prog. Pulse Gen. 11 */
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ICR54 = 31; /* Prog. Pulse Gen. 12 */
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/* Prog. Pulse Gen. 13 */
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ICR55 = 31; /* Prog. Pulse Gen. 14 */
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/* Prog. Pulse Gen. 15 */
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ICR56 = 31; /* Up/Down Counter 0 */
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/* Up/Down Counter 1 */
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ICR57 = 31; /* Up/Down Counter 2 */
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/* Up/Down Counter 3 */
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ICR58 = 31; /* Real Time Clock */
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/* Calibration Unit */
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ICR59 = 31; /* A/D Converter 0 */
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/* - */
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ICR60 = 31; /* Alarm Comperator 0 */
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/* Alarm Comperator 1 */
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ICR61 = 31; /* Low Volage Detector */
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/* SMC Zero Point 0-5 */
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ICR62 = 31; /* Timebase Overflow */
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/* PLL Clock Gear */
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ICR63 = 31; /* DMA Controller */
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/* Main/Sub OSC stability wait */
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}
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