mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-11-03 18:22:45 -05:00
Add interrupt nesting support, cache setup and reg test tasks.
This commit is contained in:
Richard Barry
parent
a943ccd85a
commit
60da4247dd
2 changed files with 188 additions and 11 deletions
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@ -31,6 +31,8 @@ OBJS = $(OUTPUT_DIR)/portasm.o \
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$(OUTPUT_DIR)/tasks.o \
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$(OUTPUT_DIR)/queue.o \
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$(OUTPUT_DIR)/heap_2.o \
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$(OUTPUT_DIR)/IntQueueTimer.o \
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$(OUTPUT_DIR)/IntQueue.o \
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$(OUTPUT_DIR)/FreeRTOS_Tick_Setup.o
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C_DEPS = $(OBJS:.o=.d)
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@ -44,6 +46,7 @@ CFLAGS= -I"$(FREERTOS_SOURCE_DIR)/include" \
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-I. \
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-D COLDFIRE_V2_GCC \
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-O0 \
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-fno-strict-aliasing \
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-g3 \
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-Wall \
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-Wextra \
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@ -124,9 +124,11 @@ static void prvSetupHardware( void );
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* file.
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*/
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static void prvCheckTask( void *pvParameters );
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static void vRegTest1Task( void *pvParameters );
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static void vRegTest2Task( void *pvParameters );
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/*-----------------------------------------------------------*/
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static volatile unsigned portLONG ulRegTest1Counter = 0, ulRegTest2Counter = 0;
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int main( void )
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{
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@ -143,6 +145,10 @@ int main( void )
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vStartQueuePeekTasks();
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vStartRecursiveMutexTasks();
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vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
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vStartInterruptQueueTasks();
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xTaskCreate( vRegTest1Task, ( signed portCHAR * ) "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
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xTaskCreate( vRegTest2Task, ( signed portCHAR * ) "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
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/* Create the check task. */
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xTaskCreate( prvCheckTask, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
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@ -163,7 +169,7 @@ int main( void )
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static void prvCheckTask( void *pvParameters )
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{
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unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0;
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unsigned ulTicksToWait = mainNO_ERROR_PERIOD, ulError = 0, ulLastRegTest1Count = 0, ulLastRegTest2Count = 0;
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portTickType xLastExecutionTime;
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( void ) pvParameters;
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@ -182,43 +188,70 @@ portTickType xLastExecutionTime;
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{
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ulError |= 0x01UL;
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}
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else if( xAreQueuePeekTasksStillRunning() != pdTRUE )
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if( xAreQueuePeekTasksStillRunning() != pdTRUE )
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{
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ulError |= 0x02UL;
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}
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else if( xAreBlockingQueuesStillRunning() != pdTRUE )
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if( xAreBlockingQueuesStillRunning() != pdTRUE )
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{
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ulError |= 0x04UL;
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}
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else if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
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if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
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{
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ulError |= 0x10UL;
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}
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else if( xAreSemaphoreTasksStillRunning() != pdTRUE )
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if( xAreSemaphoreTasksStillRunning() != pdTRUE )
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{
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ulError |= 0x20UL;
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}
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else if( xArePollingQueuesStillRunning() != pdTRUE )
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if( xArePollingQueuesStillRunning() != pdTRUE )
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{
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ulError |= 0x40UL;
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}
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else if( xIsCreateTaskStillRunning() != pdTRUE )
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if( xIsCreateTaskStillRunning() != pdTRUE )
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{
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ulError |= 0x80UL;
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}
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else if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
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if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
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{
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ulError |= 0x100UL;
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}
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else if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
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if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
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{
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ulError |= 0x200UL;
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}
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else if( xAreComTestTasksStillRunning() != pdTRUE )
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if( xAreComTestTasksStillRunning() != pdTRUE )
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{
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ulError |= 0x400UL;
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}
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if( xAreIntQueueTasksStillRunning() != pdTRUE )
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{
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ulError |= 0x800UL;
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}
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if( ulLastRegTest1Count == ulRegTest1Counter )
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{
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ulError |= 0x1000UL;
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}
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if( ulLastRegTest2Count == ulRegTest2Counter )
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{
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ulError |= 0x1000UL;
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}
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ulLastRegTest1Count = ulRegTest1Counter;
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ulLastRegTest2Count = ulRegTest2Counter;
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if( ulError != 0 )
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{
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ulTicksToWait = mainERROR_PERIOD;
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@ -231,6 +264,11 @@ portTickType xLastExecutionTime;
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void prvSetupHardware( void )
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{
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extern void mcf5xxx_wr_cacr( unsigned portLONG );
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/* Enable the cache. */
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mcf5xxx_wr_cacr( MCF5XXX_CACR_CENB | MCF5XXX_CACR_CINV | MCF5XXX_CACR_DISD | MCF5XXX_CACR_CEIB | MCF5XXX_CACR_CLNF_00 );
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/* Multiply 8Mhz reference crystal by 8 to achieve system clock of 64Mhz. */
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MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD( 2 );
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@ -251,5 +289,141 @@ void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTask
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for( ;; );
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}
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/*-----------------------------------------------------------*/
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static void vRegTest1Task( void *pvParameters )
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{
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( void ) pvParameters;
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asm volatile ( "reg_test_1_start: \n\t"
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" moveq #1, %d0 \n\t"
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" moveq #2, %d1 \n\t"
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" moveq #3, %d2 \n\t"
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" moveq #4, %d3 \n\t"
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" moveq #5, %d4 \n\t"
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" moveq #6, %d5 \n\t"
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" moveq #7, %d6 \n\t"
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" moveq #8, %d7 \n\t"
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" move #9, %a0 \n\t"
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" move #10, %a1 \n\t"
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" move #11, %a2 \n\t"
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" move #12, %a3 \n\t"
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" move #13, %a4 \n\t"
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" move #14, %a5 \n\t"
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" move #15, %a6 \n\t"
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" \n\t"
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" cmpi.l #1, %d0 \n\t"
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" bne reg_test_1_error \n\t"
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" cmpi.l #2, %d1 \n\t"
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" bne reg_test_1_error \n\t"
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" cmpi.l #3, %d2 \n\t"
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" bne reg_test_1_error \n\t"
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" cmpi.l #4, %d3 \n\t"
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" bne reg_test_1_error \n\t"
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" cmpi.l #5, %d4 \n\t"
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" bne reg_test_1_error \n\t"
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" cmpi.l #6, %d5 \n\t"
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" bne reg_test_1_error \n\t"
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" cmpi.l #7, %d6 \n\t"
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" bne reg_test_1_error \n\t"
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" cmpi.l #8, %d7 \n\t"
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" bne reg_test_1_error \n\t"
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" move %a0, %d0 \n\t"
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" cmpi.l #9, %d0 \n\t"
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" bne reg_test_1_error \n\t"
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" move %a1, %d0 \n\t"
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" cmpi.l #10, %d0 \n\t"
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" bne reg_test_1_error \n\t"
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" move %a2, %d0 \n\t"
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" cmpi.l #11, %d0 \n\t"
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" bne reg_test_1_error \n\t"
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" move %a3, %d0 \n\t"
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" cmpi.l #12, %d0 \n\t"
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" bne reg_test_1_error \n\t"
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" move %a4, %d0 \n\t"
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" cmpi.l #13, %d0 \n\t"
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" bne reg_test_1_error \n\t"
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" move %a5, %d0 \n\t"
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" cmpi.l #14, %d0 \n\t"
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" bne reg_test_1_error \n\t"
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" move %a6, %d0 \n\t"
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" cmpi.l #15, %d0 \n\t"
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" bne reg_test_1_error \n\t"
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" movel ulRegTest1Counter, %d0 \n\t"
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" addql #1, %d0 \n\t"
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" movel %d0, ulRegTest1Counter \n\t"
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" bra reg_test_1_start \n\t"
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"reg_test_1_error: \n\t"
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" bra reg_test_1_error \n\t"
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);
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}
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/*-----------------------------------------------------------*/
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static void vRegTest2Task( void *pvParameters )
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{
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( void ) pvParameters;
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asm volatile ( "reg_test_2_start: \n\t"
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" moveq #10, %d0 \n\t"
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" moveq #20, %d1 \n\t"
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" moveq #30, %d2 \n\t"
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" moveq #40, %d3 \n\t"
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" moveq #50, %d4 \n\t"
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" moveq #60, %d5 \n\t"
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" moveq #70, %d6 \n\t"
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" moveq #80, %d7 \n\t"
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" move #90, %a0 \n\t"
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" move #100, %a1 \n\t"
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" move #110, %a2 \n\t"
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" move #120, %a3 \n\t"
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" move #130, %a4 \n\t"
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" move #140, %a5 \n\t"
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" move #150, %a6 \n\t"
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" \n\t"
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" cmpi.l #10, %d0 \n\t"
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" bne reg_test_2_error \n\t"
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" cmpi.l #20, %d1 \n\t"
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" bne reg_test_2_error \n\t"
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" cmpi.l #30, %d2 \n\t"
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" bne reg_test_2_error \n\t"
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" cmpi.l #40, %d3 \n\t"
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" bne reg_test_2_error \n\t"
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" cmpi.l #50, %d4 \n\t"
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" bne reg_test_2_error \n\t"
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" cmpi.l #60, %d5 \n\t"
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" bne reg_test_2_error \n\t"
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" cmpi.l #70, %d6 \n\t"
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" bne reg_test_2_error \n\t"
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" cmpi.l #80, %d7 \n\t"
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" bne reg_test_2_error \n\t"
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" move %a0, %d0 \n\t"
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" cmpi.l #90, %d0 \n\t"
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" bne reg_test_2_error \n\t"
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" move %a1, %d0 \n\t"
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" cmpi.l #100, %d0 \n\t"
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" bne reg_test_2_error \n\t"
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" move %a2, %d0 \n\t"
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" cmpi.l #110, %d0 \n\t"
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" bne reg_test_2_error \n\t"
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" move %a3, %d0 \n\t"
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" cmpi.l #120, %d0 \n\t"
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" bne reg_test_2_error \n\t"
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" move %a4, %d0 \n\t"
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" cmpi.l #130, %d0 \n\t"
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" bne reg_test_2_error \n\t"
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" move %a5, %d0 \n\t"
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" cmpi.l #140, %d0 \n\t"
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" bne reg_test_2_error \n\t"
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" move %a6, %d0 \n\t"
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" cmpi.l #150, %d0 \n\t"
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" bne reg_test_2_error \n\t"
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" movel ulRegTest1Counter, %d0 \n\t"
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" addql #1, %d0 \n\t"
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" movel %d0, ulRegTest2Counter \n\t"
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" bra reg_test_2_start \n\t"
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"reg_test_2_error: \n\t"
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" bra reg_test_2_error \n\t"
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);
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}
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/*-----------------------------------------------------------*/
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