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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
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Richard Barry
parent
911a1de273
commit
60b133b2c6
6 changed files with 195 additions and 149 deletions
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@ -25,6 +25,15 @@
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* 1 tab == 4 spaces!
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*/
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define portWORD_SIZE 8
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#elif __riscv_xlen == 32
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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@ -42,7 +51,7 @@
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* regiters.
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* registers.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
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@ -67,27 +76,6 @@ definitions. */
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#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_port_specific_extensions.h header file.
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#endif
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#ifndef portasmSAVE_ADDITIONAL_REGISTERS
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/* portasmSAVE_ADDITIONAL_REGISTERS is not defined so assume no additional
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registers need to be saved. */
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#define portasmSAVE_ADDITIONAL_REGISTERS
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#endif
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#ifndef portasmRESTORE_ADDITIONAL_REGISTERS
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/* portasmRESTORE_ADDITIONAL_REGISTERS is not defined so assume no
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additional registers need to be restored. */
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#define portasmRESTORE_ADDITIONAL_REGISTERS
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#endif
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define portWORD_SIZE 8
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#elif __riscv_xlen == 32
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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/* Only the standard core registers are stored by default. Any additional
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registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
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portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
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@ -97,6 +85,7 @@ at the top of this file. */
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.global xPortStartFirstTask
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.global vFreeRTOSPortTrapHandler
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.global pxPortInitialiseStack
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.extern pxCurrentTCB
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.extern ulPortTrapHandler
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.extern vTaskSwitchContext
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@ -105,11 +94,11 @@ at the top of this file. */
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.extern pullNextTime
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.extern ulTimerIncrementsForOneTick
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.extern xISRStackTop
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.extern vPortHandleInterrupt
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/*-----------------------------------------------------------*/
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.align 16
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.align 8
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.func
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vFreeRTOSPortTrapHandler:
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addi sp, sp, -portCONTEXT_SIZE
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sw x1, 1 * portWORD_SIZE( sp )
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@ -141,11 +130,11 @@ vFreeRTOSPortTrapHandler:
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sw x30, 27 * portWORD_SIZE( sp )
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sw x31, 28 * portWORD_SIZE( sp )
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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csrr t0, mstatus /* Required for MPIE bit. */
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sw t0, 29 * portWORD_SIZE( sp )
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp to first TCB member. */
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@ -217,16 +206,16 @@ processed_source:
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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/* Load mret with the address of the next task. */
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/* Load mret with the address of the next instruction in the task to run next. */
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lw t0, 0( sp )
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csrw mepc, t0
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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/* Load mstatus with the interrupt enable bits used by the task. */
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lw t0, 29 * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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lw x1, 1 * portWORD_SIZE( sp )
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lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
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lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
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@ -255,12 +244,14 @@ processed_source:
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lw x29, 26 * portWORD_SIZE( sp ) /* t4 */
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lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
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lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
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addi sp, sp, portCONTEXT_SIZE
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addi sp, sp, portCONTEXT_SIZE
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mret
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.endfunc
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/*-----------------------------------------------------------*/
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.align 16
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.align 8
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.func
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xPortStartFirstTask:
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#if( portasmHAS_CLINT != 0 )
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@ -275,6 +266,12 @@ xPortStartFirstTask:
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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lw t0, 29 * portWORD_SIZE( sp ) /* mstatus */
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csrrw x0, mstatus, t0 /* Interrupts enabled from here! */
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lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
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lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
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lw x7, 4 * portWORD_SIZE( sp ) /* t2 */
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@ -303,8 +300,98 @@ xPortStartFirstTask:
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lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
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lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
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addi sp, sp, portCONTEXT_SIZE
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csrs mstatus, 8 /* Enable machine interrupts. */
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ret
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.endfunc
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/*-----------------------------------------------------------*/
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/*
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* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
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* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
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* for the function is as per the other ports:
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* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
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*
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* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
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* a1, and pvParameters in a2. The new top of stack is passed out in a0.
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*
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* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
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* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
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*
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* Register ABI Name Description Saver
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* x0 zero Hard-wired zero -
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* x1 ra Return address Caller
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* x2 sp Stack pointer Callee
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* x3 gp Global pointer -
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* x4 tp Thread pointer -
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* x5-7 t0-2 Temporaries Caller
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* x8 s0/fp Saved register/Frame pointer Callee
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* x9 s1 Saved register Callee
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* x10-11 a0-1 Function Arguments/return values Caller
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* x12-17 a2-7 Function arguments Caller
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* x18-27 s2-11 Saved registers Callee
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* x28-31 t3-6 Temporaries Caller
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*
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* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
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* where the global and thread pointers are currently assumed to be constant so
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* are not saved:
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*
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* mstatus
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* x31
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* x30
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* x29
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* x28
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* x27
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* x26
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* x25
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* x24
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* x23
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* x22
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* x21
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* x20
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* x19
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* x18
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* x17
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* x16
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* x15
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* x14
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* x13
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* x12
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* x11
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* pvParameters
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* x9
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* x8
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* x7
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* x6
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* x5
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* portTASK_RETURN_ADDRESS
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* pxCode
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*/
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.align 8
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.func
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pxPortInitialiseStack:
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addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
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chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
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beq t0, x0, standard_stack_frame /* No more chip specific registers to save. */
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addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
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sw x0, 0(a0) /* Give the chip specific register an initial value of zero. */
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addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
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j chip_specific_stack_frame /* Until no more chip specific registers. */
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standard_stack_frame: /* Now create the stack frame for the standard registers. */
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csrr t0, mstatus /* Obtain current mstatus value. */
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addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
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slli t1, t1, 4
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or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
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addi a0, a0, -portWORD_SIZE
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sw t0, 0(a0) /* mstatus onto the stack. */
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addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
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sw a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
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addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
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sw x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
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addi a0, a0, -portWORD_SIZE
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sw a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
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ret
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.endfunc
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/*-----------------------------------------------------------*/
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