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CI-CD Updates (#768)
* Use new version of CI-CD Actions * Use cSpell spell check, and use ubuntu-20.04 for formatting check * Format and spell check all files in the portable directory * Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /* * Use checkout@v3 instead of checkout@v2 on all jobs ---------
This commit is contained in:
Soren Ptak
GitHub
parent
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485 changed files with 108790 additions and 107581 deletions
162
portable/ThirdParty/GCC/Xtensa_ESP32/port.c
vendored
162
portable/ThirdParty/GCC/Xtensa_ESP32/port.c
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@ -6,6 +6,7 @@
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*
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* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
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*/
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/*
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* FreeRTOS Kernel V10.4.3
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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@ -33,6 +34,7 @@
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
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*
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@ -63,22 +65,22 @@
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#include "xtensa_rtos.h"
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#include "esp_idf_version.h"
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#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
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#include "rom/ets_sys.h"
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#include "esp_panic.h"
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#include "esp_crosscore_int.h"
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#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
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#include "rom/ets_sys.h"
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#include "esp_panic.h"
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#include "esp_crosscore_int.h"
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#else
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h"
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#endif
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#include "esp_private/panic_reason.h"
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#include "esp_debug_helpers.h"
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#include "esp_private/crosscore_int.h"
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#include "esp_log.h"
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "esp32s2/rom/ets_sys.h"
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#elif CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/ets_sys.h"
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#endif
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#include "esp_private/panic_reason.h"
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#include "esp_debug_helpers.h"
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#include "esp_private/crosscore_int.h"
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#include "esp_log.h"
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#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
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#include "soc/cpu.h"
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@ -94,12 +96,12 @@
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/* Defined in xtensa_context.S */
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extern void _xt_coproc_init( void );
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_Static_assert(tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value");
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_Static_assert( tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value" );
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/*-----------------------------------------------------------*/
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extern volatile int port_xSchedulerRunning[portNUM_PROCESSORS];
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unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
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extern volatile int port_xSchedulerRunning[ portNUM_PROCESSORS ];
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unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
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/*-----------------------------------------------------------*/
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@ -153,15 +155,15 @@ void _xt_user_exit( void );
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thread_local_sz = ALIGNUP( 0x10, thread_local_sz );
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/* Initialize task's stack so that we have the following structure at the top:
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----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES----------
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task stack | interrupt stack frame | thread local vars | co-processor save area |
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----------------------------------------------------------------------------------
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SP pxTopOfStack
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All parts are aligned to 16 byte boundary.
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*/
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*
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* ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES----------
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* task stack | interrupt stack frame | thread local vars | co-processor save area |
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* ----------------------------------------------------------------------------------
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| SP pxTopOfStack
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| All parts are aligned to 16 byte boundary.
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*/
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/* Create interrupt stack frame aligned to 16 byte boundary */
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sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ ) & ~0xf );
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@ -309,7 +311,7 @@ void vPortYieldOtherCore( BaseType_t coreid )
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uint32_t usStackDepth )
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{
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#if XCHAL_CP_NUM > 0
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ));
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ) );
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
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@ -351,27 +353,29 @@ BaseType_t IRAM_ATTR xPortInterruptedFromISRContext()
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return( port_interruptNesting[ xPortGetCoreID() ] != 0 );
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}
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void IRAM_ATTR vPortEvaluateYieldFromISR( int argc, ... )
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void IRAM_ATTR vPortEvaluateYieldFromISR( int argc,
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... )
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{
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BaseType_t xYield;
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va_list ap;
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va_start( ap, argc );
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if( argc )
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{
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xYield = ( BaseType_t )va_arg( ap, int );
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xYield = ( BaseType_t ) va_arg( ap, int );
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va_end( ap );
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}
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else
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{
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//it is a empty parameter vPortYieldFromISR macro call:
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/*it is a empty parameter vPortYieldFromISR macro call: */
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va_end( ap );
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traceISR_EXIT_TO_SCHEDULER();
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_frxt_setup_switch();
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return;
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}
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//Yield exists, so need evaluate it first then switch:
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/*Yield exists, so need evaluate it first then switch: */
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if( xYield == pdTRUE )
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{
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traceISR_EXIT_TO_SCHEDULER();
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@ -477,8 +481,8 @@ void vPortCPUInitializeMutex( portMUX_TYPE * mux )
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}
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#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
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#define STACK_WATCH_AREA_SIZE ( 32 )
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#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 )
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#define STACK_WATCH_AREA_SIZE ( 32 )
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#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 )
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void vPortSetStackWatchpoint( void * pxStackStart )
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{
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@ -491,48 +495,48 @@ void vPortSetStackWatchpoint( void * pxStackStart )
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int addr = ( int ) pxStackStart;
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addr = ( addr + 31 ) & ( ~31 );
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esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, (char*)addr, 32, ESP_WATCHPOINT_STORE );
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esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, ( char * ) addr, 32, ESP_WATCHPOINT_STORE );
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}
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#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
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#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
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#if defined( CONFIG_SPIRAM_SUPPORT )
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#if defined( CONFIG_SPIRAM_SUPPORT )
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/*
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* Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it.
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*/
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static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
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static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
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void uxPortCompareSetExtram( volatile uint32_t * addr,
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uint32_t compare,
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uint32_t * set )
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{
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uint32_t prev;
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uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR();
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#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
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vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
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#else
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vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
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#endif
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prev = *addr;
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if( prev == compare )
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void uxPortCompareSetExtram( volatile uint32_t * addr,
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uint32_t compare,
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uint32_t * set )
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{
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*addr = *set;
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uint32_t prev;
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uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR();
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#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
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vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
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#else
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vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
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#endif
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prev = *addr;
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if( prev == compare )
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{
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*addr = *set;
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}
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*set = prev;
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#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
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vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
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#else
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vPortCPUReleaseMutexIntsDisabled( &extram_mux );
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#endif
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portCLEAR_INTERRUPT_MASK_FROM_ISR( oldlevel );
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}
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*set = prev;
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#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
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vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
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#else
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vPortCPUReleaseMutexIntsDisabled( &extram_mux );
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#endif
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portCLEAR_INTERRUPT_MASK_FROM_ISR(oldlevel);
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}
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#endif //defined(CONFIG_SPIRAM_SUPPORT)
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#endif //defined(CONFIG_SPIRAM_SUPPORT)
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#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
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@ -542,27 +546,27 @@ uint32_t xPortGetTickRateHz( void )
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return ( uint32_t ) configTICK_RATE_HZ;
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}
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// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
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// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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// should mirror each other's values.
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//
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// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE.
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/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */
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/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */
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/* should mirror each other's values. */
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/* */
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/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */
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#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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#error "FreeRTOS and system configuration mismatch regarding the use of multiple cores."
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#endif
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extern void esp_startup_start_app_common(void);
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extern void esp_startup_start_app_common( void );
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void esp_startup_start_app(void)
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void esp_startup_start_app( void )
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{
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#if !CONFIG_ESP_INT_WDT
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
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#endif
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#endif
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#if !CONFIG_ESP_INT_WDT
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#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
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assert( !soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!" );
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#endif
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#endif
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esp_startup_start_app_common();
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ESP_LOGI("cpu_start", "Starting scheduler on PRO CPU.");
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ESP_LOGI( "cpu_start", "Starting scheduler on PRO CPU." );
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vTaskStartScheduler();
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}
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