mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-20 01:58:32 -04:00
CI-CD Updates (#768)
* Use new version of CI-CD Actions * Use cSpell spell check, and use ubuntu-20.04 for formatting check * Format and spell check all files in the portable directory * Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /* * Use checkout@v3 instead of checkout@v2 on all jobs ---------
This commit is contained in:
Soren Ptak
GitHub
parent
d6bccb1f4c
commit
5fb9b50da8
485 changed files with 108790 additions and 107581 deletions
|
|
@ -5,6 +5,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
|
|
@ -39,29 +40,30 @@
|
|||
#include "sdkconfig.h"
|
||||
|
||||
/* enable use of optimized task selection by the scheduler */
|
||||
#if defined (CONFIG_FREERTOS_OPTIMIZED_SCHEDULER) && !defined(configUSE_PORT_OPTIMISED_TASK_SELECTION)
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#if defined( CONFIG_FREERTOS_OPTIMIZED_SCHEDULER ) && !defined( configUSE_PORT_OPTIMISED_TASK_SELECTION )
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#define XT_USE_THREAD_SAFE_CLIB 0
|
||||
#define XT_USE_THREAD_SAFE_CLIB 0
|
||||
#undef XT_USE_SWPRI
|
||||
|
||||
#if CONFIG_FREERTOS_CORETIMER_0
|
||||
#define XT_TIMER_INDEX 0
|
||||
#define XT_TIMER_INDEX 0
|
||||
#elif CONFIG_FREERTOS_CORETIMER_1
|
||||
#define XT_TIMER_INDEX 1
|
||||
#define XT_TIMER_INDEX 1
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
/**
|
||||
* This function is defined to provide a deprecation warning whenever
|
||||
* XT_CLOCK_FREQ macro is used.
|
||||
* Update the code to use esp_clk_cpu_freq function instead.
|
||||
* @return current CPU clock frequency, in Hz
|
||||
*/
|
||||
int xt_clock_freq(void) __attribute__((deprecated));
|
||||
int xt_clock_freq( void ) __attribute__( ( deprecated ) );
|
||||
|
||||
#define XT_CLOCK_FREQ (xt_clock_freq())
|
||||
#define XT_CLOCK_FREQ ( xt_clock_freq() )
|
||||
|
||||
#endif // __ASSEMBLER__
|
||||
|
||||
|
|
@ -70,47 +72,50 @@ int xt_clock_freq(void) __attribute__((deprecated));
|
|||
|
||||
/* configASSERT behaviour */
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <assert.h>
|
||||
#include "esp_rom_sys.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/ets_sys.h"
|
||||
#endif
|
||||
#include <assert.h>
|
||||
#include "esp_rom_sys.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h" /* will be removed in idf v5.0 */
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/ets_sys.h"
|
||||
#endif
|
||||
#endif // __ASSEMBLER__
|
||||
|
||||
// If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro
|
||||
// configASSERT_DEFINED remains unset (meaning some warnings are avoided)
|
||||
/* If CONFIG_FREERTOS_ASSERT_DISABLE is set then configASSERT is defined empty later in FreeRTOS.h and the macro */
|
||||
/* configASSERT_DEFINED remains unset (meaning some warnings are avoided) */
|
||||
#ifdef configASSERT
|
||||
#undef configASSERT
|
||||
#if defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE)
|
||||
#define configASSERT(a) if (unlikely(!(a))) { \
|
||||
esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \
|
||||
__FUNCTION__); \
|
||||
#undef configASSERT
|
||||
#if defined( CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE )
|
||||
#define configASSERT( a ) \
|
||||
if( unlikely( !( a ) ) ) { \
|
||||
esp_rom_printf( "%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \
|
||||
__FUNCTION__ ); \
|
||||
}
|
||||
#elif defined(CONFIG_FREERTOS_ASSERT_FAIL_ABORT)
|
||||
#define configASSERT(a) assert(a)
|
||||
#endif
|
||||
#endif
|
||||
#elif defined( CONFIG_FREERTOS_ASSERT_FAIL_ABORT )
|
||||
#define configASSERT( a ) assert( a )
|
||||
#endif
|
||||
#endif /* ifdef configASSERT */
|
||||
|
||||
#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION
|
||||
#define UNTESTED_FUNCTION() { esp_rom_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0)
|
||||
#define UNTESTED_FUNCTION() \
|
||||
{ esp_rom_printf( "Untested FreeRTOS function %s\r\n", __FUNCTION__ ); configASSERT( false ); } \
|
||||
while( 0 )
|
||||
#else
|
||||
#define UNTESTED_FUNCTION()
|
||||
#define UNTESTED_FUNCTION()
|
||||
#endif
|
||||
|
||||
#define configXT_BOARD 1 /* Board mode */
|
||||
#define configXT_SIMULATOR 0
|
||||
#define configXT_BOARD 1 /* Board mode */
|
||||
#define configXT_SIMULATOR 0
|
||||
|
||||
/* The maximum interrupt priority from which FreeRTOS.org API functions can
|
||||
be called. Only API functions that end in ...FromISR() can be used within
|
||||
interrupts. */
|
||||
* be called. Only API functions that end in ...FromISR() can be used within
|
||||
* interrupts. */
|
||||
#define configMAX_SYSCALL_INTERRUPT_PRIORITY XCHAL_EXCM_LEVEL
|
||||
|
||||
/* Stack alignment, architecture specifc. Must be a power of two. */
|
||||
#define configSTACK_ALIGNMENT 16
|
||||
#define configSTACK_ALIGNMENT 16
|
||||
|
||||
|
||||
/* The Xtensa port uses a separate interrupt stack. Adjust the stack size
|
||||
|
|
@ -119,16 +124,16 @@ int xt_clock_freq(void) __attribute__((deprecated));
|
|||
* the stack for the 2nd CPU will be calculated using configISR_STACK_SIZE.
|
||||
*/
|
||||
#ifndef configISR_STACK_SIZE
|
||||
#define configISR_STACK_SIZE ((CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1) & (~(configSTACK_ALIGNMENT - 1)))
|
||||
#define configISR_STACK_SIZE ( ( CONFIG_FREERTOS_ISR_STACKSIZE + configSTACK_ALIGNMENT - 1 ) & ( ~( configSTACK_ALIGNMENT - 1 ) ) )
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#if CONFIG_APPTRACE_SV_ENABLE
|
||||
extern uint32_t port_switch_flag[];
|
||||
#define os_task_switch_is_pended(_cpu_) (port_switch_flag[_cpu_])
|
||||
#else
|
||||
#define os_task_switch_is_pended(_cpu_) (false)
|
||||
#endif
|
||||
#if CONFIG_APPTRACE_SV_ENABLE
|
||||
extern uint32_t port_switch_flag[];
|
||||
#define os_task_switch_is_pended( _cpu_ ) ( port_switch_flag[ _cpu_ ] )
|
||||
#else
|
||||
#define os_task_switch_is_pended( _cpu_ ) ( false )
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif // FREERTOS_CONFIG_XTENSA_H
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
/**
|
||||
* @brief Set up the SysTick interrupt
|
||||
*/
|
||||
void vPortSetupTimer(void);
|
||||
void vPortSetupTimer( void );
|
||||
|
||||
/* *INDENT-OFF* */
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
|
|
@ -75,23 +76,23 @@
|
|||
#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
|
||||
#include <xtensa/xtruntime.h>
|
||||
#include "soc/spinlock.h"
|
||||
#include "esp_timer.h" /* required for FreeRTOS run time stats */
|
||||
#include "esp_timer.h" /* required for FreeRTOS run time stats */
|
||||
#include "esp_system.h"
|
||||
#include "esp_idf_version.h"
|
||||
#include "esp_heap_caps.h"
|
||||
|
||||
/* TODO: Resolve build warnings generated due to this header inclusion */
|
||||
/* TODO: Resolve build warnings generated due to this header inclusion */
|
||||
#include "hal/cpu_hal.h"
|
||||
|
||||
/* TODO: These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */
|
||||
/* TODO: These includes are not directly used in this file. They are kept into to prevent a breaking change. Remove these. */
|
||||
#include <limits.h>
|
||||
#include <xtensa/xtensa_api.h>
|
||||
|
||||
#include "soc/cpu.h"
|
||||
#include "soc/soc_memory_layout.h"
|
||||
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
#include "soc/compare_set.h"
|
||||
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
|
||||
#if ( ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
#include "soc/compare_set.h"
|
||||
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
|
||||
|
||||
/*#include "xtensa_context.h" */
|
||||
|
||||
|
|
@ -122,7 +123,7 @@
|
|||
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
|
||||
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#else
|
||||
|
|
@ -137,14 +138,14 @@
|
|||
#include "esp_attr.h"
|
||||
|
||||
/* "mux" data structure (spinlock) */
|
||||
typedef spinlock_t portMUX_TYPE; /**< Spinlock type used by FreeRTOS critical sections */
|
||||
#define portMUX_INITIALIZER_UNLOCKED SPINLOCK_INITIALIZER /**< Spinlock initializer */
|
||||
#define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */
|
||||
#define portMUX_NO_TIMEOUT SPINLOCK_WAIT_FOREVER /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */
|
||||
#define portMUX_TRY_LOCK SPINLOCK_NO_WAIT /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */
|
||||
#define portMUX_INITIALIZE(mux) spinlock_initialize(mux) /*< Initialize a spinlock to its unlocked state */
|
||||
typedef spinlock_t portMUX_TYPE; /**< Spinlock type used by FreeRTOS critical sections */
|
||||
#define portMUX_INITIALIZER_UNLOCKED SPINLOCK_INITIALIZER /**< Spinlock initializer */
|
||||
#define portMUX_FREE_VAL SPINLOCK_FREE /**< Spinlock is free. [refactor-todo] check if this is still required */
|
||||
#define portMUX_NO_TIMEOUT SPINLOCK_WAIT_FOREVER /**< When passed for 'timeout_cycles', spin forever if necessary. [refactor-todo] check if this is still required */
|
||||
#define portMUX_TRY_LOCK SPINLOCK_NO_WAIT /**< Try to acquire the spinlock a single time only. [refactor-todo] check if this is still required */
|
||||
#define portMUX_INITIALIZE( mux ) spinlock_initialize( mux ) /*< Initialize a spinlock to its unlocked state */
|
||||
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
|
||||
/*
|
||||
* Modifications to portENTER_CRITICAL.
|
||||
|
|
@ -223,8 +224,8 @@
|
|||
} \
|
||||
} while( 0 )
|
||||
|
||||
#define portASSERT_IF_IN_ISR() vPortAssertIfInISR()
|
||||
void vPortAssertIfInISR(void);
|
||||
#define portASSERT_IF_IN_ISR() vPortAssertIfInISR()
|
||||
void vPortAssertIfInISR( void );
|
||||
|
||||
/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
|
||||
/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
|
||||
|
|
@ -239,6 +240,7 @@
|
|||
static inline UBaseType_t __attribute__( ( always_inline ) ) xPortSetInterruptMaskFromISR( void )
|
||||
{
|
||||
UBaseType_t prev_int_level = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
|
||||
|
||||
portbenchmarkINTERRUPT_DISABLE();
|
||||
return prev_int_level;
|
||||
}
|
||||
|
|
@ -255,11 +257,11 @@
|
|||
|
||||
/*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */
|
||||
/*the stack memory to always be internal. */
|
||||
#define portTcbMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
|
||||
#define portStackMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
|
||||
#define portTcbMemoryCaps ( MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
|
||||
#define portStackMemoryCaps ( MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
|
||||
|
||||
#define pvPortMallocTcbMem(size) heap_caps_malloc(size, portTcbMemoryCaps)
|
||||
#define pvPortMallocStackMem(size) heap_caps_malloc(size, portStackMemoryCaps)
|
||||
#define pvPortMallocTcbMem( size ) heap_caps_malloc( size, portTcbMemoryCaps )
|
||||
#define pvPortMallocStackMem( size ) heap_caps_malloc( size, portStackMemoryCaps )
|
||||
|
||||
/*xTaskCreateStatic uses these functions to check incoming memory. */
|
||||
#define portVALID_TCB_MEM( ptr ) ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
|
||||
|
|
@ -278,18 +280,18 @@
|
|||
* *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the
|
||||
* ESP32 (portMUX assertions would fail).
|
||||
*/
|
||||
static inline void uxPortCompareSet( volatile uint32_t * addr,
|
||||
uint32_t compare,
|
||||
uint32_t * set )
|
||||
{
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
static inline void uxPortCompareSet( volatile uint32_t * addr,
|
||||
uint32_t compare,
|
||||
uint32_t * set )
|
||||
{
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
__asm__ __volatile__ (
|
||||
"WSR %2,SCOMPARE1 \n"
|
||||
"S32C1I %0, %1, 0 \n"
|
||||
: "=r" ( *set )
|
||||
: "r" ( addr ), "r" ( compare ), "0" ( *set )
|
||||
);
|
||||
#else
|
||||
#else
|
||||
#if ( XCHAL_HAVE_S32C1I > 0 )
|
||||
__asm__ __volatile__ (
|
||||
"WSR %2,SCOMPARE1 \n"
|
||||
|
|
@ -316,21 +318,23 @@
|
|||
|
||||
*set = old_value;
|
||||
#endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */
|
||||
#endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */
|
||||
}
|
||||
#endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */
|
||||
}
|
||||
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
void uxPortCompareSetExtram( volatile uint32_t * addr,
|
||||
uint32_t compare,
|
||||
uint32_t * set );
|
||||
#else
|
||||
static inline void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set)
|
||||
#else
|
||||
static inline void uxPortCompareSetExtram( volatile uint32_t * addr,
|
||||
uint32_t compare,
|
||||
uint32_t * set )
|
||||
{
|
||||
#if defined(CONFIG_SPIRAM)
|
||||
compare_and_set_extram(addr, compare, set);
|
||||
#endif
|
||||
#if defined( CONFIG_SPIRAM )
|
||||
compare_and_set_extram( addr, compare, set );
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#endif /* if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) ) */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -348,15 +352,17 @@
|
|||
|
||||
#ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
|
||||
/* Coarse resolution time (us) */
|
||||
#define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) do { x = ( uint32_t )esp_timer_get_time(); } while( 0 )
|
||||
#define portALT_GET_RUN_TIME_COUNTER_VALUE( x ) do { x = ( uint32_t ) esp_timer_get_time(); } while( 0 )
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Kernel utilities. */
|
||||
void vPortYield( void );
|
||||
void vPortEvaluateYieldFromISR( int argc, ... );
|
||||
void vPortEvaluateYieldFromISR( int argc,
|
||||
... );
|
||||
void _frxt_setup_switch( void );
|
||||
|
||||
/* Macro to count number of arguments of a __VA_ARGS__ used to support portYIELD_FROM_ISR with,
|
||||
* or without arguments. The macro counts only 0 or 1 arguments.
|
||||
*
|
||||
|
|
@ -366,26 +372,26 @@
|
|||
* This allows users to compile their code with standard C++20 enabled instead of the GNU extension.
|
||||
* Below C++20, we haven't found any good alternative to using ##__VA_ARGS__.
|
||||
*/
|
||||
#if defined( __cplusplus ) && ( __cplusplus > 201703L )
|
||||
#define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0 __VA_OPT__(,) __VA_ARGS__, 1 , 0 )
|
||||
#if defined( __cplusplus ) && ( __cplusplus > 201703L )
|
||||
#define portGET_ARGUMENT_COUNT( ... ) portGET_ARGUMENT_COUNT_INNER( 0 __VA_OPT__(, ) __VA_ARGS__, 1, 0 )
|
||||
#else
|
||||
#define portGET_ARGUMENT_COUNT(...) portGET_ARGUMENT_COUNT_INNER( 0, ##__VA_ARGS__, 1, 0 )
|
||||
#define portGET_ARGUMENT_COUNT( ... ) portGET_ARGUMENT_COUNT_INNER( 0, ## __VA_ARGS__, 1, 0 )
|
||||
#endif
|
||||
#define portGET_ARGUMENT_COUNT_INNER( zero, one, count, ... ) count
|
||||
#define portGET_ARGUMENT_COUNT_INNER( zero, one, count, ... ) count
|
||||
|
||||
_Static_assert( portGET_ARGUMENT_COUNT() == 0, "portGET_ARGUMENT_COUNT() result does not match for 0 arguments" );
|
||||
_Static_assert( portGET_ARGUMENT_COUNT( 1 ) == 1, "portGET_ARGUMENT_COUNT() result does not match for 1 argument" );
|
||||
|
||||
#define portYIELD() vPortYield()
|
||||
#define portYIELD() vPortYield()
|
||||
|
||||
/* The macro below could be used when passing a single argument, or without any argument,
|
||||
* it was developed to support both usages of portYIELD inside of an ISR. Any other usage form
|
||||
* might result in undesired behaviour
|
||||
*/
|
||||
#if defined( __cplusplus ) && ( __cplusplus > 201703L )
|
||||
#define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ) __VA_OPT__( , ) __VA_ARGS__ )
|
||||
#if defined( __cplusplus ) && ( __cplusplus > 201703L )
|
||||
#define portYIELD_FROM_ISR( ... ) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ) __VA_OPT__(, ) __VA_ARGS__ )
|
||||
#else
|
||||
#define portYIELD_FROM_ISR(...) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ), ##__VA_ARGS__ )
|
||||
#define portYIELD_FROM_ISR( ... ) vPortEvaluateYieldFromISR( portGET_ARGUMENT_COUNT( __VA_ARGS__ ), ## __VA_ARGS__ )
|
||||
#endif
|
||||
|
||||
static inline BaseType_t xPortGetCoreID();
|
||||
|
|
@ -436,31 +442,31 @@
|
|||
|
||||
void _xt_coproc_release( volatile void * coproc_sa_base );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
/* Architecture specific optimisations. */
|
||||
#if ( ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
/* Architecture specific optimisations. */
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) )
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
|
||||
#endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Map to the memory management routines required for the port.
|
||||
|
|
@ -474,7 +480,8 @@
|
|||
#define xPortGetFreeHeapSize esp_get_free_heap_size
|
||||
#define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size
|
||||
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
|
||||
/*
|
||||
* Send an interrupt to another core in order to make the task running
|
||||
* on it yield for a higher-priority task.
|
||||
|
|
@ -482,7 +489,7 @@
|
|||
|
||||
void vPortYieldOtherCore( BaseType_t coreid ) PRIVILEGED_FUNCTION;
|
||||
|
||||
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
|
||||
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
|
||||
|
||||
/*
|
||||
* Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
|
||||
|
|
@ -522,27 +529,27 @@
|
|||
/* Multi-core: get current core ID */
|
||||
static inline BaseType_t IRAM_ATTR xPortGetCoreID()
|
||||
{
|
||||
return ( uint32_t )cpu_hal_get_core_id();
|
||||
return ( uint32_t ) cpu_hal_get_core_id();
|
||||
}
|
||||
|
||||
/* Get tick rate per second */
|
||||
uint32_t xPortGetTickRateHz( void );
|
||||
|
||||
static inline bool IRAM_ATTR xPortCanYield(void)
|
||||
static inline bool IRAM_ATTR xPortCanYield( void )
|
||||
{
|
||||
uint32_t ps_reg = 0;
|
||||
|
||||
//Get the current value of PS (processor status) register
|
||||
RSR(PS, ps_reg);
|
||||
/*Get the current value of PS (processor status) register */
|
||||
RSR( PS, ps_reg );
|
||||
|
||||
/*
|
||||
* intlevel = (ps_reg & 0xf);
|
||||
* excm = (ps_reg >> 4) & 0x1;
|
||||
* CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3.
|
||||
* However, just return true, only intlevel is zero.
|
||||
*/
|
||||
* intlevel = (ps_reg & 0xf);
|
||||
* excm = (ps_reg >> 4) & 0x1;
|
||||
* CINTLEVEL is max(excm * EXCMLEVEL, INTLEVEL), where EXCMLEVEL is 3.
|
||||
* However, just return true, only intlevel is zero.
|
||||
*/
|
||||
|
||||
return ((ps_reg & PS_INTLEVEL_MASK) == 0);
|
||||
return( ( ps_reg & PS_INTLEVEL_MASK ) == 0 );
|
||||
}
|
||||
|
||||
/* porttrace */
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
|
||||
/* File adapted to use on IDF FreeRTOS component, extracted
|
||||
* originally from zephyr RTOS code base:
|
||||
* https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h
|
||||
* https://github.com/zephyrproject-rtos/zephyr/blob/dafd3485bf67880e667b6e9a758b0b64fb688d63/arch/xtensa/include/xtensa-asm2-s.h
|
||||
*/
|
||||
|
||||
#ifndef __XT_ASM_UTILS_H
|
||||
|
|
@ -67,9 +67,9 @@
|
|||
rotw 3
|
||||
and a4, a4, a4
|
||||
rotw 2
|
||||
#else
|
||||
#error Unrecognized XCHAL_NUM_AREGS
|
||||
#endif
|
||||
.endm
|
||||
#else /* if XCHAL_NUM_AREGS == 64 */
|
||||
#error Unrecognized XCHAL_NUM_AREGS
|
||||
#endif /* if XCHAL_NUM_AREGS == 64 */
|
||||
.endm
|
||||
|
||||
#endif
|
||||
#endif /* ifndef __XT_ASM_UTILS_H */
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
|
|
@ -40,7 +41,7 @@
|
|||
*******************************************************************************/
|
||||
|
||||
#ifndef XTENSA_CONFIG_H
|
||||
#define XTENSA_CONFIG_H
|
||||
#define XTENSA_CONFIG_H
|
||||
|
||||
/* *INDENT-OFF* */
|
||||
#ifdef __cplusplus
|
||||
|
|
@ -48,11 +49,11 @@
|
|||
#endif
|
||||
/* *INDENT-ON* */
|
||||
|
||||
#include <xtensa/hal.h>
|
||||
#include <xtensa/config/core.h>
|
||||
#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
|
||||
#include <xtensa/hal.h>
|
||||
#include <xtensa/config/core.h>
|
||||
#include <xtensa/config/system.h> /* required for XSHAL_CLIB */
|
||||
|
||||
#include "xtensa_context.h"
|
||||
#include "xtensa_context.h"
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
|
|
@ -105,27 +106,27 @@
|
|||
* -----------------------------------------------------------------------------*/
|
||||
|
||||
/* Extra space required for interrupt/exception hooks. */
|
||||
#ifdef XT_INTEXC_HOOKS
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define STK_INTEXC_EXTRA 0x200
|
||||
#else
|
||||
#define STK_INTEXC_EXTRA 0x180
|
||||
#endif
|
||||
#ifdef XT_INTEXC_HOOKS
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define STK_INTEXC_EXTRA 0x200
|
||||
#else
|
||||
#define STK_INTEXC_EXTRA 0
|
||||
#define STK_INTEXC_EXTRA 0x180
|
||||
#endif
|
||||
#else
|
||||
#define STK_INTEXC_EXTRA 0
|
||||
#endif
|
||||
|
||||
#define XT_CLIB_CONTEXT_AREA_SIZE 0
|
||||
#define XT_CLIB_CONTEXT_AREA_SIZE 0
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Extra size -- interrupt frame plus coprocessor save area plus hook space.
|
||||
* NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
|
||||
#else
|
||||
#define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
|
||||
#endif
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
|
||||
#else
|
||||
#define XT_XTRA_SIZE ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
|
||||
#endif
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Space allocated for user code -- function calls and local variables.
|
||||
|
|
@ -135,18 +136,18 @@
|
|||
* NOTE: The windowed ABI requires more stack, since space has to be reserved
|
||||
* for spilling register windows.
|
||||
* ------------------------------------------------------------------------------*/
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define XT_USER_SIZE 0x200
|
||||
#else
|
||||
#define XT_USER_SIZE 0x400
|
||||
#endif
|
||||
#ifdef __XTENSA_CALL0_ABI__
|
||||
#define XT_USER_SIZE 0x200
|
||||
#else
|
||||
#define XT_USER_SIZE 0x400
|
||||
#endif
|
||||
|
||||
/* Minimum recommended stack size. */
|
||||
#define XT_STACK_MIN_SIZE ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
|
||||
#define XT_STACK_MIN_SIZE ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
|
||||
|
||||
/* OS overhead with and without C library thread context. */
|
||||
#define XT_STACK_EXTRA ( XT_XTRA_SIZE )
|
||||
#define XT_STACK_EXTRA_CLIB ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
|
||||
#define XT_STACK_EXTRA ( XT_XTRA_SIZE )
|
||||
#define XT_STACK_EXTRA_CLIB ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
|
||||
|
||||
/* *INDENT-OFF* */
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
|
|
@ -60,6 +61,7 @@
|
|||
#include <xtensa/corebits.h>
|
||||
#include <xtensa/config/system.h>
|
||||
#include "sdkconfig.h"
|
||||
|
||||
/*
|
||||
* Include any RTOS specific definitions that are needed by this header.
|
||||
*/
|
||||
|
|
@ -155,9 +157,9 @@
|
|||
*/
|
||||
/* void XT_RTOS_TIMER_INT(void) */
|
||||
#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
|
||||
#define XT_RTOS_TIMER_INT _frxt_timer_int
|
||||
#define XT_RTOS_TIMER_INT _frxt_timer_int
|
||||
#endif
|
||||
#define XT_TICK_PER_SEC configTICK_RATE_HZ
|
||||
#define XT_TICK_PER_SEC configTICK_RATE_HZ
|
||||
|
||||
/*
|
||||
* Return in a15 the base address of the co-processor state save area for the
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
|
|
|
|||
162
portable/ThirdParty/GCC/Xtensa_ESP32/port.c
vendored
162
portable/ThirdParty/GCC/Xtensa_ESP32/port.c
vendored
|
|
@ -6,6 +6,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* FreeRTOS Kernel V10.4.3
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
|
|
@ -33,6 +34,7 @@
|
|||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
|
|
@ -63,22 +65,22 @@
|
|||
#include "xtensa_rtos.h"
|
||||
#include "esp_idf_version.h"
|
||||
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
#include "rom/ets_sys.h"
|
||||
#include "esp_panic.h"
|
||||
#include "esp_crosscore_int.h"
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
#include "rom/ets_sys.h"
|
||||
#include "esp_panic.h"
|
||||
#include "esp_crosscore_int.h"
|
||||
#else
|
||||
#if CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#endif
|
||||
#include "esp_private/panic_reason.h"
|
||||
#include "esp_debug_helpers.h"
|
||||
#include "esp_private/crosscore_int.h"
|
||||
#include "esp_log.h"
|
||||
#if CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/rom/ets_sys.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/rom/ets_sys.h"
|
||||
#endif
|
||||
#include "esp_private/panic_reason.h"
|
||||
#include "esp_debug_helpers.h"
|
||||
#include "esp_private/crosscore_int.h"
|
||||
#include "esp_log.h"
|
||||
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
|
||||
#include "soc/cpu.h"
|
||||
|
||||
|
|
@ -94,12 +96,12 @@
|
|||
/* Defined in xtensa_context.S */
|
||||
extern void _xt_coproc_init( void );
|
||||
|
||||
_Static_assert(tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value");
|
||||
_Static_assert( tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value" );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
extern volatile int port_xSchedulerRunning[portNUM_PROCESSORS];
|
||||
unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
|
||||
extern volatile int port_xSchedulerRunning[ portNUM_PROCESSORS ];
|
||||
unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 }; /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -153,15 +155,15 @@ void _xt_user_exit( void );
|
|||
thread_local_sz = ALIGNUP( 0x10, thread_local_sz );
|
||||
|
||||
/* Initialize task's stack so that we have the following structure at the top:
|
||||
|
||||
----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES----------
|
||||
task stack | interrupt stack frame | thread local vars | co-processor save area |
|
||||
----------------------------------------------------------------------------------
|
||||
| |
|
||||
SP pxTopOfStack
|
||||
|
||||
All parts are aligned to 16 byte boundary.
|
||||
*/
|
||||
*
|
||||
* ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES----------
|
||||
* task stack | interrupt stack frame | thread local vars | co-processor save area |
|
||||
* ----------------------------------------------------------------------------------
|
||||
| |
|
||||
| SP pxTopOfStack
|
||||
|
|
||||
| All parts are aligned to 16 byte boundary.
|
||||
*/
|
||||
|
||||
/* Create interrupt stack frame aligned to 16 byte boundary */
|
||||
sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ ) & ~0xf );
|
||||
|
|
@ -309,7 +311,7 @@ void vPortYieldOtherCore( BaseType_t coreid )
|
|||
uint32_t usStackDepth )
|
||||
{
|
||||
#if XCHAL_CP_NUM > 0
|
||||
xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ));
|
||||
xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ) );
|
||||
xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
|
||||
xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
|
||||
|
||||
|
|
@ -351,27 +353,29 @@ BaseType_t IRAM_ATTR xPortInterruptedFromISRContext()
|
|||
return( port_interruptNesting[ xPortGetCoreID() ] != 0 );
|
||||
}
|
||||
|
||||
void IRAM_ATTR vPortEvaluateYieldFromISR( int argc, ... )
|
||||
void IRAM_ATTR vPortEvaluateYieldFromISR( int argc,
|
||||
... )
|
||||
{
|
||||
BaseType_t xYield;
|
||||
va_list ap;
|
||||
|
||||
va_start( ap, argc );
|
||||
|
||||
if( argc )
|
||||
{
|
||||
xYield = ( BaseType_t )va_arg( ap, int );
|
||||
xYield = ( BaseType_t ) va_arg( ap, int );
|
||||
va_end( ap );
|
||||
}
|
||||
else
|
||||
{
|
||||
//it is a empty parameter vPortYieldFromISR macro call:
|
||||
/*it is a empty parameter vPortYieldFromISR macro call: */
|
||||
va_end( ap );
|
||||
traceISR_EXIT_TO_SCHEDULER();
|
||||
_frxt_setup_switch();
|
||||
return;
|
||||
}
|
||||
|
||||
//Yield exists, so need evaluate it first then switch:
|
||||
/*Yield exists, so need evaluate it first then switch: */
|
||||
if( xYield == pdTRUE )
|
||||
{
|
||||
traceISR_EXIT_TO_SCHEDULER();
|
||||
|
|
@ -477,8 +481,8 @@ void vPortCPUInitializeMutex( portMUX_TYPE * mux )
|
|||
}
|
||||
#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
|
||||
|
||||
#define STACK_WATCH_AREA_SIZE ( 32 )
|
||||
#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 )
|
||||
#define STACK_WATCH_AREA_SIZE ( 32 )
|
||||
#define STACK_WATCH_POINT_NUMBER ( SOC_CPU_WATCHPOINTS_NUM - 1 )
|
||||
|
||||
void vPortSetStackWatchpoint( void * pxStackStart )
|
||||
{
|
||||
|
|
@ -491,48 +495,48 @@ void vPortSetStackWatchpoint( void * pxStackStart )
|
|||
int addr = ( int ) pxStackStart;
|
||||
|
||||
addr = ( addr + 31 ) & ( ~31 );
|
||||
esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, (char*)addr, 32, ESP_WATCHPOINT_STORE );
|
||||
esp_cpu_set_watchpoint( STACK_WATCH_POINT_NUMBER, ( char * ) addr, 32, ESP_WATCHPOINT_STORE );
|
||||
}
|
||||
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
|
||||
#if defined( CONFIG_SPIRAM_SUPPORT )
|
||||
#if defined( CONFIG_SPIRAM_SUPPORT )
|
||||
|
||||
/*
|
||||
* Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it.
|
||||
*/
|
||||
static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
|
||||
static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
|
||||
|
||||
void uxPortCompareSetExtram( volatile uint32_t * addr,
|
||||
uint32_t compare,
|
||||
uint32_t * set )
|
||||
{
|
||||
uint32_t prev;
|
||||
|
||||
uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR();
|
||||
|
||||
#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
|
||||
vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
|
||||
#else
|
||||
vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
|
||||
#endif
|
||||
prev = *addr;
|
||||
|
||||
if( prev == compare )
|
||||
void uxPortCompareSetExtram( volatile uint32_t * addr,
|
||||
uint32_t compare,
|
||||
uint32_t * set )
|
||||
{
|
||||
*addr = *set;
|
||||
uint32_t prev;
|
||||
|
||||
uint32_t oldlevel = portSET_INTERRUPT_MASK_FROM_ISR();
|
||||
|
||||
#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
|
||||
vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
|
||||
#else
|
||||
vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
|
||||
#endif
|
||||
prev = *addr;
|
||||
|
||||
if( prev == compare )
|
||||
{
|
||||
*addr = *set;
|
||||
}
|
||||
|
||||
*set = prev;
|
||||
#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
|
||||
vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
|
||||
#else
|
||||
vPortCPUReleaseMutexIntsDisabled( &extram_mux );
|
||||
#endif
|
||||
|
||||
portCLEAR_INTERRUPT_MASK_FROM_ISR( oldlevel );
|
||||
}
|
||||
|
||||
*set = prev;
|
||||
#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
|
||||
vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
|
||||
#else
|
||||
vPortCPUReleaseMutexIntsDisabled( &extram_mux );
|
||||
#endif
|
||||
|
||||
portCLEAR_INTERRUPT_MASK_FROM_ISR(oldlevel);
|
||||
}
|
||||
#endif //defined(CONFIG_SPIRAM_SUPPORT)
|
||||
#endif //defined(CONFIG_SPIRAM_SUPPORT)
|
||||
|
||||
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
|
||||
|
||||
|
|
@ -542,27 +546,27 @@ uint32_t xPortGetTickRateHz( void )
|
|||
return ( uint32_t ) configTICK_RATE_HZ;
|
||||
}
|
||||
|
||||
// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
|
||||
// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
||||
// should mirror each other's values.
|
||||
//
|
||||
// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE.
|
||||
/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */
|
||||
/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */
|
||||
/* should mirror each other's values. */
|
||||
/* */
|
||||
/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */
|
||||
#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
||||
#error "FreeRTOS and system configuration mismatch regarding the use of multiple cores."
|
||||
#endif
|
||||
|
||||
extern void esp_startup_start_app_common(void);
|
||||
extern void esp_startup_start_app_common( void );
|
||||
|
||||
void esp_startup_start_app(void)
|
||||
void esp_startup_start_app( void )
|
||||
{
|
||||
#if !CONFIG_ESP_INT_WDT
|
||||
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
|
||||
assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
|
||||
#endif
|
||||
#endif
|
||||
#if !CONFIG_ESP_INT_WDT
|
||||
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
|
||||
assert( !soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!" );
|
||||
#endif
|
||||
#endif
|
||||
|
||||
esp_startup_start_app_common();
|
||||
|
||||
ESP_LOGI("cpu_start", "Starting scheduler on PRO CPU.");
|
||||
ESP_LOGI( "cpu_start", "Starting scheduler on PRO CPU." );
|
||||
vTaskStartScheduler();
|
||||
}
|
||||
|
|
|
|||
180
portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c
vendored
180
portable/ThirdParty/GCC/Xtensa_ESP32/port_common.c
vendored
|
|
@ -14,7 +14,7 @@
|
|||
#include "esp_task_wdt.h"
|
||||
#include "esp_task.h"
|
||||
#include "esp_private/crosscore_int.h"
|
||||
#include "esp_private/startup_internal.h" /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */
|
||||
#include "esp_private/startup_internal.h" /* Required by g_spiram_ok. [refactor-todo] for g_spiram_ok */
|
||||
#include "esp_log.h"
|
||||
#include "soc/soc_memory_types.h"
|
||||
#include "soc/dport_access.h"
|
||||
|
|
@ -22,17 +22,17 @@
|
|||
#include "esp_freertos_hooks.h"
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/spiram.h"
|
||||
#include "esp32/spiram.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/spiram.h"
|
||||
#include "esp32s2/spiram.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/spiram.h"
|
||||
#include "esp32s3/spiram.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
// SPIRAM is not supported on ESP32-C3
|
||||
/* SPIRAM is not supported on ESP32-C3 */
|
||||
#endif
|
||||
|
||||
#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
|
||||
static const char* TAG = "cpu_start";
|
||||
static const char * TAG = "cpu_start";
|
||||
#endif
|
||||
|
||||
/* Architecture-agnostic parts of the FreeRTOS ESP-IDF port layer can go here.
|
||||
|
|
@ -41,119 +41,127 @@ static const char* TAG = "cpu_start";
|
|||
* which will then call esp_startup_start_app_common()
|
||||
*/
|
||||
|
||||
// Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
|
||||
volatile unsigned port_xSchedulerRunning[portNUM_PROCESSORS] = {0};
|
||||
/* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */
|
||||
volatile unsigned port_xSchedulerRunning[ portNUM_PROCESSORS ] = { 0 };
|
||||
|
||||
// For now, running FreeRTOS on one core and a bare metal on the other (or other OSes)
|
||||
// is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
||||
// should mirror each other's values.
|
||||
//
|
||||
// And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE.
|
||||
/* For now, running FreeRTOS on one core and a bare metal on the other (or other OSes) */
|
||||
/* is not supported. For now CONFIG_FREERTOS_UNICORE and CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE */
|
||||
/* should mirror each other's values. */
|
||||
/* */
|
||||
/* And since this should be true, we can just check for CONFIG_FREERTOS_UNICORE. */
|
||||
#if CONFIG_FREERTOS_UNICORE != CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
||||
#error "FreeRTOS and system configuration mismatch regarding the use of multiple cores."
|
||||
#endif
|
||||
|
||||
static void main_task(void* args);
|
||||
static void main_task( void * args );
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
|
||||
void esp_gdbstub_init(void);
|
||||
void esp_gdbstub_init( void );
|
||||
#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
|
||||
|
||||
extern void app_main(void);
|
||||
extern void app_main( void );
|
||||
|
||||
void esp_startup_start_app_common(void)
|
||||
void esp_startup_start_app_common( void )
|
||||
{
|
||||
#if CONFIG_ESP_INT_WDT
|
||||
esp_int_wdt_init();
|
||||
//Initialize the interrupt watch dog for CPU0.
|
||||
esp_int_wdt_cpu_init();
|
||||
#endif
|
||||
#if CONFIG_ESP_INT_WDT
|
||||
esp_int_wdt_init();
|
||||
/*Initialize the interrupt watch dog for CPU0. */
|
||||
esp_int_wdt_cpu_init();
|
||||
#endif
|
||||
|
||||
esp_crosscore_int_init();
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
|
||||
esp_gdbstub_init();
|
||||
#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
|
||||
#ifdef CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
|
||||
esp_gdbstub_init();
|
||||
#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
|
||||
|
||||
portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
|
||||
ESP_TASK_MAIN_STACK, NULL,
|
||||
ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE);
|
||||
assert(res == pdTRUE);
|
||||
(void)res;
|
||||
portBASE_TYPE res = xTaskCreatePinnedToCore( &main_task, "main",
|
||||
ESP_TASK_MAIN_STACK, NULL,
|
||||
ESP_TASK_MAIN_PRIO, NULL, ESP_TASK_MAIN_CORE );
|
||||
assert( res == pdTRUE );
|
||||
( void ) res;
|
||||
}
|
||||
|
||||
#if !CONFIG_FREERTOS_UNICORE
|
||||
static volatile bool s_other_cpu_startup_done = false;
|
||||
static bool other_cpu_startup_idle_hook_cb(void)
|
||||
{
|
||||
s_other_cpu_startup_done = true;
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void main_task(void* args)
|
||||
{
|
||||
#if !CONFIG_FREERTOS_UNICORE
|
||||
// Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack
|
||||
esp_register_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID());
|
||||
while (!s_other_cpu_startup_done) {
|
||||
;
|
||||
static volatile bool s_other_cpu_startup_done = false;
|
||||
static bool other_cpu_startup_idle_hook_cb( void )
|
||||
{
|
||||
s_other_cpu_startup_done = true;
|
||||
return true;
|
||||
}
|
||||
esp_deregister_freertos_idle_hook_for_cpu(other_cpu_startup_idle_hook_cb, !xPortGetCoreID());
|
||||
#endif
|
||||
|
||||
// [refactor-todo] check if there is a way to move the following block to esp_system startup
|
||||
static void main_task( void * args )
|
||||
{
|
||||
#if !CONFIG_FREERTOS_UNICORE
|
||||
/* Wait for FreeRTOS initialization to finish on other core, before replacing its startup stack */
|
||||
esp_register_freertos_idle_hook_for_cpu( other_cpu_startup_idle_hook_cb, !xPortGetCoreID() );
|
||||
|
||||
while( !s_other_cpu_startup_done )
|
||||
{
|
||||
}
|
||||
esp_deregister_freertos_idle_hook_for_cpu( other_cpu_startup_idle_hook_cb, !xPortGetCoreID() );
|
||||
#endif
|
||||
|
||||
/* [refactor-todo] check if there is a way to move the following block to esp_system startup */
|
||||
heap_caps_enable_nonos_stack_heaps();
|
||||
|
||||
// Now we have startup stack RAM available for heap, enable any DMA pool memory
|
||||
#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
|
||||
if (g_spiram_ok) {
|
||||
esp_err_t r = esp_spiram_reserve_dma_pool(CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL);
|
||||
if (r != ESP_OK) {
|
||||
ESP_EARLY_LOGE(TAG, "Could not reserve internal/DMA pool (error 0x%x)", r);
|
||||
abort();
|
||||
/* Now we have startup stack RAM available for heap, enable any DMA pool memory */
|
||||
#if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL
|
||||
if( g_spiram_ok )
|
||||
{
|
||||
esp_err_t r = esp_spiram_reserve_dma_pool( CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL );
|
||||
|
||||
if( r != ESP_OK )
|
||||
{
|
||||
ESP_EARLY_LOGE( TAG, "Could not reserve internal/DMA pool (error 0x%x)", r );
|
||||
abort();
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif /* if CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL */
|
||||
|
||||
//Initialize task wdt if configured to do so
|
||||
#ifdef CONFIG_ESP_TASK_WDT_PANIC
|
||||
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, true));
|
||||
#elif CONFIG_ESP_TASK_WDT
|
||||
ESP_ERROR_CHECK(esp_task_wdt_init(CONFIG_ESP_TASK_WDT_TIMEOUT_S, false));
|
||||
#endif
|
||||
/*Initialize task wdt if configured to do so */
|
||||
#ifdef CONFIG_ESP_TASK_WDT_PANIC
|
||||
ESP_ERROR_CHECK( esp_task_wdt_init( CONFIG_ESP_TASK_WDT_TIMEOUT_S, true ) );
|
||||
#elif CONFIG_ESP_TASK_WDT
|
||||
ESP_ERROR_CHECK( esp_task_wdt_init( CONFIG_ESP_TASK_WDT_TIMEOUT_S, false ) );
|
||||
#endif
|
||||
|
||||
//Add IDLE 0 to task wdt
|
||||
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
|
||||
TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU(0);
|
||||
if(idle_0 != NULL){
|
||||
ESP_ERROR_CHECK(esp_task_wdt_add(idle_0));
|
||||
}
|
||||
#endif
|
||||
//Add IDLE 1 to task wdt
|
||||
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
|
||||
TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU(1);
|
||||
if(idle_1 != NULL){
|
||||
ESP_ERROR_CHECK(esp_task_wdt_add(idle_1));
|
||||
}
|
||||
#endif
|
||||
/*Add IDLE 0 to task wdt */
|
||||
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
|
||||
TaskHandle_t idle_0 = xTaskGetIdleTaskHandleForCPU( 0 );
|
||||
|
||||
if( idle_0 != NULL )
|
||||
{
|
||||
ESP_ERROR_CHECK( esp_task_wdt_add( idle_0 ) );
|
||||
}
|
||||
#endif
|
||||
/*Add IDLE 1 to task wdt */
|
||||
#ifdef CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
|
||||
TaskHandle_t idle_1 = xTaskGetIdleTaskHandleForCPU( 1 );
|
||||
|
||||
if( idle_1 != NULL )
|
||||
{
|
||||
ESP_ERROR_CHECK( esp_task_wdt_add( idle_1 ) );
|
||||
}
|
||||
#endif
|
||||
|
||||
app_main();
|
||||
vTaskDelete(NULL);
|
||||
vTaskDelete( NULL );
|
||||
}
|
||||
|
||||
// -------------------- Heap Related -----------------------
|
||||
/* -------------------- Heap Related ----------------------- */
|
||||
|
||||
bool xPortCheckValidTCBMem(const void *ptr)
|
||||
bool xPortCheckValidTCBMem( const void * ptr )
|
||||
{
|
||||
return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr);
|
||||
return esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr );
|
||||
}
|
||||
|
||||
bool xPortcheckValidStackMem(const void *ptr)
|
||||
bool xPortcheckValidStackMem( const void * ptr )
|
||||
{
|
||||
#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
|
||||
return esp_ptr_byte_accessible(ptr);
|
||||
#else
|
||||
return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr);
|
||||
#endif
|
||||
#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
|
||||
return esp_ptr_byte_accessible( ptr );
|
||||
#else
|
||||
return esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr );
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
206
portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c
vendored
206
portable/ThirdParty/GCC/Xtensa_ESP32/port_systick.c
vendored
|
|
@ -14,51 +14,51 @@
|
|||
#include "esp_log.h"
|
||||
#include "sdkconfig.h"
|
||||
#ifdef CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
|
||||
#include "soc/periph_defs.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "hal/systimer_hal.h"
|
||||
#include "hal/systimer_ll.h"
|
||||
#include "soc/periph_defs.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "hal/systimer_hal.h"
|
||||
#include "hal/systimer_ll.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM_TRACE
|
||||
#include "esp_private/pm_trace.h"
|
||||
#include "esp_private/pm_trace.h"
|
||||
#endif //CONFIG_PM_TRACE
|
||||
|
||||
BaseType_t xPortSysTickHandler(void);
|
||||
BaseType_t xPortSysTickHandler( void );
|
||||
|
||||
#ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
|
||||
extern void _frxt_tick_timer_init(void);
|
||||
extern void _xt_tick_divisor_init(void);
|
||||
extern void _frxt_tick_timer_init( void );
|
||||
extern void _xt_tick_divisor_init( void );
|
||||
|
||||
#ifdef CONFIG_FREERTOS_CORETIMER_0
|
||||
#define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
|
||||
#endif
|
||||
#ifdef CONFIG_FREERTOS_CORETIMER_1
|
||||
#define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
|
||||
#endif
|
||||
#ifdef CONFIG_FREERTOS_CORETIMER_0
|
||||
#define SYSTICK_INTR_ID ( ETS_INTERNAL_TIMER0_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF )
|
||||
#endif
|
||||
#ifdef CONFIG_FREERTOS_CORETIMER_1
|
||||
#define SYSTICK_INTR_ID ( ETS_INTERNAL_TIMER1_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Initialize CCONT timer to generate the tick interrupt
|
||||
*
|
||||
*/
|
||||
void vPortSetupTimer(void)
|
||||
{
|
||||
/* Init the tick divisor value */
|
||||
_xt_tick_divisor_init();
|
||||
void vPortSetupTimer( void )
|
||||
{
|
||||
/* Init the tick divisor value */
|
||||
_xt_tick_divisor_init();
|
||||
|
||||
_frxt_tick_timer_init();
|
||||
}
|
||||
_frxt_tick_timer_init();
|
||||
}
|
||||
|
||||
|
||||
#elif CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
|
||||
|
||||
_Static_assert(SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER");
|
||||
_Static_assert( SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER" );
|
||||
|
||||
void SysTickIsrHandler(void *arg);
|
||||
void SysTickIsrHandler( void * arg );
|
||||
|
||||
static uint32_t s_handled_systicks[portNUM_PROCESSORS] = { 0 };
|
||||
static uint32_t s_handled_systicks[ portNUM_PROCESSORS ] = { 0 };
|
||||
|
||||
#define SYSTICK_INTR_ID (ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE)
|
||||
#define SYSTICK_INTR_ID ( ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE )
|
||||
|
||||
/**
|
||||
* @brief Set up the systimer peripheral to generate the tick interrupt
|
||||
|
|
@ -67,50 +67,58 @@ static uint32_t s_handled_systicks[portNUM_PROCESSORS] = { 0 };
|
|||
* It is done at the same time so SysTicks for both CPUs occur at the same time or very close.
|
||||
* Shifts a time of triggering interrupts for core 0 and core 1.
|
||||
*/
|
||||
void vPortSetupTimer(void)
|
||||
{
|
||||
unsigned cpuid = xPortGetCoreID();
|
||||
#ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3
|
||||
const unsigned level = ESP_INTR_FLAG_LEVEL3;
|
||||
#else
|
||||
const unsigned level = ESP_INTR_FLAG_LEVEL1;
|
||||
#endif
|
||||
/* Systimer HAL layer object */
|
||||
static systimer_hal_context_t systimer_hal;
|
||||
/* set system timer interrupt vector */
|
||||
ESP_ERROR_CHECK(esp_intr_alloc(ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL));
|
||||
void vPortSetupTimer( void )
|
||||
{
|
||||
unsigned cpuid = xPortGetCoreID();
|
||||
|
||||
if (cpuid == 0) {
|
||||
systimer_hal_init(&systimer_hal);
|
||||
systimer_ll_set_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK, 0);
|
||||
systimer_ll_apply_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK);
|
||||
#ifdef CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL3
|
||||
const unsigned level = ESP_INTR_FLAG_LEVEL3;
|
||||
#else
|
||||
const unsigned level = ESP_INTR_FLAG_LEVEL1;
|
||||
#endif
|
||||
/* Systimer HAL layer object */
|
||||
static systimer_hal_context_t systimer_hal;
|
||||
/* set system timer interrupt vector */
|
||||
ESP_ERROR_CHECK( esp_intr_alloc( ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE + cpuid, ESP_INTR_FLAG_IRAM | level, SysTickIsrHandler, &systimer_hal, NULL ) );
|
||||
|
||||
for (cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++) {
|
||||
systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, false);
|
||||
}
|
||||
if( cpuid == 0 )
|
||||
{
|
||||
systimer_hal_init( &systimer_hal );
|
||||
systimer_ll_set_counter_value( systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK, 0 );
|
||||
systimer_ll_apply_counter_value( systimer_hal.dev, SYSTIMER_LL_COUNTER_OS_TICK );
|
||||
|
||||
for (cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid) {
|
||||
uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
|
||||
for( cpuid = 0; cpuid < SOC_CPU_CORES_NUM; cpuid++ )
|
||||
{
|
||||
systimer_hal_counter_can_stall_by_cpu( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, false );
|
||||
}
|
||||
|
||||
/* configure the timer */
|
||||
systimer_hal_connect_alarm_counter(&systimer_hal, alarm_id, SYSTIMER_LL_COUNTER_OS_TICK);
|
||||
systimer_hal_set_alarm_period(&systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ);
|
||||
systimer_hal_select_alarm_mode(&systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD);
|
||||
systimer_hal_counter_can_stall_by_cpu(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, true);
|
||||
if (cpuid == 0) {
|
||||
systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
|
||||
systimer_hal_enable_counter(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK);
|
||||
#ifndef CONFIG_FREERTOS_UNICORE
|
||||
// SysTick of core 0 and core 1 are shifted by half of period
|
||||
systimer_hal_counter_value_advance(&systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2);
|
||||
#endif
|
||||
for( cpuid = 0; cpuid < portNUM_PROCESSORS; ++cpuid )
|
||||
{
|
||||
uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
|
||||
|
||||
/* configure the timer */
|
||||
systimer_hal_connect_alarm_counter( &systimer_hal, alarm_id, SYSTIMER_LL_COUNTER_OS_TICK );
|
||||
systimer_hal_set_alarm_period( &systimer_hal, alarm_id, 1000000UL / CONFIG_FREERTOS_HZ );
|
||||
systimer_hal_select_alarm_mode( &systimer_hal, alarm_id, SYSTIMER_ALARM_MODE_PERIOD );
|
||||
systimer_hal_counter_can_stall_by_cpu( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, cpuid, true );
|
||||
|
||||
if( cpuid == 0 )
|
||||
{
|
||||
systimer_hal_enable_alarm_int( &systimer_hal, alarm_id );
|
||||
systimer_hal_enable_counter( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK );
|
||||
#ifndef CONFIG_FREERTOS_UNICORE
|
||||
/* SysTick of core 0 and core 1 are shifted by half of period */
|
||||
systimer_hal_counter_value_advance( &systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK, 1000000UL / CONFIG_FREERTOS_HZ / 2 );
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
|
||||
systimer_hal_enable_alarm_int(&systimer_hal, alarm_id);
|
||||
else
|
||||
{
|
||||
uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
|
||||
systimer_hal_enable_alarm_int( &systimer_hal, alarm_id );
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Systimer interrupt handler.
|
||||
|
|
@ -118,37 +126,46 @@ void vPortSetupTimer(void)
|
|||
* The Systimer interrupt for SysTick works in periodic mode no need to calc the next alarm.
|
||||
* If a timer interrupt is ever serviced more than one tick late, it is necessary to process multiple ticks.
|
||||
*/
|
||||
IRAM_ATTR void SysTickIsrHandler(void *arg)
|
||||
{
|
||||
uint32_t cpuid = xPortGetCoreID();
|
||||
systimer_hal_context_t *systimer_hal = (systimer_hal_context_t *)arg;
|
||||
#ifdef CONFIG_PM_TRACE
|
||||
ESP_PM_TRACE_ENTER(TICK, cpuid);
|
||||
#endif
|
||||
IRAM_ATTR void SysTickIsrHandler( void * arg )
|
||||
{
|
||||
uint32_t cpuid = xPortGetCoreID();
|
||||
systimer_hal_context_t * systimer_hal = ( systimer_hal_context_t * ) arg;
|
||||
|
||||
uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
|
||||
do {
|
||||
systimer_ll_clear_alarm_int(systimer_hal->dev, alarm_id);
|
||||
#ifdef CONFIG_PM_TRACE
|
||||
ESP_PM_TRACE_ENTER( TICK, cpuid );
|
||||
#endif
|
||||
|
||||
uint32_t diff = systimer_hal_get_counter_value(systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK) / systimer_ll_get_alarm_period(systimer_hal->dev, alarm_id) - s_handled_systicks[cpuid];
|
||||
if (diff > 0) {
|
||||
if (s_handled_systicks[cpuid] == 0) {
|
||||
s_handled_systicks[cpuid] = diff;
|
||||
diff = 1;
|
||||
} else {
|
||||
s_handled_systicks[cpuid] += diff;
|
||||
uint32_t alarm_id = SYSTIMER_LL_ALARM_OS_TICK_CORE0 + cpuid;
|
||||
|
||||
do
|
||||
{
|
||||
systimer_ll_clear_alarm_int( systimer_hal->dev, alarm_id );
|
||||
|
||||
uint32_t diff = systimer_hal_get_counter_value( systimer_hal, SYSTIMER_LL_COUNTER_OS_TICK ) / systimer_ll_get_alarm_period( systimer_hal->dev, alarm_id ) - s_handled_systicks[ cpuid ];
|
||||
|
||||
if( diff > 0 )
|
||||
{
|
||||
if( s_handled_systicks[ cpuid ] == 0 )
|
||||
{
|
||||
s_handled_systicks[ cpuid ] = diff;
|
||||
diff = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
s_handled_systicks[ cpuid ] += diff;
|
||||
}
|
||||
|
||||
do
|
||||
{
|
||||
xPortSysTickHandler();
|
||||
} while( --diff );
|
||||
}
|
||||
} while( systimer_ll_is_alarm_int_fired( systimer_hal->dev, alarm_id ) );
|
||||
|
||||
do {
|
||||
xPortSysTickHandler();
|
||||
} while (--diff);
|
||||
}
|
||||
} while (systimer_ll_is_alarm_int_fired(systimer_hal->dev, alarm_id));
|
||||
|
||||
#ifdef CONFIG_PM_TRACE
|
||||
ESP_PM_TRACE_EXIT(TICK, cpuid);
|
||||
#endif
|
||||
}
|
||||
#ifdef CONFIG_PM_TRACE
|
||||
ESP_PM_TRACE_EXIT( TICK, cpuid );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
|
||||
|
||||
|
|
@ -160,15 +177,20 @@ IRAM_ATTR void SysTickIsrHandler(void *arg)
|
|||
* - SysTickIsrHandler for xtensa with CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER
|
||||
* - SysTickIsrHandler for riscv
|
||||
*/
|
||||
BaseType_t xPortSysTickHandler(void)
|
||||
BaseType_t xPortSysTickHandler( void )
|
||||
{
|
||||
portbenchmarkIntLatency();
|
||||
traceISR_ENTER(SYSTICK_INTR_ID);
|
||||
traceISR_ENTER( SYSTICK_INTR_ID );
|
||||
BaseType_t ret = xTaskIncrementTick();
|
||||
if(ret != pdFALSE) {
|
||||
|
||||
if( ret != pdFALSE )
|
||||
{
|
||||
portYIELD_FROM_ISR();
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
traceISR_EXIT();
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,10 +31,10 @@
|
|||
#include "portable.h"
|
||||
|
||||
/* XOR one core ID with this value to get the other core ID */
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
#define CORE_ID_XOR_SWAP ( CORE_ID_PRO ^ CORE_ID_APP )
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
#define CORE_ID_XOR_SWAP ( CORE_ID_PRO ^ CORE_ID_APP )
|
||||
#else
|
||||
#define CORE_ID_REGVAL_XOR_SWAP (CORE_ID_REGVAL_PRO ^ CORE_ID_REGVAL_APP)
|
||||
#define CORE_ID_REGVAL_XOR_SWAP ( CORE_ID_REGVAL_PRO ^ CORE_ID_REGVAL_APP )
|
||||
#endif
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -53,16 +53,16 @@ static inline bool __attribute__( ( always_inline ) )
|
|||
#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
|
||||
uint32_t owner = mux->owner;
|
||||
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
|
||||
#else
|
||||
if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP)
|
||||
if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_REGVAL_PRO ) && ( owner != CORE_ID_REGVAL_APP ) )
|
||||
#endif
|
||||
{
|
||||
ets_printf( "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, owner, fnName, line );
|
||||
mux->owner = portMUX_FREE_VAL;
|
||||
}
|
||||
#endif
|
||||
#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
|
||||
|
||||
/* Spin until we own the core */
|
||||
|
||||
|
|
@ -71,10 +71,10 @@ static inline bool __attribute__( ( always_inline ) )
|
|||
/* Note: coreID is the full 32 bit core ID (CORE_ID_PRO/CORE_ID_APP),
|
||||
* not the 0/1 value returned by xPortGetCoreID()
|
||||
*/
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
otherCoreID = CORE_ID_XOR_SWAP ^ coreID;
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
otherCoreID = CORE_ID_XOR_SWAP ^ coreID;
|
||||
#else
|
||||
otherCoreID = CORE_ID_REGVAL_XOR_SWAP ^ coreID;
|
||||
otherCoreID = CORE_ID_REGVAL_XOR_SWAP ^ coreID;
|
||||
#endif
|
||||
|
||||
do
|
||||
|
|
@ -154,10 +154,10 @@ static inline bool __attribute__( ( always_inline ) )
|
|||
mux->lastLockedLine = line;
|
||||
uint32_t owner = mux->owner;
|
||||
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
|
||||
#else
|
||||
if (owner != portMUX_FREE_VAL && owner != CORE_ID_REGVAL_PRO && owner != CORE_ID_REGVAL_APP)
|
||||
if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_REGVAL_PRO ) && ( owner != CORE_ID_REGVAL_APP ) )
|
||||
#endif
|
||||
{
|
||||
ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p is invalid (0x%x)!\n", mux, mux->owner );
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
|
|
@ -39,37 +40,37 @@
|
|||
|
||||
|
||||
#ifdef XT_BOARD
|
||||
#include "xtensa/xtbsp.h"
|
||||
#include "xtensa/xtbsp.h"
|
||||
#endif
|
||||
|
||||
#include "xtensa_rtos.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_idf_version.h"
|
||||
#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
|
||||
#include "esp_clk.h"
|
||||
#if ( ESP_IDF_VERSION < ESP_IDF_VERSION_VAL( 4, 2, 0 ) )
|
||||
#include "esp_clk.h"
|
||||
#else
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/clk.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/clk.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/clk.h"
|
||||
#endif
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
#include "esp32/clk.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||
#include "esp32s2/clk.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
#include "esp32s3/clk.h"
|
||||
#endif
|
||||
#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
|
||||
|
||||
#ifdef XT_RTOS_TIMER_INT
|
||||
|
||||
unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */
|
||||
unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */
|
||||
|
||||
void _xt_tick_divisor_init(void)
|
||||
{
|
||||
_xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC;
|
||||
}
|
||||
void _xt_tick_divisor_init( void )
|
||||
{
|
||||
_xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC;
|
||||
}
|
||||
|
||||
/* Deprecated, to be removed */
|
||||
int xt_clock_freq(void)
|
||||
{
|
||||
return esp_clk_cpu_freq();
|
||||
}
|
||||
int xt_clock_freq( void )
|
||||
{
|
||||
return esp_clk_cpu_freq();
|
||||
}
|
||||
|
||||
#endif /* XT_RTOS_TIMER_INT */
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
*
|
||||
* SPDX-FileContributor: 2016-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
|
||||
*
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue