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This commit is contained in:
Soren Ptak
GitHub
parent
d6bccb1f4c
commit
5fb9b50da8
485 changed files with 108790 additions and 107581 deletions
315
portable/ThirdParty/GCC/RP2040/include/portmacro.h
vendored
315
portable/ThirdParty/GCC/RP2040/include/portmacro.h
vendored
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@ -28,7 +28,7 @@
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#define PORTMACRO_H
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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@ -36,8 +36,8 @@
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#endif
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/* *INDENT-ON* */
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#include "pico.h"
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#include "hardware/sync.h"
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#include "pico.h"
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#include "hardware/sync.h"
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/*-----------------------------------------------------------
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* Port specific definitions.
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@ -50,210 +50,225 @@
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*/
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE long
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typedef portSTACK_TYPE StackType_t;
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typedef int32_t BaseType_t;
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typedef uint32_t UBaseType_t;
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typedef portSTACK_TYPE StackType_t;
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typedef int32_t BaseType_t;
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typedef uint32_t UBaseType_t;
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#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
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typedef uint16_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffff
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#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
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typedef uint32_t TickType_t;
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
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* not need to be guarded with a critical section. */
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#define portTICK_TYPE_IS_ATOMIC 1
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#else
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#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
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#endif
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#define portTICK_TYPE_IS_ATOMIC 1
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#else
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#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
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#endif
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/*-----------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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#define portDONT_DISCARD __attribute__( ( used ) )
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/* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config,
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* as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */
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#define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS
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#if portUSE_DIVIDER_SAVE_RESTORE
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#define portSTACK_LIMIT_PADDING 4
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#endif
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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#define portDONT_DISCARD __attribute__( ( used ) )
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/* We have to use PICO_DIVIDER_DISABLE_INTERRUPTS as the source of truth rathern than our config,
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* as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */
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#define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS
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#if portUSE_DIVIDER_SAVE_RESTORE
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#define portSTACK_LIMIT_PADDING 4
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#endif
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/*-----------------------------------------------------------*/
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/* Scheduler utilities. */
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extern void vPortYield( void );
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portYIELD() vPortYield()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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extern void vPortYield( void );
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#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
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#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
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#define portYIELD() vPortYield()
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#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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/*-----------------------------------------------------------*/
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/* Exception handlers */
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#if (configUSE_DYNAMIC_EXCEPTION_HANDLERS == 0)
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/* We only need to override the SDK's weak functions if we want to replace them at compile time */
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#define vPortSVCHandler isr_svcall
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#define xPortPendSVHandler isr_pendsv
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#define xPortSysTickHandler isr_systick
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#endif
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#if ( configUSE_DYNAMIC_EXCEPTION_HANDLERS == 0 )
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/* We only need to override the SDK's weak functions if we want to replace them at compile time */
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#define vPortSVCHandler isr_svcall
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#define xPortPendSVHandler isr_pendsv
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#define xPortSysTickHandler isr_systick
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#endif
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/*-----------------------------------------------------------*/
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/* Multi-core */
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#define portMAX_CORE_COUNT 2
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#define portMAX_CORE_COUNT 2
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/* Check validity of number of cores specified in config */
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#if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES )
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#error "Invalid number of cores specified in config!"
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#endif
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/* Check validity of number of cores specified in config */
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#if ( configNUMBER_OF_CORES < 1 || portMAX_CORE_COUNT < configNUMBER_OF_CORES )
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#error "Invalid number of cores specified in config!"
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#endif
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#if ( configTICK_CORE < 0 || configTICK_CORE > configNUMBER_OF_CORES )
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#error "Invalid tick core specified in config!"
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#endif
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/* FreeRTOS core id is always zero based, so always 0 if we're running on only one core */
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#if configNUMBER_OF_CORES == portMAX_CORE_COUNT
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#define portGET_CORE_ID() get_core_num()
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#else
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#define portGET_CORE_ID() 0
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#endif
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#if ( configTICK_CORE < 0 || configTICK_CORE > configNUMBER_OF_CORES )
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#error "Invalid tick core specified in config!"
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#endif
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/* FreeRTOS core id is always zero based, so always 0 if we're running on only one core */
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#if configNUMBER_OF_CORES == portMAX_CORE_COUNT
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#define portGET_CORE_ID() get_core_num()
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#else
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#define portGET_CORE_ID() 0
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#endif
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#define portCHECK_IF_IN_ISR() ({ \
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uint32_t ulIPSR; \
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__asm volatile ("mrs %0, IPSR" : "=r" (ulIPSR)::); \
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((uint8_t)ulIPSR)>0;})
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#define portCHECK_IF_IN_ISR() \
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( { \
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uint32_t ulIPSR; \
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__asm volatile ( "mrs %0, IPSR" : "=r" ( ulIPSR )::); \
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( ( uint8_t ) ulIPSR ) > 0; } )
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void vYieldCore(int xCoreID);
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#define portYIELD_CORE(a) vYieldCore(a)
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#define portRESTORE_INTERRUPTS(ulState) __asm volatile ("msr PRIMASK,%0"::"r" (ulState) : )
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void vYieldCore( int xCoreID );
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#define portYIELD_CORE( a ) vYieldCore( a )
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#define portRESTORE_INTERRUPTS( ulState ) __asm volatile ( "msr PRIMASK,%0" ::"r" ( ulState ) : )
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/*-----------------------------------------------------------*/
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/* Critical nesting count management. */
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extern UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ];
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#define portGET_CRITICAL_NESTING_COUNT() ( uxCriticalNestings[ portGET_CORE_ID() ] )
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#define portSET_CRITICAL_NESTING_COUNT( x ) ( uxCriticalNestings[ portGET_CORE_ID() ] = ( x ) )
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#define portINCREMENT_CRITICAL_NESTING_COUNT() ( uxCriticalNestings[ portGET_CORE_ID() ]++ )
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#define portDECREMENT_CRITICAL_NESTING_COUNT() ( uxCriticalNestings[ portGET_CORE_ID() ]-- )
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extern UBaseType_t uxCriticalNestings[ configNUMBER_OF_CORES ];
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#define portGET_CRITICAL_NESTING_COUNT() ( uxCriticalNestings[ portGET_CORE_ID() ] )
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#define portSET_CRITICAL_NESTING_COUNT( x ) ( uxCriticalNestings[ portGET_CORE_ID() ] = ( x ) )
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#define portINCREMENT_CRITICAL_NESTING_COUNT() ( uxCriticalNestings[ portGET_CORE_ID() ]++ )
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#define portDECREMENT_CRITICAL_NESTING_COUNT() ( uxCriticalNestings[ portGET_CORE_ID() ]-- )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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#define portSET_INTERRUPT_MASK() ({ \
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uint32_t ulState; \
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__asm volatile ("mrs %0, PRIMASK" : "=r" (ulState)::); \
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__asm volatile ( " cpsid i " ::: "memory" ); \
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ulState;})
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#define portSET_INTERRUPT_MASK() \
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( { \
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uint32_t ulState; \
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__asm volatile ( "mrs %0, PRIMASK" : "=r" ( ulState )::); \
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__asm volatile ( " cpsid i " ::: "memory" ); \
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ulState; } )
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#define portCLEAR_INTERRUPT_MASK(ulState) __asm volatile ("msr PRIMASK,%0"::"r" (ulState) : )
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#define portCLEAR_INTERRUPT_MASK( ulState ) __asm volatile ( "msr PRIMASK,%0" ::"r" ( ulState ) : )
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extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
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extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) );
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#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x )
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extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
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extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) );
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#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x )
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#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
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#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
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extern void vPortEnableInterrupts();
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#define portENABLE_INTERRUPTS() vPortEnableInterrupts()
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extern void vPortEnableInterrupts();
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#define portENABLE_INTERRUPTS() vPortEnableInterrupts()
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#if ( configNUMBER_OF_CORES == 1 )
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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#else
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extern void vTaskEnterCritical( void );
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extern void vTaskExitCritical( void );
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extern UBaseType_t vTaskEnterCriticalFromISR( void );
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extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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#define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR()
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#define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x )
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#endif
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#if ( configNUMBER_OF_CORES == 1 )
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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#else
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extern void vTaskEnterCritical( void );
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extern void vTaskExitCritical( void );
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extern UBaseType_t vTaskEnterCriticalFromISR( void );
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extern void vTaskExitCriticalFromISR( UBaseType_t uxSavedInterruptStatus );
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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#define portENTER_CRITICAL_FROM_ISR() vTaskEnterCriticalFromISR()
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#define portEXIT_CRITICAL_FROM_ISR( x ) vTaskExitCriticalFromISR( x )
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#endif /* if ( configNUMBER_OF_CORES == 1 ) */
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#define portRTOS_SPINLOCK_COUNT 2
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#define portRTOS_SPINLOCK_COUNT 2
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/* Note this is a single method with uxAcquire parameter since we have
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* static vars, the method is always called with a compile time constant for
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* uxAcquire, and the compiler should dothe right thing! */
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static inline void vPortRecursiveLock(uint32_t ulLockNum, spin_lock_t *pxSpinLock, BaseType_t uxAcquire) {
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static uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ];
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static uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
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configASSERT( ulLockNum < portRTOS_SPINLOCK_COUNT );
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uint32_t ulCoreNum = get_core_num();
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uint32_t ulLockBit = 1u << ulLockNum;
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configASSERT(ulLockBit < 256u );
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if( uxAcquire )
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/* Note this is a single method with uxAcquire parameter since we have
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* static vars, the method is always called with a compile time constant for
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* uxAcquire, and the compiler should dothe right thing! */
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static inline void vPortRecursiveLock( uint32_t ulLockNum,
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spin_lock_t * pxSpinLock,
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BaseType_t uxAcquire )
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{
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static uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ];
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static uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
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configASSERT( ulLockNum < portRTOS_SPINLOCK_COUNT );
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uint32_t ulCoreNum = get_core_num();
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uint32_t ulLockBit = 1u << ulLockNum;
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configASSERT( ulLockBit < 256u );
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if( uxAcquire )
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{
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if( __builtin_expect( !*pxSpinLock, 0 ) )
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{
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if( __builtin_expect( !*pxSpinLock, 0 ) )
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if( ucOwnedByCore[ ulCoreNum ] & ulLockBit )
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{
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if( ucOwnedByCore[ulCoreNum] & ulLockBit )
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{
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configASSERT(ucRecursionCountByLock[ulLockNum] != 255u );
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ucRecursionCountByLock[ulLockNum]++;
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return;
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}
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while ( __builtin_expect( !*pxSpinLock, 0 ) );
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configASSERT( ucRecursionCountByLock[ ulLockNum ] != 255u );
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ucRecursionCountByLock[ ulLockNum ]++;
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return;
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}
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__mem_fence_acquire();
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configASSERT(ucRecursionCountByLock[ulLockNum] == 0 );
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ucRecursionCountByLock[ulLockNum] = 1;
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ucOwnedByCore[ulCoreNum] |= ulLockBit;
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} else {
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configASSERT((ucOwnedByCore[ulCoreNum] & ulLockBit) != 0 );
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configASSERT(ucRecursionCountByLock[ulLockNum] != 0 );
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if( !--ucRecursionCountByLock[ulLockNum] )
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while( __builtin_expect( !*pxSpinLock, 0 ) )
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{
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ucOwnedByCore[ulCoreNum] &= ~ulLockBit;
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__mem_fence_release();
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*pxSpinLock = 1;
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}
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}
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}
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#if ( configNUMBER_OF_CORES == 1 )
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#define portGET_ISR_LOCK()
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#define portRELEASE_ISR_LOCK()
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#define portGET_TASK_LOCK()
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#define portRELEASE_TASK_LOCK()
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#else
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#define portGET_ISR_LOCK() vPortRecursiveLock(0, spin_lock_instance(configSMP_SPINLOCK_0), pdTRUE)
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#define portRELEASE_ISR_LOCK() vPortRecursiveLock(0, spin_lock_instance(configSMP_SPINLOCK_0), pdFALSE)
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#define portGET_TASK_LOCK() vPortRecursiveLock(1, spin_lock_instance(configSMP_SPINLOCK_1), pdTRUE)
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#define portRELEASE_TASK_LOCK() vPortRecursiveLock(1, spin_lock_instance(configSMP_SPINLOCK_1), pdFALSE)
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#endif
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__mem_fence_acquire();
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configASSERT( ucRecursionCountByLock[ ulLockNum ] == 0 );
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ucRecursionCountByLock[ ulLockNum ] = 1;
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ucOwnedByCore[ ulCoreNum ] |= ulLockBit;
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}
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else
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{
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configASSERT( ( ucOwnedByCore[ ulCoreNum ] & ulLockBit ) != 0 );
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configASSERT( ucRecursionCountByLock[ ulLockNum ] != 0 );
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if( !--ucRecursionCountByLock[ ulLockNum ] )
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{
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ucOwnedByCore[ ulCoreNum ] &= ~ulLockBit;
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__mem_fence_release();
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*pxSpinLock = 1;
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}
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}
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}
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#if ( configNUMBER_OF_CORES == 1 )
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#define portGET_ISR_LOCK()
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#define portRELEASE_ISR_LOCK()
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#define portGET_TASK_LOCK()
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#define portRELEASE_TASK_LOCK()
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#else
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#define portGET_ISR_LOCK() vPortRecursiveLock( 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdTRUE )
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#define portRELEASE_ISR_LOCK() vPortRecursiveLock( 0, spin_lock_instance( configSMP_SPINLOCK_0 ), pdFALSE )
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#define portGET_TASK_LOCK() vPortRecursiveLock( 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdTRUE )
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#define portRELEASE_TASK_LOCK() vPortRecursiveLock( 1, spin_lock_instance( configSMP_SPINLOCK_1 ), pdFALSE )
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#endif
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/*-----------------------------------------------------------*/
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/* Tickless idle/low power functionality. */
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#ifndef portSUPPRESS_TICKS_AND_SLEEP
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extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
|
||||
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
|
||||
#endif
|
||||
#ifndef portSUPPRESS_TICKS_AND_SLEEP
|
||||
extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
|
||||
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
|
||||
#define portNOP()
|
||||
#define portNOP()
|
||||
|
||||
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
|
||||
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
|
||||
|
||||
/* *INDENT-OFF* */
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue