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CI-CD Updates (#768)
* Use new version of CI-CD Actions * Use cSpell spell check, and use ubuntu-20.04 for formatting check * Format and spell check all files in the portable directory * Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /* * Use checkout@v3 instead of checkout@v2 on all jobs ---------
This commit is contained in:
Soren Ptak
GitHub
parent
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commit
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485 changed files with 108790 additions and 107581 deletions
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@ -28,187 +28,187 @@
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#include "FreeRTOSConfig.h"
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#define portCONTEXT_SIZE 132
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#define portEPC_STACK_LOCATION 124
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#define portSTATUS_STACK_LOCATION 128
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#define portCONTEXT_SIZE 132
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#define portEPC_STACK_LOCATION 124
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#define portSTATUS_STACK_LOCATION 128
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#ifdef __LANGUAGE_ASSEMBLY__
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/******************************************************************/
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.macro portSAVE_CONTEXT
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.macro portSAVE_CONTEXT
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/* Make room for the context. First save the current status so it can be
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manipulated, and the cause and EPC registers so their original values are
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captured. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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mfc0 k1, _CP0_STATUS
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/* Make room for the context. First save the current status so it can be
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* manipulated, and the cause and EPC registers so their original values are
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* captured. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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mfc0 k1, _CP0_STATUS
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/* Also save s6 and s5 so they can be used. Any nesting interrupts should
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maintain the values of these registers across the ISR. */
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sw s6, 44(sp)
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sw s5, 40(sp)
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sw k1, portSTATUS_STACK_LOCATION(sp)
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/* Also save s6 and s5 so they can be used. Any nesting interrupts should
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* maintain the values of these registers across the ISR. */
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sw s6, 44 ( sp )
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sw s5, 40 ( sp )
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sw k1, portSTATUS_STACK_LOCATION( sp )
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/* Prepare to enable interrupts above the current priority.
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k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
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srl k0, k0, 0xa
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/* Prepare to enable interrupts above the current priority.
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* k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
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srl k0, k0, 0xa
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/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
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ins k1, k0, 10, 7
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/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
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ins k1, k0, 10, 7
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/* Sets CP0.Status.IPL = CP0.Cause.RIPL
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Copy the MSB of the IPL, but it would be an error if it was set anyway. */
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srl k0, k0, 0x7
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/* Sets CP0.Status.IPL = CP0.Cause.RIPL
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* Copy the MSB of the IPL, but it would be an error if it was set anyway. */
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srl k0, k0, 0x7
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/* MSB of IPL is bit[18] of CP0.Status */
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ins k1, k0, 18, 1
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/* MSB of IPL is bit[18] of CP0.Status */
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ins k1, k0, 18, 1
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/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
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b[3]=Rsvd, b[2]=ERL, b[1]=EXL
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Setting EXL=0 allows higher priority interrupts
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to preempt this handler */
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ins k1, zero, 1, 4
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/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
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* b[3]=Rsvd, b[2]=ERL, b[1]=EXL
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* Setting EXL=0 allows higher priority interrupts
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* to preempt this handler */
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ins k1, zero, 1, 4
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/* s5 is used as the frame pointer. */
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add s5, zero, sp
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/* s5 is used as the frame pointer. */
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add s5, zero, sp
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/* Check the nesting count value. */
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la k0, uxInterruptNesting
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lw s6, (k0)
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/* Check the nesting count value. */
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la k0, uxInterruptNesting
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lw s6, ( k0 )
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/* If the nesting count is 0 then swap to the the system stack, otherwise
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the system stack is already being used. */
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bne s6, zero, 1f
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/* If the nesting count is 0 then swap to the the system stack, otherwise
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* the system stack is already being used. */
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bne s6, zero, 1f
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nop
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/* Swap to the system stack. */
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la sp, xISRStackTop
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lw sp, (sp)
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/* Swap to the system stack. */
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la sp, xISRStackTop
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lw sp, ( sp )
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/* Increment and save the nesting count. */
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1: addiu s6, s6, 1
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sw s6, 0(k0)
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/* Increment and save the nesting count. */
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1 : addiu s6, s6, 1
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sw s6, 0 ( k0 )
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/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
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mfc0 s6, _CP0_EPC
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/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
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mfc0 s6, _CP0_EPC
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/* Re-enable interrupts. */
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mtc0 k1, _CP0_STATUS
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/* Re-enable interrupts. */
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mtc0 k1, _CP0_STATUS
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/* Save the context into the space just created. s6 is saved again
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here as it now contains the EPC value. No other s registers need be
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saved. */
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sw ra, 120(s5) /* Return address (RA=R31) */
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sw s8, 116(s5) /* Frame Pointer (FP=R30) */
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sw t9, 112(s5)
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sw t8, 108(s5)
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sw t7, 104(s5)
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sw t6, 100(s5)
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sw t5, 96(s5)
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sw t4, 92(s5)
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sw t3, 88(s5)
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sw t2, 84(s5)
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sw t1, 80(s5)
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sw t0, 76(s5)
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sw a3, 72(s5)
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sw a2, 68(s5)
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sw a1, 64(s5)
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sw a0, 60(s5)
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sw v1, 56(s5)
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sw v0, 52(s5)
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sw s6, portEPC_STACK_LOCATION(s5)
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sw $1, 16(s5)
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/* Save the context into the space just created. s6 is saved again
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* here as it now contains the EPC value. No other s registers need be
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* saved. */
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sw ra, 120 ( s5 ) /* Return address (RA=R31) */
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sw s8, 116 ( s5 ) /* Frame Pointer (FP=R30) */
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sw t9, 112 ( s5 )
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sw t8, 108 ( s5 )
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sw t7, 104 ( s5 )
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sw t6, 100 ( s5 )
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sw t5, 96 ( s5 )
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sw t4, 92 ( s5 )
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sw t3, 88 ( s5 )
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sw t2, 84 ( s5 )
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sw t1, 80 ( s5 )
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sw t0, 76 ( s5 )
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sw a3, 72 ( s5 )
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sw a2, 68 ( s5 )
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sw a1, 64 ( s5 )
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sw a0, 60 ( s5 )
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sw v1, 56 ( s5 )
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sw v0, 52 ( s5 )
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sw s6, portEPC_STACK_LOCATION( s5 )
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sw $1, 16 ( s5 )
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/* MEC14xx does not have DSP, removed 7 words */
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mfhi s6
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sw s6, 12(s5)
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mflo s6
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sw s6, 8(s5)
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/* MEC14xx does not have DSP, removed 7 words */
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mfhi s6
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sw s6, 12 ( s5 )
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mflo s6
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sw s6, 8 ( s5 )
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/* Update the task stack pointer value if nesting is zero. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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addiu s6, s6, -1
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bne s6, zero, 1f
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/* Update the task stack pointer value if nesting is zero. */
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la s6, uxInterruptNesting
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lw s6, ( s6 )
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addiu s6, s6, -1
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bne s6, zero, 1f
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nop
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/* Save the stack pointer. */
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la s6, uxSavedTaskStackPointer
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sw s5, (s6)
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1:
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/* Save the stack pointer. */
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la s6, uxSavedTaskStackPointer
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sw s5, ( s6 )
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1 :
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.endm
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/******************************************************************/
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.macro portRESTORE_CONTEXT
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.macro portRESTORE_CONTEXT
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/* Restore the stack pointer from the TCB. This is only done if the
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nesting count is 1. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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addiu s6, s6, -1
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bne s6, zero, 1f
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/* Restore the stack pointer from the TCB. This is only done if the
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* nesting count is 1. */
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la s6, uxInterruptNesting
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lw s6, ( s6 )
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addiu s6, s6, -1
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bne s6, zero, 1f
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nop
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la s6, uxSavedTaskStackPointer
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lw s5, (s6)
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la s6, uxSavedTaskStackPointer
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lw s5, ( s6 )
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/* Restore the context.
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MCHP MEC14xx does not include DSP */
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1:
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lw s6, 8(s5)
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mtlo s6
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lw s6, 12(s5)
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mthi s6
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lw $1, 16(s5)
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/* Restore the context.
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* MCHP MEC14xx does not include DSP */
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1 :
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lw s6, 8 ( s5 )
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mtlo s6
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lw s6, 12 ( s5 )
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mthi s6
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lw $1, 16 ( s5 )
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/* s6 is loaded as it was used as a scratch register and therefore saved
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as part of the interrupt context. */
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lw s6, 44(s5)
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lw v0, 52(s5)
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lw v1, 56(s5)
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lw a0, 60(s5)
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lw a1, 64(s5)
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lw a2, 68(s5)
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lw a3, 72(s5)
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lw t0, 76(s5)
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lw t1, 80(s5)
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lw t2, 84(s5)
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lw t3, 88(s5)
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lw t4, 92(s5)
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lw t5, 96(s5)
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lw t6, 100(s5)
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lw t7, 104(s5)
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lw t8, 108(s5)
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lw t9, 112(s5)
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lw s8, 116(s5)
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lw ra, 120(s5)
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/* s6 is loaded as it was used as a scratch register and therefore saved
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* as part of the interrupt context. */
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lw s6, 44 ( s5 )
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lw v0, 52 ( s5 )
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lw v1, 56 ( s5 )
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lw a0, 60 ( s5 )
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lw a1, 64 ( s5 )
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lw a2, 68 ( s5 )
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lw a3, 72 ( s5 )
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lw t0, 76 ( s5 )
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lw t1, 80 ( s5 )
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lw t2, 84 ( s5 )
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lw t3, 88 ( s5 )
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lw t4, 92 ( s5 )
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lw t5, 96 ( s5 )
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lw t6, 100 ( s5 )
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lw t7, 104 ( s5 )
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lw t8, 108 ( s5 )
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lw t9, 112 ( s5 )
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lw s8, 116 ( s5 )
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lw ra, 120 ( s5 )
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/* Protect access to the k registers, and others. */
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/* Protect access to the k registers, and others. */
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di
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ehb
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/* Decrement the nesting count. */
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la k0, uxInterruptNesting
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lw k1, (k0)
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addiu k1, k1, -1
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sw k1, 0(k0)
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/* Decrement the nesting count. */
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la k0, uxInterruptNesting
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lw k1, ( k0 )
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addiu k1, k1, -1
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sw k1, 0 ( k0 )
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lw k0, portSTATUS_STACK_LOCATION(s5)
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lw k1, portEPC_STACK_LOCATION(s5)
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lw k0, portSTATUS_STACK_LOCATION( s5 )
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lw k1, portEPC_STACK_LOCATION( s5 )
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/* Leave the stack in its original state. First load sp from s5, then
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restore s5 from the stack. */
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add sp, zero, s5
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lw s5, 40(sp)
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addiu sp, sp, portCONTEXT_SIZE
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/* Leave the stack in its original state. First load sp from s5, then
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* restore s5 from the stack. */
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add sp, zero, s5
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lw s5, 40 ( sp )
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addiu sp, sp, portCONTEXT_SIZE
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mtc0 k0, _CP0_STATUS
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mtc0 k1, _CP0_EPC
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mtc0 k0, _CP0_STATUS
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mtc0 k1, _CP0_EPC
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ehb
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eret
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nop
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.endm
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.endm
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#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
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@ -27,8 +27,8 @@
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the PIC32MEC14xx port.
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*----------------------------------------------------------*/
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* Implementation of functions defined in portable.h for the PIC32MEC14xx port.
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*----------------------------------------------------------*/
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/* Scheduler include files. */
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#include "FreeRTOS.h"
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@ -38,57 +38,57 @@
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#include <xc.h>
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#include <cp0defs.h>
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#if !defined(__MEC__)
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#if !defined( __MEC__ )
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#error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.
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#endif
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#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
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#if ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
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#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
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#endif
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/* Bits within various registers. */
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#define portIE_BIT ( 0x00000001 )
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#define portEXL_BIT ( 0x00000002 )
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#define portIE_BIT ( 0x00000001 )
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#define portEXL_BIT ( 0x00000002 )
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/* The EXL bit is set to ensure interrupts do not occur while the context of
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the first task is being restored. MEC14xx does not have DSP HW. */
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#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
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* the first task is being restored. MEC14xx does not have DSP HW. */
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#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
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/* MEC14xx RTOS Timer MMCR's. */
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#define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul))
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#define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul))
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#define portMMCR_RTMR_PRELOAD *( ( volatile uint32_t * ) ( 0xA0007404ul ) )
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#define portMMCR_RTMR_CONTROL *( ( volatile uint32_t * ) ( 0xA0007408ul ) )
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/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
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peripheral space. */
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#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
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#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
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#define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))
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#define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul))
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#define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))
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* peripheral space. */
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#define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
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#define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
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#define portMMCR_JTVIC_GIRQ23_SRC *( ( volatile uint32_t * ) ( 0xBFFFC0F0ul ) )
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#define portMMCR_JTVIC_GIRQ23_SETEN *( ( volatile uint32_t * ) ( 0xBFFFC0F4ul ) )
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#define portMMCR_JTVIC_GIRQ23_PRIA *( ( volatile uint32_t * ) ( 0xBFFFC3F0ul ) )
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/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
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#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
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#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
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#define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul))
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#define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul))
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#define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul))
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#define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
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#define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
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#define portMMCR_JTVIC_GIRQ24_SRC *( ( volatile uint32_t * ) ( 0xBFFFC100ul ) )
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#define portMMCR_JTVIC_GIRQ24_SETEN *( ( volatile uint32_t * ) ( 0xBFFFC104ul ) )
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#define portMMCR_JTVIC_GIRQ24_PRIA *( ( volatile uint32_t * ) ( 0xBFFFC400ul ) )
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/*
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By default port.c generates its tick interrupt from the RTOS timer. The user
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can override this behaviour by:
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1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
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which is the function that configures the timer. The function is defined
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as a weak symbol in this file so if the same function name is used in the
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application code then the version in the application code will be linked
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into the application in preference to the version defined in this file.
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2: Provide a vector implementation in port_asm.S that overrides the default
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behaviour for the specified interrupt vector.
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3: Specify the correct bit to clear the interrupt during the timer interrupt
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handler.
|
||||
*/
|
||||
* By default port.c generates its tick interrupt from the RTOS timer. The user
|
||||
* can override this behaviour by:
|
||||
* 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
|
||||
* which is the function that configures the timer. The function is defined
|
||||
* as a weak symbol in this file so if the same function name is used in the
|
||||
* application code then the version in the application code will be linked
|
||||
* into the application in preference to the version defined in this file.
|
||||
* 2: Provide a vector implementation in port_asm.S that overrides the default
|
||||
* behaviour for the specified interrupt vector.
|
||||
* 3: Specify the correct bit to clear the interrupt during the timer interrupt
|
||||
* handler.
|
||||
*/
|
||||
#ifndef configTICK_INTERRUPT_VECTOR
|
||||
#define configTICK_INTERRUPT_VECTOR girq23_b4
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
|
||||
#define configTICK_INTERRUPT_VECTOR girq23_b4
|
||||
#define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
|
||||
#else
|
||||
#ifndef configCLEAR_TICK_TIMER_INTERRUPT
|
||||
#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
|
||||
|
|
@ -96,34 +96,36 @@ can override this behaviour by:
|
|||
#endif
|
||||
|
||||
/* Let the user override the pre-loading of the initial RA with the address of
|
||||
prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
|
||||
in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
* prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
|
||||
* in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
|
||||
#ifdef configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||
#else
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||
#endif
|
||||
|
||||
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
stack overflow hook function (because the stack overflow hook is specific to a
|
||||
task stack, not the ISR stack). */
|
||||
#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
* stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||
* stack overflow hook function (because the stack overflow hook is specific to a
|
||||
* task stack, not the ISR stack). */
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
the task stacks, and so will legitimately appear in many positions within
|
||||
the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
|
||||
* the task stacks, and so will legitimately appear in many positions within
|
||||
* the ISR stack. */
|
||||
#define portISR_STACK_FILL_BYTE 0xee
|
||||
|
||||
static const uint8_t ucExpectedStackBytes[] = {
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||
static const uint8_t ucExpectedStackBytes[] =
|
||||
{
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE
|
||||
}; \
|
||||
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else
|
||||
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||
#else /* if ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
|
||||
/* Define the function away. */
|
||||
#define portCHECK_ISR_STACK()
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
|
@ -139,7 +141,7 @@ static void prvTaskExitError( void );
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Records the interrupt nesting depth. This is initialised to one as it is
|
||||
decremented to 0 when the first task starts. */
|
||||
* decremented to 0 when the first task starts. */
|
||||
volatile UBaseType_t uxInterruptNesting = 0x01;
|
||||
|
||||
/* Stores the task stack pointer when a switch is made to use the system stack. */
|
||||
|
|
@ -149,7 +151,7 @@ UBaseType_t uxSavedTaskStackPointer = 0;
|
|||
StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
|
||||
|
||||
/* The top of stack value ensures there is enough space to store 6 registers on
|
||||
the callers stack, as some functions seem to want to do this. */
|
||||
* the callers stack, as some functions seem to want to do this. */
|
||||
const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -157,30 +159,32 @@ const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7
|
|||
/*
|
||||
* See header file for description.
|
||||
*/
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
||||
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||
TaskFunction_t pxCode,
|
||||
void * pvParameters )
|
||||
{
|
||||
/* Ensure byte alignment is maintained when leaving this function. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) 0xDEADBEEF;
|
||||
*pxTopOfStack = ( StackType_t ) 0xDEADBEEF;
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
*pxTopOfStack = ( StackType_t ) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
|
||||
*pxTopOfStack = ( StackType_t ) ulPortGetCP0Cause();
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */
|
||||
*pxTopOfStack = ( StackType_t ) portINITIAL_SR; /* CP0_STATUS */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
|
||||
*pxTopOfStack = ( StackType_t ) pxCode; /* CP0_EPC */
|
||||
pxTopOfStack--;
|
||||
|
||||
*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
|
||||
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* ra */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
|
||||
*pxTopOfStack = ( StackType_t ) pvParameters; /* Parameters to pass in. */
|
||||
pxTopOfStack -= 15;
|
||||
|
||||
return pxTopOfStack;
|
||||
|
|
@ -189,9 +193,10 @@ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t px
|
|||
|
||||
static __inline uint32_t prvDisableInterrupt( void )
|
||||
{
|
||||
uint32_t prev_state;
|
||||
uint32_t prev_state;
|
||||
|
||||
__asm volatile ( "di %0; ehb" : "=r" ( prev_state )::"memory" );
|
||||
|
||||
__asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
|
||||
return prev_state;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
@ -199,14 +204,17 @@ uint32_t prev_state;
|
|||
static void prvTaskExitError( void )
|
||||
{
|
||||
/* A function that implements a task must not exit or attempt to return to
|
||||
its caller as there is nothing to return to. If a task wants to exit it
|
||||
should instead call vTaskDelete( NULL ).
|
||||
|
||||
Artificially force an assert() to be triggered if configASSERT() is
|
||||
defined, then stop here so application writers can catch the error. */
|
||||
* its caller as there is nothing to return to. If a task wants to exit it
|
||||
* should instead call vTaskDelete( NULL ).
|
||||
*
|
||||
* Artificially force an assert() to be triggered if configASSERT() is
|
||||
* defined, then stop here so application writers can catch the error. */
|
||||
configASSERT( uxSavedTaskStackPointer == 0UL );
|
||||
portDISABLE_INTERRUPTS();
|
||||
for( ;; );
|
||||
|
||||
for( ; ; )
|
||||
{
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
|
@ -218,10 +226,10 @@ static void prvTaskExitError( void )
|
|||
* ensure the RTOS provided tick interrupt handler is installed on the correct
|
||||
* vector number.
|
||||
*/
|
||||
__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
|
||||
__attribute__( ( weak ) ) void vApplicationSetupTickTimerInterrupt( void )
|
||||
{
|
||||
/* MEC14xx RTOS Timer whose input clock is 32KHz. */
|
||||
const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
|
||||
const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
|
||||
|
||||
configASSERT( ulPreload != 0UL );
|
||||
|
||||
|
|
@ -240,18 +248,18 @@ const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
|
|||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortEndScheduler(void)
|
||||
void vPortEndScheduler( void )
|
||||
{
|
||||
/* Not implemented in ports where there is nothing to return to.
|
||||
Artificially force an assert. */
|
||||
* Artificially force an assert. */
|
||||
configASSERT( uxInterruptNesting == 1000UL );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPortStartScheduler( void )
|
||||
{
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void *pxCurrentTCB;
|
||||
extern void vPortStartFirstTask( void );
|
||||
extern void * pxCurrentTCB;
|
||||
|
||||
#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||
{
|
||||
|
|
@ -261,29 +269,29 @@ extern void *pxCurrentTCB;
|
|||
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||
|
||||
/* Clear the software interrupt flag. */
|
||||
portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
|
||||
portMMCR_JTVIC_GIRQ24_SRC = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
|
||||
|
||||
/* Set software timer priority. Each GIRQn has one nibble containing its
|
||||
priority */
|
||||
portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
|
||||
* priority */
|
||||
portMMCR_JTVIC_GIRQ24_PRIA &= ~( 0xF0ul );
|
||||
portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
|
||||
|
||||
/* Enable software interrupt. */
|
||||
portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
|
||||
|
||||
/* Setup the timer to generate the tick. Interrupts will have been disabled
|
||||
by the time we get here. */
|
||||
* by the time we get here. */
|
||||
vApplicationSetupTickTimerInterrupt();
|
||||
|
||||
/* Start the highest priority task that has been created so far. Its stack
|
||||
location is loaded into uxSavedTaskStackPointer. */
|
||||
* location is loaded into uxSavedTaskStackPointer. */
|
||||
uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
|
||||
vPortStartFirstTask();
|
||||
|
||||
/* Should never get here as the tasks will now be executing! Call the task
|
||||
exit error function to prevent compiler warnings about a static function
|
||||
not being called in the case that the application writer overrides this
|
||||
functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
* exit error function to prevent compiler warnings about a static function
|
||||
* not being called in the case that the application writer overrides this
|
||||
* functionality by defining configTASK_RETURN_ADDRESS. */
|
||||
prvTaskExitError();
|
||||
|
||||
return pdFALSE;
|
||||
|
|
@ -292,8 +300,8 @@ extern void *pxCurrentTCB;
|
|||
|
||||
void vPortIncrementTick( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatus;
|
||||
uint32_t ulCause;
|
||||
UBaseType_t uxSavedStatus;
|
||||
uint32_t ulCause;
|
||||
|
||||
uxSavedStatus = uxPortSetInterruptMaskFromISR();
|
||||
{
|
||||
|
|
@ -317,17 +325,17 @@ uint32_t ulCause;
|
|||
|
||||
UBaseType_t uxPortSetInterruptMaskFromISR( void )
|
||||
{
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
UBaseType_t uxSavedStatusRegister;
|
||||
|
||||
prvDisableInterrupt();
|
||||
uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
from an interrupt that has a priority above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
can only result in the IPL being unchanged or raised, and therefore never
|
||||
lowered. */
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
|
||||
* from an interrupt that has a priority above
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
|
||||
* can only result in the IPL being unchanged or raised, and therefore never
|
||||
* lowered. */
|
||||
vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
|
||||
|
||||
return uxSavedStatusRegister;
|
||||
|
|
|
|||
|
|
@ -46,23 +46,23 @@
|
|||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE uint32_t
|
||||
#define portBASE_TYPE long
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef long BaseType_t;
|
||||
typedef unsigned long UBaseType_t;
|
||||
|
||||
#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
|
||||
typedef uint32_t TickType_t;
|
||||
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
|
||||
typedef uint16_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffff
|
||||
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
|
||||
typedef uint32_t TickType_t;
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#else
|
||||
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
|
||||
|
|
@ -70,15 +70,16 @@ typedef unsigned long UBaseType_t;
|
|||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portBYTE_ALIGNMENT 8
|
||||
#define portSTACK_GROWTH -1
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portIPL_SHIFT ( 10UL )
|
||||
|
||||
/* Don't straddle the CEE bit. Interrupts calling FreeRTOS functions should
|
||||
never have higher IPL bits set anyway. */
|
||||
* never have higher IPL bits set anyway. */
|
||||
#define portALL_IPL_BITS ( 0x7FUL << portIPL_SHIFT )
|
||||
#define portSW0_BIT ( 0x01 << 8 )
|
||||
|
||||
|
|
@ -90,38 +91,38 @@ never have higher IPL bits set anyway. */
|
|||
|
||||
static inline uint32_t ulPortGetCP0Status( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
uint32_t rv;
|
||||
|
||||
__asm volatile(
|
||||
"\n\t"
|
||||
"mfc0 %0,$12,0 \n\t"
|
||||
: "=r" ( rv ) :: );
|
||||
__asm volatile (
|
||||
"\n\t"
|
||||
"mfc0 %0,$12,0 \n\t"
|
||||
: "=r" ( rv )::);
|
||||
|
||||
return rv;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline void vPortSetCP0Status( uint32_t new_status)
|
||||
static inline void vPortSetCP0Status( uint32_t new_status )
|
||||
{
|
||||
( void ) new_status;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"\n\t"
|
||||
"mtc0 %0,$12,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
:"r" ( new_status ) : );
|
||||
__asm__ __volatile__ (
|
||||
"\n\t"
|
||||
"mtc0 %0,$12,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
: "r" ( new_status ) : );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static inline uint32_t ulPortGetCP0Cause( void )
|
||||
{
|
||||
uint32_t rv;
|
||||
uint32_t rv;
|
||||
|
||||
__asm volatile(
|
||||
"\n\t"
|
||||
"mfc0 %0,$13,0 \n\t"
|
||||
: "=r" ( rv ) :: );
|
||||
__asm volatile (
|
||||
"\n\t"
|
||||
"mfc0 %0,$13,0 \n\t"
|
||||
: "=r" ( rv )::);
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
|
@ -131,86 +132,86 @@ static inline void vPortSetCP0Cause( uint32_t new_cause )
|
|||
{
|
||||
( void ) new_cause;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"\n\t"
|
||||
"mtc0 %0,$13,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
:"r" ( new_cause ) : );
|
||||
__asm__ __volatile__ (
|
||||
"\n\t"
|
||||
"mtc0 %0,$13,0 \n\t"
|
||||
"ehb \n\t"
|
||||
:
|
||||
: "r" ( new_cause ) : );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* This clears the IPL bits, then sets them to
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
* configMAX_SYSCALL_INTERRUPT_PRIORITY. An extra check is performed if
|
||||
* configASSERT() is defined to ensure an assertion handler does not inadvertently
|
||||
* attempt to lower the IPL when the call to assert was triggered because the IPL
|
||||
* value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
|
||||
* safe FreeRTOS API function was executed. ISR safe FreeRTOS API functions are
|
||||
* those that end in FromISR. FreeRTOS maintains a separate interrupt API to
|
||||
* ensure API function and interrupt entry is as fast and as simple as possible. */
|
||||
#ifdef configASSERT
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ \
|
||||
if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
|
||||
{ \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
} \
|
||||
}
|
||||
#else /* configASSERT */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Mask interrupts at and below the kernel interrupt priority. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
|
||||
}
|
||||
#endif /* configASSERT */
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ulStatus ); \
|
||||
}
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ \
|
||||
uint32_t ulStatus; \
|
||||
/* Unmask all interrupts. */ \
|
||||
ulStatus = ulPortGetCP0Status(); \
|
||||
ulStatus &= ~portALL_IPL_BITS; \
|
||||
vPortSetCP0Status( ulStatus ); \
|
||||
}
|
||||
|
||||
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
#define portCRITICAL_NESTING_IN_TCB 1
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
|
||||
extern UBaseType_t uxPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
|
||||
|
||||
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||
#endif
|
||||
|
||||
#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
|
||||
|
||||
/* Check the configuration. */
|
||||
#if( configMAX_PRIORITIES > 32 )
|
||||
/* Check the configuration. */
|
||||
#if ( configMAX_PRIORITIES > 32 )
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||
#endif
|
||||
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
/* Store/clear the ready priorities in a bit map. */
|
||||
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
|
||||
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
|
||||
|
||||
#endif /* taskRECORD_READY_PRIORITY */
|
||||
|
||||
|
|
@ -218,28 +219,28 @@ extern void vPortClearInterruptMaskFromISR( UBaseType_t );
|
|||
|
||||
/* Task utilities. */
|
||||
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = ulPortGetCP0Cause(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
vPortSetCP0Cause( ulCause ); \
|
||||
}
|
||||
#define portYIELD() \
|
||||
{ \
|
||||
uint32_t ulCause; \
|
||||
/* Trigger software interrupt. */ \
|
||||
ulCause = ulPortGetCP0Cause(); \
|
||||
ulCause |= portSW0_BIT; \
|
||||
vPortSetCP0Cause( ulCause ); \
|
||||
}
|
||||
|
||||
extern volatile UBaseType_t uxInterruptNesting;
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
|
||||
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
#define portNOP() __asm volatile ( "nop" )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) __attribute__( ( noreturn ) )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) { portYIELD(); } } while( 0 )
|
||||
|
||||
/* Required by the kernel aware debugger. */
|
||||
#ifdef __DEBUG
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue