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CI-CD Updates (#768)
* Use new version of CI-CD Actions * Use cSpell spell check, and use ubuntu-20.04 for formatting check * Format and spell check all files in the portable directory * Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /* * Use checkout@v3 instead of checkout@v2 on all jobs ---------
This commit is contained in:
Soren Ptak
GitHub
parent
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commit
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485 changed files with 108790 additions and 107581 deletions
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@ -30,13 +30,13 @@
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#define PORTCONTEXT_H
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#if __riscv_xlen == 64
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#define portWORD_SIZE 8
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#define store_x sd
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#define load_x ld
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#define portWORD_SIZE 8
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#define store_x sd
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#define load_x ld
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#elif __riscv_xlen == 32
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#define store_x sw
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#define load_x lw
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#define portWORD_SIZE 4
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#define store_x sw
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#define load_x lw
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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@ -49,36 +49,36 @@
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* specific version of freertos_risc_v_chip_specific_extensions.h. See the
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* notes at the top of portASM.S file. */
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#ifdef __riscv_32e
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#define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 13
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#define portMSTATUS_OFFSET 14
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#define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 13
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#define portMSTATUS_OFFSET 14
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#else
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#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 29
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#define portMSTATUS_OFFSET 30
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#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 29
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#define portMSTATUS_OFFSET 30
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#endif
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EXTERN pxCurrentTCB
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EXTERN xISRStackTop
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EXTERN xCriticalNesting
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EXTERN pxCriticalNesting
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EXTERN pxCurrentTCB
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EXTERN xISRStackTop
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EXTERN xCriticalNesting
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EXTERN pxCriticalNesting
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/*-----------------------------------------------------------*/
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portcontextSAVE_CONTEXT_INTERNAL MACRO
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 1 * portWORD_SIZE( sp )
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store_x x5, 2 * portWORD_SIZE( sp )
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store_x x6, 3 * portWORD_SIZE( sp )
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store_x x7, 4 * portWORD_SIZE( sp )
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store_x x8, 5 * portWORD_SIZE( sp )
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store_x x9, 6 * portWORD_SIZE( sp )
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store_x x10, 7 * portWORD_SIZE( sp )
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store_x x11, 8 * portWORD_SIZE( sp )
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store_x x12, 9 * portWORD_SIZE( sp )
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store_x x13, 10 * portWORD_SIZE( sp )
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store_x x14, 11 * portWORD_SIZE( sp )
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store_x x15, 12 * portWORD_SIZE( sp )
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 1 * portWORD_SIZE( sp )
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store_x x5, 2 * portWORD_SIZE( sp )
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store_x x6, 3 * portWORD_SIZE( sp )
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store_x x7, 4 * portWORD_SIZE( sp )
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store_x x8, 5 * portWORD_SIZE( sp )
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store_x x9, 6 * portWORD_SIZE( sp )
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store_x x10, 7 * portWORD_SIZE( sp )
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store_x x11, 8 * portWORD_SIZE( sp )
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store_x x12, 9 * portWORD_SIZE( sp )
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store_x x13, 10 * portWORD_SIZE( sp )
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store_x x14, 11 * portWORD_SIZE( sp )
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store_x x15, 12 * portWORD_SIZE( sp )
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#ifndef __riscv_32e
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store_x x16, 13 * portWORD_SIZE( sp )
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store_x x17, 14 * portWORD_SIZE( sp )
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@ -96,94 +96,94 @@ portcontextSAVE_CONTEXT_INTERNAL MACRO
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store_x x29, 26 * portWORD_SIZE( sp )
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store_x x30, 27 * portWORD_SIZE( sp )
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store_x x31, 28 * portWORD_SIZE( sp )
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#endif
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#endif /* ifndef __riscv_32e */
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load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
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store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
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load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
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store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
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csrr t0, mstatus /* Required for MPIE bit. */
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store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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csrr t0, mstatus /* Required for MPIE bit. */
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store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
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store_x sp, 0( t0 ) /* Write sp to first TCB member. */
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load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
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store_x sp, 0 ( t0 ) /* Write sp to first TCB member. */
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ENDM
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ENDM
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/*-----------------------------------------------------------*/
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portcontextSAVE_EXCEPTION_CONTEXT MACRO
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
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store_x a1, 0( sp ) /* Save updated exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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ENDM
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
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store_x a1, 0 ( sp ) /* Save updated exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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ENDM
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/*-----------------------------------------------------------*/
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portcontextSAVE_INTERRUPT_CONTEXT MACRO
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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ENDM
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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store_x a1, 0 ( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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ENDM
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/*-----------------------------------------------------------*/
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portcontextRESTORE_CONTEXT MACRO
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load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0( t1 ) /* Read sp from first TCB member. */
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load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0 ( t1 ) /* Read sp from first TCB member. */
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/* Load mepc with the address of the instruction in the task to run next. */
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load_x t0, 0( sp )
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csrw mepc, t0
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/* Load mepc with the address of the instruction in the task to run next. */
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load_x t0, 0 ( sp )
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csrw mepc, t0
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/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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portasmRESTORE_ADDITIONAL_REGISTERS
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/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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portasmRESTORE_ADDITIONAL_REGISTERS
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/* Load mstatus with the interrupt enable bits used by the task. */
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load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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/* Load mstatus with the interrupt enable bits used by the task. */
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load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
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load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
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store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */
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load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
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load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
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store_x t0, 0 ( t1 ) /* Restore the critical nesting value for this task. */
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load_x x1, 1 * portWORD_SIZE( sp )
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load_x x5, 2 * portWORD_SIZE( sp )
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load_x x6, 3 * portWORD_SIZE( sp )
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load_x x7, 4 * portWORD_SIZE( sp )
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load_x x8, 5 * portWORD_SIZE( sp )
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load_x x9, 6 * portWORD_SIZE( sp )
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load_x x10, 7 * portWORD_SIZE( sp )
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load_x x11, 8 * portWORD_SIZE( sp )
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load_x x12, 9 * portWORD_SIZE( sp )
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load_x x13, 10 * portWORD_SIZE( sp )
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load_x x14, 11 * portWORD_SIZE( sp )
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load_x x15, 12 * portWORD_SIZE( sp )
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load_x x1, 1 * portWORD_SIZE( sp )
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load_x x5, 2 * portWORD_SIZE( sp )
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load_x x6, 3 * portWORD_SIZE( sp )
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load_x x7, 4 * portWORD_SIZE( sp )
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load_x x8, 5 * portWORD_SIZE( sp )
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load_x x9, 6 * portWORD_SIZE( sp )
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load_x x10, 7 * portWORD_SIZE( sp )
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load_x x11, 8 * portWORD_SIZE( sp )
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load_x x12, 9 * portWORD_SIZE( sp )
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load_x x13, 10 * portWORD_SIZE( sp )
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load_x x14, 11 * portWORD_SIZE( sp )
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load_x x15, 12 * portWORD_SIZE( sp )
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#ifndef __riscv_32e
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load_x x16, 13 * portWORD_SIZE( sp )
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load_x x17, 14 * portWORD_SIZE( sp )
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load_x x18, 15 * portWORD_SIZE( sp )
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load_x x19, 16 * portWORD_SIZE( sp )
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load_x x20, 17 * portWORD_SIZE( sp )
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load_x x21, 18 * portWORD_SIZE( sp )
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load_x x22, 19 * portWORD_SIZE( sp )
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load_x x23, 20 * portWORD_SIZE( sp )
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load_x x24, 21 * portWORD_SIZE( sp )
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load_x x25, 22 * portWORD_SIZE( sp )
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load_x x26, 23 * portWORD_SIZE( sp )
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load_x x27, 24 * portWORD_SIZE( sp )
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load_x x28, 25 * portWORD_SIZE( sp )
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load_x x29, 26 * portWORD_SIZE( sp )
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load_x x30, 27 * portWORD_SIZE( sp )
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load_x x31, 28 * portWORD_SIZE( sp )
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#endif
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addi sp, sp, portCONTEXT_SIZE
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load_x x16, 13 * portWORD_SIZE( sp )
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load_x x17, 14 * portWORD_SIZE( sp )
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load_x x18, 15 * portWORD_SIZE( sp )
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load_x x19, 16 * portWORD_SIZE( sp )
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load_x x20, 17 * portWORD_SIZE( sp )
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load_x x21, 18 * portWORD_SIZE( sp )
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load_x x22, 19 * portWORD_SIZE( sp )
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load_x x23, 20 * portWORD_SIZE( sp )
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load_x x24, 21 * portWORD_SIZE( sp )
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load_x x25, 22 * portWORD_SIZE( sp )
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load_x x26, 23 * portWORD_SIZE( sp )
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load_x x27, 24 * portWORD_SIZE( sp )
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load_x x28, 25 * portWORD_SIZE( sp )
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load_x x29, 26 * portWORD_SIZE( sp )
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load_x x30, 27 * portWORD_SIZE( sp )
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load_x x31, 28 * portWORD_SIZE( sp )
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#endif /* ifndef __riscv_32e */
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addi sp, sp, portCONTEXT_SIZE
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mret
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ENDM
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mret
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ENDM
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/*-----------------------------------------------------------*/
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#endif /* PORTCONTEXT_H */
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