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CI-CD Updates (#768)
* Use new version of CI-CD Actions * Use cSpell spell check, and use ubuntu-20.04 for formatting check * Format and spell check all files in the portable directory * Remove the https:// from #errors and #warnings as uncrustify attempts to change it to /* * Use checkout@v3 instead of checkout@v2 on all jobs ---------
This commit is contained in:
Soren Ptak
GitHub
parent
d6bccb1f4c
commit
5fb9b50da8
485 changed files with 108790 additions and 107581 deletions
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@ -54,16 +54,16 @@
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_SIFIVE_CLINT 1
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#define portasmHAS_MTIME 1
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#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
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#define portasmHAS_SIFIVE_CLINT 1
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#define portasmHAS_MTIME 1
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#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
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portasmSAVE_ADDITIONAL_REGISTERS MACRO
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/* No additional registers to save, so this macro does nothing. */
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ENDM
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/* No additional registers to save, so this macro does nothing. */
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ENDM
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portasmRESTORE_ADDITIONAL_REGISTERS MACRO
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/* No additional registers to restore, so this macro does nothing. */
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/* No additional registers to restore, so this macro does nothing. */
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ENDM
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -39,15 +39,15 @@
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#include "string.h"
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#ifdef configCLINT_BASE_ADDRESS
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#warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */
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#warning "The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS directly in place of configCLINT_BASE_ADDRESS. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
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#endif
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#ifndef configMTIME_BASE_ADDRESS
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#warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */
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#warning "configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
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#endif
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#ifndef configMTIMECMP_BASE_ADDRESS
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#warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https: /*www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html */
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#warning "configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
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#endif
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/* Let the user override the pre-loading of the initial LR with the address of
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@ -70,7 +70,7 @@
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static __attribute__( ( aligned( 16 ) ) ) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
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const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
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/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
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/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
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* the task stacks, and so will legitimately appear in many positions within
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* the ISR stack. */
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#define portISR_STACK_FILL_BYTE 0xee
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@ -114,7 +114,7 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
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* the stack overflow hook function (because the stack overflow hook is specific
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* to a task stack, not the ISR stack). */
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#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
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#warning This path not tested, or even compiled yet.
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#warning "This path not tested, or even compiled yet."
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static const uint8_t ucExpectedStackBytes[] =
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{
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@ -126,7 +126,7 @@ size_t xTaskReturnAddress = ( size_t ) portTASK_RETURN_ADDRESS;
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}; \
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#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
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#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
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#else /* if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 ) */
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/* Define the function away. */
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#define portCHECK_ISR_STACK()
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#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
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@ -167,7 +167,7 @@ static void prvTaskExitError( void )
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volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS );
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volatile uint32_t ulHartId;
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__asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is hartid. */
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__asm volatile ( "csrr %0, 0xf14" : "=r" ( ulHartId ) ); /* 0xf14 is HART ID. */
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pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
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@ -30,13 +30,13 @@
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#define PORTCONTEXT_H
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#if __riscv_xlen == 64
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#define portWORD_SIZE 8
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#define store_x sd
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#define load_x ld
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#define portWORD_SIZE 8
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#define store_x sd
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#define load_x ld
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#elif __riscv_xlen == 32
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#define store_x sw
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#define load_x lw
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#define portWORD_SIZE 4
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#define store_x sw
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#define load_x lw
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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@ -49,36 +49,36 @@
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* specific version of freertos_risc_v_chip_specific_extensions.h. See the
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* notes at the top of portASM.S file. */
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#ifdef __riscv_32e
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#define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 13
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#define portMSTATUS_OFFSET 14
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#define portCONTEXT_SIZE ( 15 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 13
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#define portMSTATUS_OFFSET 14
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#else
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#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 29
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#define portMSTATUS_OFFSET 30
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#define portCONTEXT_SIZE ( 31 * portWORD_SIZE )
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#define portCRITICAL_NESTING_OFFSET 29
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#define portMSTATUS_OFFSET 30
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#endif
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EXTERN pxCurrentTCB
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EXTERN xISRStackTop
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EXTERN xCriticalNesting
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EXTERN pxCriticalNesting
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EXTERN pxCurrentTCB
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EXTERN xISRStackTop
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EXTERN xCriticalNesting
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EXTERN pxCriticalNesting
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/*-----------------------------------------------------------*/
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portcontextSAVE_CONTEXT_INTERNAL MACRO
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 1 * portWORD_SIZE( sp )
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store_x x5, 2 * portWORD_SIZE( sp )
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store_x x6, 3 * portWORD_SIZE( sp )
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store_x x7, 4 * portWORD_SIZE( sp )
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store_x x8, 5 * portWORD_SIZE( sp )
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store_x x9, 6 * portWORD_SIZE( sp )
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store_x x10, 7 * portWORD_SIZE( sp )
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store_x x11, 8 * portWORD_SIZE( sp )
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store_x x12, 9 * portWORD_SIZE( sp )
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store_x x13, 10 * portWORD_SIZE( sp )
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store_x x14, 11 * portWORD_SIZE( sp )
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store_x x15, 12 * portWORD_SIZE( sp )
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addi sp, sp, -portCONTEXT_SIZE
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store_x x1, 1 * portWORD_SIZE( sp )
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store_x x5, 2 * portWORD_SIZE( sp )
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store_x x6, 3 * portWORD_SIZE( sp )
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store_x x7, 4 * portWORD_SIZE( sp )
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store_x x8, 5 * portWORD_SIZE( sp )
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store_x x9, 6 * portWORD_SIZE( sp )
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store_x x10, 7 * portWORD_SIZE( sp )
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store_x x11, 8 * portWORD_SIZE( sp )
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store_x x12, 9 * portWORD_SIZE( sp )
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store_x x13, 10 * portWORD_SIZE( sp )
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store_x x14, 11 * portWORD_SIZE( sp )
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store_x x15, 12 * portWORD_SIZE( sp )
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#ifndef __riscv_32e
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store_x x16, 13 * portWORD_SIZE( sp )
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store_x x17, 14 * portWORD_SIZE( sp )
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@ -96,94 +96,94 @@ portcontextSAVE_CONTEXT_INTERNAL MACRO
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store_x x29, 26 * portWORD_SIZE( sp )
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store_x x30, 27 * portWORD_SIZE( sp )
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store_x x31, 28 * portWORD_SIZE( sp )
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#endif
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#endif /* ifndef __riscv_32e */
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load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
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store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
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load_x t0, xCriticalNesting /* Load the value of xCriticalNesting into t0. */
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store_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Store the critical nesting value to the stack. */
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csrr t0, mstatus /* Required for MPIE bit. */
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store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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csrr t0, mstatus /* Required for MPIE bit. */
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store_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
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store_x sp, 0( t0 ) /* Write sp to first TCB member. */
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load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
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store_x sp, 0 ( t0 ) /* Write sp to first TCB member. */
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ENDM
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ENDM
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/*-----------------------------------------------------------*/
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portcontextSAVE_EXCEPTION_CONTEXT MACRO
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
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store_x a1, 0( sp ) /* Save updated exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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ENDM
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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addi a1, a1, 4 /* Synchronous so update exception return address to the instruction after the instruction that generated the exception. */
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store_x a1, 0 ( sp ) /* Save updated exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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ENDM
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/*-----------------------------------------------------------*/
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portcontextSAVE_INTERRUPT_CONTEXT MACRO
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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store_x a1, 0( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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ENDM
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portcontextSAVE_CONTEXT_INTERNAL
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csrr a0, mcause
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csrr a1, mepc
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store_x a1, 0 ( sp ) /* Asynchronous interrupt so save unmodified exception return address. */
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load_x sp, xISRStackTop /* Switch to ISR stack. */
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ENDM
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/*-----------------------------------------------------------*/
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portcontextRESTORE_CONTEXT MACRO
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load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0( t1 ) /* Read sp from first TCB member. */
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load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
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load_x sp, 0 ( t1 ) /* Read sp from first TCB member. */
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/* Load mepc with the address of the instruction in the task to run next. */
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load_x t0, 0( sp )
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csrw mepc, t0
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/* Load mepc with the address of the instruction in the task to run next. */
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load_x t0, 0 ( sp )
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csrw mepc, t0
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/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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portasmRESTORE_ADDITIONAL_REGISTERS
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/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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portasmRESTORE_ADDITIONAL_REGISTERS
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/* Load mstatus with the interrupt enable bits used by the task. */
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load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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/* Load mstatus with the interrupt enable bits used by the task. */
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load_x t0, portMSTATUS_OFFSET * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
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load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
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store_x t0, 0( t1 ) /* Restore the critical nesting value for this task. */
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load_x t0, portCRITICAL_NESTING_OFFSET * portWORD_SIZE( sp ) /* Obtain xCriticalNesting value for this task from task's stack. */
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load_x t1, pxCriticalNesting /* Load the address of xCriticalNesting into t1. */
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store_x t0, 0 ( t1 ) /* Restore the critical nesting value for this task. */
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load_x x1, 1 * portWORD_SIZE( sp )
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load_x x5, 2 * portWORD_SIZE( sp )
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load_x x6, 3 * portWORD_SIZE( sp )
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load_x x7, 4 * portWORD_SIZE( sp )
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load_x x8, 5 * portWORD_SIZE( sp )
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load_x x9, 6 * portWORD_SIZE( sp )
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load_x x10, 7 * portWORD_SIZE( sp )
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load_x x11, 8 * portWORD_SIZE( sp )
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load_x x12, 9 * portWORD_SIZE( sp )
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load_x x13, 10 * portWORD_SIZE( sp )
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load_x x14, 11 * portWORD_SIZE( sp )
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load_x x15, 12 * portWORD_SIZE( sp )
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load_x x1, 1 * portWORD_SIZE( sp )
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load_x x5, 2 * portWORD_SIZE( sp )
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load_x x6, 3 * portWORD_SIZE( sp )
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load_x x7, 4 * portWORD_SIZE( sp )
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load_x x8, 5 * portWORD_SIZE( sp )
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load_x x9, 6 * portWORD_SIZE( sp )
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load_x x10, 7 * portWORD_SIZE( sp )
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load_x x11, 8 * portWORD_SIZE( sp )
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load_x x12, 9 * portWORD_SIZE( sp )
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load_x x13, 10 * portWORD_SIZE( sp )
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load_x x14, 11 * portWORD_SIZE( sp )
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load_x x15, 12 * portWORD_SIZE( sp )
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#ifndef __riscv_32e
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load_x x16, 13 * portWORD_SIZE( sp )
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load_x x17, 14 * portWORD_SIZE( sp )
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load_x x18, 15 * portWORD_SIZE( sp )
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load_x x19, 16 * portWORD_SIZE( sp )
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load_x x20, 17 * portWORD_SIZE( sp )
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load_x x21, 18 * portWORD_SIZE( sp )
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load_x x22, 19 * portWORD_SIZE( sp )
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load_x x23, 20 * portWORD_SIZE( sp )
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load_x x24, 21 * portWORD_SIZE( sp )
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load_x x25, 22 * portWORD_SIZE( sp )
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load_x x26, 23 * portWORD_SIZE( sp )
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load_x x27, 24 * portWORD_SIZE( sp )
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load_x x28, 25 * portWORD_SIZE( sp )
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load_x x29, 26 * portWORD_SIZE( sp )
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load_x x30, 27 * portWORD_SIZE( sp )
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load_x x31, 28 * portWORD_SIZE( sp )
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#endif
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addi sp, sp, portCONTEXT_SIZE
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load_x x16, 13 * portWORD_SIZE( sp )
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load_x x17, 14 * portWORD_SIZE( sp )
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load_x x18, 15 * portWORD_SIZE( sp )
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load_x x19, 16 * portWORD_SIZE( sp )
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load_x x20, 17 * portWORD_SIZE( sp )
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load_x x21, 18 * portWORD_SIZE( sp )
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load_x x22, 19 * portWORD_SIZE( sp )
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load_x x23, 20 * portWORD_SIZE( sp )
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load_x x24, 21 * portWORD_SIZE( sp )
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load_x x25, 22 * portWORD_SIZE( sp )
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load_x x26, 23 * portWORD_SIZE( sp )
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load_x x27, 24 * portWORD_SIZE( sp )
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load_x x28, 25 * portWORD_SIZE( sp )
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load_x x29, 26 * portWORD_SIZE( sp )
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load_x x30, 27 * portWORD_SIZE( sp )
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load_x x31, 28 * portWORD_SIZE( sp )
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#endif /* ifndef __riscv_32e */
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addi sp, sp, portCONTEXT_SIZE
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mret
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ENDM
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mret
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ENDM
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/*-----------------------------------------------------------*/
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#endif /* PORTCONTEXT_H */
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@ -50,85 +50,85 @@
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/* Type definitions. */
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#if __riscv_xlen == 64
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#define portSTACK_TYPE uint64_t
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#define portBASE_TYPE int64_t
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#define portUBASE_TYPE uint64_t
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#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
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#define portPOINTER_SIZE_TYPE uint64_t
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#define portSTACK_TYPE uint64_t
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#define portBASE_TYPE int64_t
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#define portUBASE_TYPE uint64_t
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#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
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#define portPOINTER_SIZE_TYPE uint64_t
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#elif __riscv_xlen == 32
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE int32_t
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#define portUBASE_TYPE uint32_t
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#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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#define portSTACK_TYPE uint32_t
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#define portBASE_TYPE int32_t
|
||||
#define portUBASE_TYPE uint32_t
|
||||
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||
#else /* if __riscv_xlen == 64 */
|
||||
#error "Assembler did not define __riscv_xlen"
|
||||
#endif /* if __riscv_xlen == 64 */
|
||||
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef portBASE_TYPE BaseType_t;
|
||||
typedef portUBASE_TYPE UBaseType_t;
|
||||
typedef portUBASE_TYPE TickType_t;
|
||||
typedef portSTACK_TYPE StackType_t;
|
||||
typedef portBASE_TYPE BaseType_t;
|
||||
typedef portUBASE_TYPE UBaseType_t;
|
||||
typedef portUBASE_TYPE TickType_t;
|
||||
|
||||
/* Legacy type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
|
||||
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||
* not need to be guarded with a critical section. */
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
#define portTICK_TYPE_IS_ATOMIC 1
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specifics. */
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||
#ifdef __riscv_32e
|
||||
#define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements. */
|
||||
#define portBYTE_ALIGNMENT 8 /* RV32E uses RISC-V EABI with reduced stack alignment requirements. */
|
||||
#else
|
||||
#define portBYTE_ALIGNMENT 16
|
||||
#define portBYTE_ALIGNMENT 16
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Scheduler utilities. */
|
||||
extern void vTaskSwitchContext( void );
|
||||
#define portYIELD() __asm volatile( "ecall" );
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext(); } while( 0 )
|
||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||
#define portYIELD() __asm volatile ( "ecall" );
|
||||
#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) vTaskSwitchContext( ); } while( 0 )
|
||||
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portCRITICAL_NESTING_IN_TCB 0
|
||||
#define portCRITICAL_NESTING_IN_TCB 0
|
||||
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() 0
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
|
||||
|
||||
#define portDISABLE_INTERRUPTS() __disable_interrupt()
|
||||
#define portENABLE_INTERRUPTS() __enable_interrupt()
|
||||
#define portDISABLE_INTERRUPTS() __disable_interrupt()
|
||||
#define portENABLE_INTERRUPTS() __enable_interrupt()
|
||||
|
||||
extern size_t xCriticalNesting;
|
||||
#define portENTER_CRITICAL() \
|
||||
{ \
|
||||
portDISABLE_INTERRUPTS(); \
|
||||
xCriticalNesting++; \
|
||||
}
|
||||
#define portENTER_CRITICAL() \
|
||||
{ \
|
||||
portDISABLE_INTERRUPTS(); \
|
||||
xCriticalNesting++; \
|
||||
}
|
||||
|
||||
#define portEXIT_CRITICAL() \
|
||||
{ \
|
||||
xCriticalNesting--; \
|
||||
if( xCriticalNesting == 0 ) \
|
||||
{ \
|
||||
portENABLE_INTERRUPTS(); \
|
||||
} \
|
||||
}
|
||||
#define portEXIT_CRITICAL() \
|
||||
{ \
|
||||
xCriticalNesting--; \
|
||||
if( xCriticalNesting == 0 ) \
|
||||
{ \
|
||||
portENABLE_INTERRUPTS(); \
|
||||
} \
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Architecture specific optimisations. */
|
||||
#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
|
||||
#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
|
||||
|
||||
#error configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated.
|
||||
#error "configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated."
|
||||
|
||||
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||
|
||||
|
|
@ -138,19 +138,19 @@ extern size_t xCriticalNesting;
|
|||
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
||||
* not necessary for to use this port. They are defined so the common demo
|
||||
* files (which build with all the ports) will build. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portNOP() __asm volatile( " nop " )
|
||||
#define portINLINE __inline
|
||||
#define portNOP() __asm volatile ( " nop " )
|
||||
#define portINLINE __inline
|
||||
|
||||
#ifndef portFORCE_INLINE
|
||||
#define portFORCE_INLINE inline __attribute__(( always_inline))
|
||||
#define portFORCE_INLINE inline __attribute__( ( always_inline ) )
|
||||
#endif
|
||||
|
||||
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
|
||||
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
|
||||
|
|
@ -163,20 +163,22 @@ extern size_t xCriticalNesting;
|
|||
* backward compatibility derive the newer definitions from the old if the old
|
||||
* definition is found. */
|
||||
#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
|
||||
/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
|
||||
* there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
|
||||
* addresses to 0. */
|
||||
#define configMTIME_BASE_ADDRESS ( 0 )
|
||||
#define configMTIMECMP_BASE_ADDRESS ( 0 )
|
||||
|
||||
/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
|
||||
* there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
|
||||
* addresses to 0. */
|
||||
#define configMTIME_BASE_ADDRESS ( 0 )
|
||||
#define configMTIMECMP_BASE_ADDRESS ( 0 )
|
||||
#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
|
||||
/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
|
||||
* the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
|
||||
* from the CLINT address. */
|
||||
#define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
|
||||
#define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
|
||||
|
||||
/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
|
||||
* the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
|
||||
* from the CLINT address. */
|
||||
#define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
|
||||
#define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
|
||||
#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
|
||||
#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||
#endif
|
||||
#error "configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html"
|
||||
#endif /* if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 ) */
|
||||
|
||||
/* *INDENT-OFF* */
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue