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283
portable/GCC/TriCore_1782/port.c
View file

@ -57,23 +57,23 @@
#define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
/* CSA manipulation macros. */
#define portCSA_FCX_MASK ( 0x000FFFFFUL )
#define portCSA_FCX_MASK ( 0x000FFFFFUL )
/* OS Interrupt and Trap mechanisms. */
#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
#define portSYSCALL_TRAP ( 6 )
#define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
#define portSYSCALL_TRAP ( 6 )
/* Each CSA contains 16 words of data. */
#define portNUM_WORDS_IN_CSA ( 16 )
#define portNUM_WORDS_IN_CSA ( 16 )
/* The interrupt enable bit in the PCP_SRC register. */
#define portENABLE_CPU_INTERRUPT ( 1U << 12U )
#define portENABLE_CPU_INTERRUPT ( 1U << 12U )
/*-----------------------------------------------------------*/
/*
* Perform any hardware configuration necessary to generate the tick interrupt.
*/
static void prvSystemTickHandler( int ) __attribute__((longcall));
static void prvSystemTickHandler( int ) __attribute__( ( longcall ) );
static void prvSetupTimerInterrupt( void );
/*
@ -89,37 +89,39 @@ static void prvInterruptYield( int iTrapIdentification );
/*-----------------------------------------------------------*/
/* This reference is required by the save/restore context macros. */
extern volatile uint32_t *pxCurrentTCB;
extern volatile uint32_t * pxCurrentTCB;
/* Precalculate the compare match value at compile time. */
static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
/*-----------------------------------------------------------*/
StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
TaskFunction_t pxCode,
void * pvParameters )
{
uint32_t *pulUpperCSA = NULL;
uint32_t *pulLowerCSA = NULL;
uint32_t * pulUpperCSA = NULL;
uint32_t * pulLowerCSA = NULL;
/* 16 Address Registers (4 Address registers are global), 16 Data
Registers, and 3 System Registers.
There are 3 registers that track the CSAs.
FCX points to the head of globally free set of CSAs.
PCX for the task needs to point to Lower->Upper->NULL arrangement.
LCX points to the last free CSA so that corrective action can be taken.
Need two CSAs to store the context of a task.
The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
The Lower Context points to the Upper Context ready for the return from the interrupt handler.
The Real stack pointer for the task is stored in the A10 which is restored
with the upper context. */
* Registers, and 3 System Registers.
*
* There are 3 registers that track the CSAs.
* FCX points to the head of globally free set of CSAs.
* PCX for the task needs to point to Lower->Upper->NULL arrangement.
* LCX points to the last free CSA so that corrective action can be taken.
*
* Need two CSAs to store the context of a task.
* The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
* The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
* The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
* The Lower Context points to the Upper Context ready for the return from the interrupt handler.
*
* The Real stack pointer for the task is stored in the A10 which is restored
* with the upper context. */
/* Have to disable interrupts here because the CSAs are going to be
manipulated. */
* manipulated. */
portENTER_CRITICAL();
{
/* DSync to ensure that buffering is not a problem. */
@ -127,6 +129,7 @@ uint32_t *pulLowerCSA = NULL;
/* Consume two free CSAs. */
pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
if( NULL != pulLowerCSA )
{
/* The Lower Links to the Upper. */
@ -155,21 +158,21 @@ uint32_t *pulLowerCSA = NULL;
memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
/* Upper Context. */
pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
pulUpperCSA[ 2 ] = ( uint32_t ) pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
/* Clear the lower CSA. */
memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
/* Lower Context. */
pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */
pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */
pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */
pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */
/* PCXI pointing to the Upper context. */
pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
/* Save the link to the CSA in the top of stack. */
pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
pxTopOfStack = ( uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
/* DSync to ensure that buffering is not a problem. */
_dsync();
@ -180,13 +183,13 @@ uint32_t *pulLowerCSA = NULL;
int32_t xPortStartScheduler( void )
{
extern void vTrapInstallHandlers( void );
uint32_t ulMFCR = 0UL;
uint32_t *pulUpperCSA = NULL;
uint32_t *pulLowerCSA = NULL;
extern void vTrapInstallHandlers( void );
uint32_t ulMFCR = 0UL;
uint32_t * pulUpperCSA = NULL;
uint32_t * pulLowerCSA = NULL;
/* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
when this function is called. */
* when this function is called. */
/* Set-up the timer interrupt. */
prvSetupTimerInterrupt();
@ -202,8 +205,9 @@ uint32_t *pulLowerCSA = NULL;
}
/* Enable then install the priority 1 interrupt for pending context
switches from an ISR. See mod_SRC in the TriCore manual. */
CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
* switches from an ISR. See mod_SRC in the TriCore manual. */
CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
{
/* Failed to install the yield handler, force an assert. */
@ -219,7 +223,7 @@ uint32_t *pulLowerCSA = NULL;
/* ENDINIT has already been applied in the 'cstart.c' code. */
/* Clear the PSW.CDC to enable the use of an RFE without it generating an
exception because this code is not genuinely in an exception. */
* exception because this code is not genuinely in an exception. */
ulMFCR = __MFCR( $PSW );
ulMFCR &= portRESTORE_PSW_MASK;
_dsync();
@ -228,7 +232,7 @@ uint32_t *pulLowerCSA = NULL;
/* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
_dsync();
_mtcr( $PCXI, *pxCurrentTCB );
_isync();
@ -237,7 +241,7 @@ uint32_t *pulLowerCSA = NULL;
_nop();
/* Return to the first task selected to execute. */
__asm volatile( "rfe" );
__asm volatile ( "rfe" );
/* Will not get here. */
return 0;
@ -250,7 +254,9 @@ static void prvSetupTimerInterrupt( void )
unlock_wdtcon();
{
/* Wait until access to Endint protected register is enabled. */
while( 0 != ( WDT_CON0.reg & 0x1UL ) );
while( 0 != ( WDT_CON0.reg & 0x1UL ) )
{
}
/* RMC == 1 so STM Clock == FPI */
STM_CLC.reg = ( 1UL << 8 );
@ -285,11 +291,11 @@ static void prvSetupTimerInterrupt( void )
static void prvSystemTickHandler( int iArg )
{
uint32_t ulSavedInterruptMask;
uint32_t *pxUpperCSA = NULL;
uint32_t xUpperCSA = 0UL;
extern volatile uint32_t *pxCurrentTCB;
int32_t lYieldRequired;
uint32_t ulSavedInterruptMask;
uint32_t * pxUpperCSA = NULL;
uint32_t xUpperCSA = 0UL;
extern volatile uint32_t * pxCurrentTCB;
int32_t lYieldRequired;
/* Just to avoid compiler warnings about unused parameters. */
( void ) iArg;
@ -298,22 +304,22 @@ int32_t lYieldRequired;
STM_ISRR.reg = 1UL;
/* Reload the Compare Match register for X ticks into the future.
If critical section or interrupt nesting budgets are exceeded, then
it is possible that the calculated next compare match value is in the
past. If this occurs (unlikely), it is possible that the resulting
time slippage will exceed a single tick period. Any adverse effect of
this is time bounded by the fact that only the first n bits of the 56 bit
STM timer are being used for a compare match, so another compare match
will occur after an overflow in just those n bits (not the entire 56 bits).
As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
a missed tick could result in the next tick interrupt occurring within a
time that is 1.7 times the desired period. The fact that this is greater
than a single tick period is an effect of using a timer that cannot be
automatically reset, in hardware, by the occurrence of a tick interrupt.
Changing the tick source to a timer that has an automatic reset on compare
match (such as a GPTA timer) will reduce the maximum possible additional
period to exactly 1 times the desired period. */
*
* If critical section or interrupt nesting budgets are exceeded, then
* it is possible that the calculated next compare match value is in the
* past. If this occurs (unlikely), it is possible that the resulting
* time slippage will exceed a single tick period. Any adverse effect of
* this is time bounded by the fact that only the first n bits of the 56 bit
* STM timer are being used for a compare match, so another compare match
* will occur after an overflow in just those n bits (not the entire 56 bits).
* As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
* a missed tick could result in the next tick interrupt occurring within a
* time that is 1.7 times the desired period. The fact that this is greater
* than a single tick period is an effect of using a timer that cannot be
* automatically reset, in hardware, by the occurrence of a tick interrupt.
* Changing the tick source to a timer that has an automatic reset on compare
* match (such as a GPTA timer) will reduce the maximum possible additional
* period to exactly 1 times the desired period. */
STM_CMP0.reg += ulCompareMatchValue;
/* Kernel API calls require Critical Sections. */
@ -327,24 +333,24 @@ int32_t lYieldRequired;
if( lYieldRequired != pdFALSE )
{
/* Save the context of a task.
The upper context is automatically saved when entering a trap or interrupt.
Need to save the lower context as well and copy the PCXI CSA ID into
pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
TCB of a task.
Call vTaskSwitchContext to select the next task, note that this changes the
value of pxCurrentTCB so that it needs to be reloaded.
Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
that has just been switched in.
Load the context of the task.
Need to restore the lower context by loading the CSA from
pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
In the Interrupt handler post-amble, RSLCX will restore the lower context
of the task. RFE will restore the upper context of the task, jump to the
return address and restore the previous state of interrupts being
enabled/disabled. */
* The upper context is automatically saved when entering a trap or interrupt.
* Need to save the lower context as well and copy the PCXI CSA ID into
* pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
* TCB of a task.
*
* Call vTaskSwitchContext to select the next task, note that this changes the
* value of pxCurrentTCB so that it needs to be reloaded.
*
* Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
* that has just been switched in.
*
* Load the context of the task.
* Need to restore the lower context by loading the CSA from
* pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
* In the Interrupt handler post-amble, RSLCX will restore the lower context
* of the task. RFE will restore the upper context of the task, jump to the
* return address and restore the previous state of interrupts being
* enabled/disabled. */
_disable();
_dsync();
xUpperCSA = __MFCR( $PCXI );
@ -376,34 +382,34 @@ int32_t lYieldRequired;
* than they can be freed assuming that tasks are being spawned and
* deleted frequently.
*/
void vPortReclaimCSA( uint32_t *pxTCB )
void vPortReclaimCSA( uint32_t * pxTCB )
{
uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
uint32_t *pulNextCSA;
uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
uint32_t * pulNextCSA;
/* A pointer to the first CSA in the list of CSAs consumed by the task is
stored in the first element of the tasks TCB structure (where the stack
pointer would be on a traditional stack based architecture). */
* stored in the first element of the tasks TCB structure (where the stack
* pointer would be on a traditional stack based architecture). */
pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
/* Mask off everything in the CSA link field other than the address. If
the address is NULL, then the CSA is not linking anywhere and there is
nothing to do. */
* the address is NULL, then the CSA is not linking anywhere and there is
* nothing to do. */
pxTailCSA = pxHeadCSA;
/* Convert the link value to contain just a raw address and store this
in a local variable. */
* in a local variable. */
pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
/* Iterate over the CSAs that were consumed as part of the task. The
first field in the CSA is the pointer to then next CSA. Mask off
everything in the pointer to the next CSA, other than the link address.
If this is NULL, then the CSA currently being pointed to is the last in
the chain. */
* first field in the CSA is the pointer to then next CSA. Mask off
* everything in the pointer to the next CSA, other than the link address.
* If this is NULL, then the CSA currently being pointed to is the last in
* the chain. */
while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
{
/* Clear all bits of the pointer to the next in the chain, other
than the address bits themselves. */
* than the address bits themselves. */
pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
/* Move the pointer to point to the next CSA in the list. */
@ -439,32 +445,33 @@ void vPortEndScheduler( void )
static void prvTrapYield( int iTrapIdentification )
{
uint32_t *pxUpperCSA = NULL;
uint32_t xUpperCSA = 0UL;
extern volatile uint32_t *pxCurrentTCB;
uint32_t * pxUpperCSA = NULL;
uint32_t xUpperCSA = 0UL;
extern volatile uint32_t * pxCurrentTCB;
switch( iTrapIdentification )
{
case portSYSCALL_TASK_YIELD:
/* Save the context of a task.
The upper context is automatically saved when entering a trap or interrupt.
Need to save the lower context as well and copy the PCXI CSA ID into
pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
TCB of a task.
Call vTaskSwitchContext to select the next task, note that this changes the
value of pxCurrentTCB so that it needs to be reloaded.
Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
that has just been switched in.
Load the context of the task.
Need to restore the lower context by loading the CSA from
pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
In the Interrupt handler post-amble, RSLCX will restore the lower context
of the task. RFE will restore the upper context of the task, jump to the
return address and restore the previous state of interrupts being
enabled/disabled. */
* The upper context is automatically saved when entering a trap or interrupt.
* Need to save the lower context as well and copy the PCXI CSA ID into
* pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
* TCB of a task.
*
* Call vTaskSwitchContext to select the next task, note that this changes the
* value of pxCurrentTCB so that it needs to be reloaded.
*
* Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
* that has just been switched in.
*
* Load the context of the task.
* Need to restore the lower context by loading the CSA from
* pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
* In the Interrupt handler post-amble, RSLCX will restore the lower context
* of the task. RFE will restore the upper context of the task, jump to the
* return address and restore the previous state of interrupts being
* enabled/disabled. */
_disable();
_dsync();
xUpperCSA = __MFCR( $PCXI );
@ -486,32 +493,32 @@ extern volatile uint32_t *pxCurrentTCB;
static void prvInterruptYield( int iId )
{
uint32_t *pxUpperCSA = NULL;
uint32_t xUpperCSA = 0UL;
extern volatile uint32_t *pxCurrentTCB;
uint32_t * pxUpperCSA = NULL;
uint32_t xUpperCSA = 0UL;
extern volatile uint32_t * pxCurrentTCB;
/* Just to remove compiler warnings. */
( void ) iId;
/* Save the context of a task.
The upper context is automatically saved when entering a trap or interrupt.
Need to save the lower context as well and copy the PCXI CSA ID into
pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
TCB of a task.
Call vTaskSwitchContext to select the next task, note that this changes the
value of pxCurrentTCB so that it needs to be reloaded.
Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
that has just been switched in.
Load the context of the task.
Need to restore the lower context by loading the CSA from
pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
In the Interrupt handler post-amble, RSLCX will restore the lower context
of the task. RFE will restore the upper context of the task, jump to the
return address and restore the previous state of interrupts being
enabled/disabled. */
* The upper context is automatically saved when entering a trap or interrupt.
* Need to save the lower context as well and copy the PCXI CSA ID into
* pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
* TCB of a task.
*
* Call vTaskSwitchContext to select the next task, note that this changes the
* value of pxCurrentTCB so that it needs to be reloaded.
*
* Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
* that has just been switched in.
*
* Load the context of the task.
* Need to restore the lower context by loading the CSA from
* pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
* In the Interrupt handler post-amble, RSLCX will restore the lower context
* of the task. RFE will restore the upper context of the task, jump to the
* return address and restore the previous state of interrupts being
* enabled/disabled. */
_disable();
_dsync();
xUpperCSA = __MFCR( $PCXI );
@ -526,7 +533,7 @@ extern volatile uint32_t *pxCurrentTCB;
uint32_t uxPortSetInterruptMaskFromISR( void )
{
uint32_t uxReturn = 0UL;
uint32_t uxReturn = 0UL;
_disable();
uxReturn = __MFCR( $ICR );
@ -535,6 +542,6 @@ uint32_t uxReturn = 0UL;
_enable();
/* Return just the interrupt mask bits. */
return ( uxReturn & portCCPN_MASK );
return( uxReturn & portCCPN_MASK );
}
/*-----------------------------------------------------------*/

144
portable/GCC/TriCore_1782/portmacro.h
View file

@ -50,126 +50,132 @@
*/
/* Type definitions. */
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE long
#define portCHAR char
#define portFLOAT float
#define portDOUBLE double
#define portLONG long
#define portSHORT short
#define portSTACK_TYPE uint32_t
#define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t;
typedef unsigned long UBaseType_t;
typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t;
typedef unsigned long UBaseType_t;
#if( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff
#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff
#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1
#else
#error configTICK_TYPE_WIDTH_IN_BITS set to unsupported tick type width.
#endif
/*---------------------------------------------------------------------------*/
/* Architecture specifics. */
#define portSTACK_GROWTH ( -1 )
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 4
#define portNOP() __asm volatile( " nop " )
#define portCRITICAL_NESTING_IN_TCB 1
#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1
#define portSTACK_GROWTH ( -1 )
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portBYTE_ALIGNMENT 4
#define portNOP() __asm volatile ( " nop " )
#define portCRITICAL_NESTING_IN_TCB 1
#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL 1
/*---------------------------------------------------------------------------*/
typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
typedef struct MPU_SETTINGS
{
uint32_t ulNotUsed;
} xMPU_SETTINGS;
/* Define away the instruction from the Restore Context Macro. */
#define portPRIVILEGE_BIT 0x0UL
#define portPRIVILEGE_BIT 0x0UL
#define portCCPN_MASK ( 0x000000FFUL )
#define portCCPN_MASK ( 0x000000FFUL )
extern void vTaskEnterCritical( void );
extern void vTaskExitCritical( void );
#define portENTER_CRITICAL() vTaskEnterCritical()
#define portEXIT_CRITICAL() vTaskExitCritical()
#define portENTER_CRITICAL() vTaskEnterCritical()
#define portEXIT_CRITICAL() vTaskExitCritical()
/*---------------------------------------------------------------------------*/
/* CSA Manipulation. */
#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
#define portCSA_TO_ADDRESS( pCSA ) ( ( uint32_t * ) ( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
#define portADDRESS_TO_CSA( pAddress ) ( ( uint32_t ) ( ( ( ( ( uint32_t ) ( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t ) ( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
/*---------------------------------------------------------------------------*/
#define portYIELD() _syscall( 0 )
#define portYIELD() _syscall( 0 )
/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
#define portSYSCALL_TASK_YIELD 0
#define portSYSCALL_RAISE_PRIORITY 1
#define portSYSCALL_TASK_YIELD 0
#define portSYSCALL_RAISE_PRIORITY 1
/*---------------------------------------------------------------------------*/
/* Critical section management. */
/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
#define portDISABLE_INTERRUPTS() { \
uint32_t ulICR; \
_disable(); \
ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
_isync(); \
_enable(); \
}
#define portDISABLE_INTERRUPTS() \
{ \
uint32_t ulICR; \
_disable(); \
ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
_isync(); \
_enable(); \
}
/* Clear ICR.CCPN to allow all interrupt priorities. */
#define portENABLE_INTERRUPTS() { \
uint32_t ulICR; \
_disable(); \
ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
_isync(); \
_enable(); \
}
#define portENABLE_INTERRUPTS() \
{ \
uint32_t ulICR; \
_disable(); \
ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
_isync(); \
_enable(); \
}
/* Set ICR.CCPN to uxSavedMaskValue. */
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \
uint32_t ulICR; \
_disable(); \
ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
_isync(); \
_enable(); \
}
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) \
{ \
uint32_t ulICR; \
_disable(); \
ulICR = __MFCR( $ICR ); /* Get current ICR value. */ \
ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
_isync(); \
_enable(); \
}
/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
extern uint32_t uxPortSetInterruptMaskFromISR( void );
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
/* Pend a priority 1 interrupt, which will take care of the context switch. */
#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 )
#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) do { if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); } } while( 0 )
/*---------------------------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
/*---------------------------------------------------------------------------*/
/*
* Port specific clean up macro required to free the CSAs that were consumed by
* a task that has since been deleted.
*/
void vPortReclaimCSA( uint32_t *pxTCB );
#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
void vPortReclaimCSA( uint32_t * pxTCB );
#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
/* *INDENT-OFF* */
#ifdef __cplusplus

116
portable/GCC/TriCore_1782/porttrap.c
View file

@ -38,7 +38,7 @@
/*
* This reference is required by the Save/Restore Context Macros.
*/
extern volatile uint32_t *pxCurrentTCB;
extern volatile uint32_t * pxCurrentTCB;
/*-----------------------------------------------------------*/
/*
@ -51,57 +51,57 @@ extern volatile uint32_t *pxCurrentTCB;
*/
/* The Trap Classes. */
#define portMMU_TRAP 0
#define portIPT_TRAP 1
#define portIE_TRAP 2
#define portCM_TRAP 3
#define portSBP_TRAP 4
#define portASSERT_TRAP 5
#define portNMI_TRAP 7
#define portMMU_TRAP 0
#define portIPT_TRAP 1
#define portIE_TRAP 2
#define portCM_TRAP 3
#define portSBP_TRAP 4
#define portASSERT_TRAP 5
#define portNMI_TRAP 7
/* MMU Trap Identifications. */
#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
#define portTIN_MMU_VIRTUAL_ADDRESS_FILL 0
#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION 1
/* Internal Protection Trap Identifications. */
#define portTIN_IPT_PRIVILIGED_INSTRUCTION 1
#define portTIN_IPT_MEMORY_PROTECTION_READ 2
#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
#define portTIN_IPT_PRIVILEGED_INSTRUCTION 1
#define portTIN_IPT_MEMORY_PROTECTION_READ 2
#define portTIN_IPT_MEMORY_PROTECTION_WRITE 3
#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION 4
#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS 5
#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS 6
#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION 7
/* Instruction Error Trap Identifications. */
#define portTIN_IE_ILLEGAL_OPCODE 1
#define portTIN_IE_UNIMPLEMENTED_OPCODE 2
#define portTIN_IE_INVALID_OPERAND 3
#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
#define portTIN_IE_ILLEGAL_OPCODE 1
#define portTIN_IE_UNIMPLEMENTED_OPCODE 2
#define portTIN_IE_INVALID_OPERAND 3
#define portTIN_IE_DATA_ADDRESS_ALIGNMENT 4
#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS 5
/* Context Management Trap Identifications. */
#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
#define portTIN_CM_CALL_DEPTH_OVERFLOW 2
#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
#define portTIN_CM_CALL_STACK_UNDERFLOW 5
#define portTIN_CM_CONTEXT_TYPE 6
#define portTIN_CM_NESTING_ERROR 7
#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION 1
#define portTIN_CM_CALL_DEPTH_OVERFLOW 2
#define portTIN_CM_CALL_DEPTH_UNDEFLOW 3
#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW 4
#define portTIN_CM_CALL_STACK_UNDERFLOW 5
#define portTIN_CM_CONTEXT_TYPE 6
#define portTIN_CM_NESTING_ERROR 7
/* System Bus and Peripherals Trap Identifications. */
#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR 1
#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR 2
#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR 3
#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR 4
#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR 5
#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR 6
/* Assertion Trap Identifications. */
#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
#define portTIN_ASSERT_ARITHMETIC_OVERFLOW 1
#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW 2
/* Non-maskable Interrupt Trap Identifications. */
#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
#define portTIN_NMI_NON_MASKABLE_INTERRUPT 0
/*---------------------------------------------------------------------------*/
void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
@ -115,37 +115,37 @@ void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longc
void vTrapInstallHandlers( void )
{
if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
if( 0 == _install_trap_handler( portMMU_TRAP, vMMUTrap ) )
{
_debug();
}
if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
if( 0 == _install_trap_handler( portIPT_TRAP, vInternalProtectionTrap ) )
{
_debug();
}
if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
if( 0 == _install_trap_handler( portIE_TRAP, vInstructionErrorTrap ) )
{
_debug();
}
if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
if( 0 == _install_trap_handler( portCM_TRAP, vContextManagementTrap ) )
{
_debug();
}
if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
if( 0 == _install_trap_handler( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
{
_debug();
}
if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
if( 0 == _install_trap_handler( portASSERT_TRAP, vAssertionTrap ) )
{
_debug();
}
if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
if( 0 == _install_trap_handler( portNMI_TRAP, vNonMaskableInterruptTrap ) )
{
_debug();
}
@ -156,11 +156,11 @@ void vMMUTrap( int iTrapIdentification )
{
switch( iTrapIdentification )
{
case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
default:
_debug();
break;
case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
default:
_debug();
break;
}
}
/*---------------------------------------------------------------------------*/
@ -170,26 +170,26 @@ void vInternalProtectionTrap( int iTrapIdentification )
/* Deliberate fall through to default. */
switch( iTrapIdentification )
{
case portTIN_IPT_PRIVILIGED_INSTRUCTION:
/* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
case portTIN_IPT_PRIVILEGED_INSTRUCTION:
/* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
case portTIN_IPT_MEMORY_PROTECTION_READ:
/* Load word using invalid address. */
/* Load word using invalid address. */
case portTIN_IPT_MEMORY_PROTECTION_WRITE:
/* Store Word using invalid address. */
/* Store Word using invalid address. */
case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
/* PC jumped to an address outside of the valid range. */
/* PC jumped to an address outside of the valid range. */
case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
/* Access to a peripheral denied at current execution level. */
/* Access to a peripheral denied at current execution level. */
case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
/* NULL Pointer. */
/* NULL Pointer. */
case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
/* Tried to modify a global address pointer register. */
/* Tried to modify a global address pointer register. */
default: